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Timur Tabic59e1b42010-06-14 15:28:24 -05001/*
ramneek mehresh3d7506f2012-04-18 19:39:53 +00002 * Copyright 2010-2012 Freescale Semiconductor, Inc.
Timur Tabic59e1b42010-06-14 15:28:24 -05003 * Authors: Srikanth Srinivasan <srikanth.srinivasan@freescale.com>
4 * Timur Tabi <timur@freescale.com>
5 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
Timur Tabic59e1b42010-06-14 15:28:24 -05007 */
8
9#ifndef __CONFIG_H
10#define __CONFIG_H
11
12#include "../board/freescale/common/ics307_clk.h"
13
Jiang Yutang9899ac12011-01-24 18:21:15 +080014#ifdef CONFIG_36BIT
15#define CONFIG_PHYS_64BIT
16#endif
17
Matthew McClintockaf253602012-05-18 06:04:17 +000018#ifdef CONFIG_SDCARD
Ying Zhang7c8eea52013-08-16 15:16:12 +080019#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
20#define CONFIG_SPL_ENV_SUPPORT
21#define CONFIG_SPL_SERIAL_SUPPORT
22#define CONFIG_SPL_MMC_SUPPORT
23#define CONFIG_SPL_MMC_MINIMAL
24#define CONFIG_SPL_FLUSH_IMAGE
25#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
26#define CONFIG_SPL_LIBGENERIC_SUPPORT
27#define CONFIG_SPL_LIBCOMMON_SUPPORT
28#define CONFIG_SPL_I2C_SUPPORT
29#define CONFIG_FSL_LAW /* Use common FSL init code */
30#define CONFIG_SYS_TEXT_BASE 0x11001000
31#define CONFIG_SPL_TEXT_BASE 0xf8f81000
Ying Zhangee4d6512014-01-24 15:50:06 +080032#define CONFIG_SPL_PAD_TO 0x20000
33#define CONFIG_SPL_MAX_SIZE (128 * 1024)
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +053034#define CONFIG_SYS_MMC_U_BOOT_SIZE (768 << 10)
Ying Zhang7c8eea52013-08-16 15:16:12 +080035#define CONFIG_SYS_MMC_U_BOOT_DST (0x11000000)
36#define CONFIG_SYS_MMC_U_BOOT_START (0x11000000)
Ying Zhangee4d6512014-01-24 15:50:06 +080037#define CONFIG_SYS_MMC_U_BOOT_OFFS (128 << 10)
Ying Zhang7c8eea52013-08-16 15:16:12 +080038#define CONFIG_SYS_MPC85XX_NO_RESETVEC
39#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
40#define CONFIG_SPL_MMC_BOOT
41#ifdef CONFIG_SPL_BUILD
42#define CONFIG_SPL_COMMON_INIT_DDR
43#endif
Matthew McClintockaf253602012-05-18 06:04:17 +000044#endif
45
46#ifdef CONFIG_SPIFLASH
Ying Zhang382ce7e2013-08-16 15:16:14 +080047#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
48#define CONFIG_SPL_ENV_SUPPORT
49#define CONFIG_SPL_SERIAL_SUPPORT
50#define CONFIG_SPL_SPI_SUPPORT
51#define CONFIG_SPL_SPI_FLASH_SUPPORT
52#define CONFIG_SPL_SPI_FLASH_MINIMAL
53#define CONFIG_SPL_FLUSH_IMAGE
54#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
55#define CONFIG_SPL_LIBGENERIC_SUPPORT
56#define CONFIG_SPL_LIBCOMMON_SUPPORT
57#define CONFIG_SPL_I2C_SUPPORT
58#define CONFIG_FSL_LAW /* Use common FSL init code */
59#define CONFIG_SYS_TEXT_BASE 0x11001000
60#define CONFIG_SPL_TEXT_BASE 0xf8f81000
Ying Zhangee4d6512014-01-24 15:50:06 +080061#define CONFIG_SPL_PAD_TO 0x20000
62#define CONFIG_SPL_MAX_SIZE (128 * 1024)
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +053063#define CONFIG_SYS_SPI_FLASH_U_BOOT_SIZE (768 << 10)
Ying Zhang382ce7e2013-08-16 15:16:14 +080064#define CONFIG_SYS_SPI_FLASH_U_BOOT_DST (0x11000000)
65#define CONFIG_SYS_SPI_FLASH_U_BOOT_START (0x11000000)
Ying Zhangee4d6512014-01-24 15:50:06 +080066#define CONFIG_SYS_SPI_FLASH_U_BOOT_OFFS (128 << 10)
Ying Zhang382ce7e2013-08-16 15:16:14 +080067#define CONFIG_SYS_MPC85XX_NO_RESETVEC
68#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot.lds"
69#define CONFIG_SPL_SPI_BOOT
70#ifdef CONFIG_SPL_BUILD
71#define CONFIG_SPL_COMMON_INIT_DDR
72#endif
Matthew McClintockaf253602012-05-18 06:04:17 +000073#endif
74
Matthew McClintockf45210d2013-02-18 10:02:19 +000075#define CONFIG_NAND_FSL_ELBC
York Sun9407c3f2013-12-17 11:21:08 -080076#define CONFIG_SYS_NAND_MAX_ECCPOS 56
77#define CONFIG_SYS_NAND_MAX_OOBFREE 5
Matthew McClintockf45210d2013-02-18 10:02:19 +000078
79#ifdef CONFIG_NAND
Ying Zhang5d97fe22013-08-16 15:16:16 +080080#ifdef CONFIG_TPL_BUILD
81#define CONFIG_SPL_NAND_BOOT
82#define CONFIG_SPL_FLUSH_IMAGE
83#define CONFIG_SPL_ENV_SUPPORT
84#define CONFIG_SPL_NAND_INIT
85#define CONFIG_SPL_SERIAL_SUPPORT
86#define CONFIG_SPL_LIBGENERIC_SUPPORT
87#define CONFIG_SPL_LIBCOMMON_SUPPORT
88#define CONFIG_SPL_I2C_SUPPORT
89#define CONFIG_SPL_NAND_SUPPORT
90#define CONFIG_SPL_MPC8XXX_INIT_DDR_SUPPORT
91#define CONFIG_SPL_COMMON_INIT_DDR
92#define CONFIG_SPL_MAX_SIZE (128 << 10)
93#define CONFIG_SPL_TEXT_BASE 0xf8f81000
94#define CONFIG_SYS_MPC85XX_NO_RESETVEC
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +053095#define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10)
Ying Zhang5d97fe22013-08-16 15:16:16 +080096#define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000)
97#define CONFIG_SYS_NAND_U_BOOT_START (0x11000000)
98#define CONFIG_SYS_NAND_U_BOOT_OFFS ((128 + 128) << 10)
99#elif defined(CONFIG_SPL_BUILD)
Matthew McClintockf45210d2013-02-18 10:02:19 +0000100#define CONFIG_SPL_INIT_MINIMAL
101#define CONFIG_SPL_SERIAL_SUPPORT
102#define CONFIG_SPL_NAND_SUPPORT
Matthew McClintockf45210d2013-02-18 10:02:19 +0000103#define CONFIG_SPL_FLUSH_IMAGE
Ying Zhang5d97fe22013-08-16 15:16:16 +0800104#define CONFIG_SPL_TEXT_BASE 0xff800000
105#define CONFIG_SPL_MAX_SIZE 4096
106#define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10)
107#define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000
108#define CONFIG_SYS_NAND_U_BOOT_START 0xf8f80000
109#define CONFIG_SYS_NAND_U_BOOT_OFFS (128 << 10)
110#endif
111#define CONFIG_SPL_PAD_TO 0x20000
112#define CONFIG_TPL_PAD_TO 0x20000
113#define CONFIG_SPL_TARGET "u-boot-with-spl.bin"
114#define CONFIG_SYS_TEXT_BASE 0x11001000
115#define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds"
Matthew McClintockf45210d2013-02-18 10:02:19 +0000116#endif
117
Timur Tabic59e1b42010-06-14 15:28:24 -0500118/* High Level Configuration Options */
119#define CONFIG_BOOKE /* BOOKE */
120#define CONFIG_E500 /* BOOKE e500 family */
Timur Tabic59e1b42010-06-14 15:28:24 -0500121#define CONFIG_P1022
122#define CONFIG_P1022DS
123#define CONFIG_MP /* support multiple processors */
124
Wolfgang Denk2ae18242010-10-06 09:05:45 +0200125#ifndef CONFIG_SYS_TEXT_BASE
Prabhakar Kushwahae222b1f2014-01-14 11:34:26 +0530126#define CONFIG_SYS_TEXT_BASE 0xeff40000
Wolfgang Denk2ae18242010-10-06 09:05:45 +0200127#endif
128
Kumar Gala7a577fd2011-01-12 02:48:53 -0600129#ifndef CONFIG_RESET_VECTOR_ADDRESS
130#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
131#endif
132
Timur Tabic59e1b42010-06-14 15:28:24 -0500133#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */
134#define CONFIG_PCI /* Enable PCI/PCIE */
135#define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */
136#define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */
137#define CONFIG_PCIE3 /* PCIE controler 3 (ULI bridge) */
138#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
139#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */
140#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
141
Timur Tabic59e1b42010-06-14 15:28:24 -0500142#define CONFIG_ENABLE_36BIT_PHYS
Timur Tabibabb3482011-09-06 09:36:06 -0500143
144#ifdef CONFIG_PHYS_64BIT
Timur Tabic59e1b42010-06-14 15:28:24 -0500145#define CONFIG_ADDR_MAP
146#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */
Jiang Yutang9899ac12011-01-24 18:21:15 +0800147#endif
Timur Tabic59e1b42010-06-14 15:28:24 -0500148
149#define CONFIG_FSL_LAW /* Use common FSL init code */
150
151#define CONFIG_SYS_CLK_FREQ get_board_sys_clk()
152#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk()
153#define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */
154
155/*
156 * These can be toggled for performance analysis, otherwise use default.
157 */
158#define CONFIG_L2_CACHE
159#define CONFIG_BTB
160
161#define CONFIG_SYS_MEMTEST_START 0x00000000
162#define CONFIG_SYS_MEMTEST_END 0x7fffffff
163
Timur Tabie46fedf2011-08-04 18:03:41 -0500164#define CONFIG_SYS_CCSRBAR 0xffe00000
165#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
Timur Tabic59e1b42010-06-14 15:28:24 -0500166
Matthew McClintockf45210d2013-02-18 10:02:19 +0000167/* IN case of NAND bootloader relocate CCSRBAR in RAMboot code not in the 4k
168 SPL code*/
169#ifdef CONFIG_SPL_BUILD
170#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE
171#endif
172
173
Timur Tabic59e1b42010-06-14 15:28:24 -0500174/* DDR Setup */
175#define CONFIG_DDR_SPD
176#define CONFIG_VERY_BIG_RAM
York Sun5614e712013-09-30 09:22:09 -0700177#define CONFIG_SYS_FSL_DDR3
Timur Tabic59e1b42010-06-14 15:28:24 -0500178
179#ifdef CONFIG_DDR_ECC
180#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
181#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
182#endif
183
184#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
185#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
186
187#define CONFIG_NUM_DDR_CONTROLLERS 1
188#define CONFIG_DIMM_SLOTS_PER_CTLR 1
189#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
190
191/* I2C addresses of SPD EEPROMs */
192#define CONFIG_SYS_SPD_BUS_NUM 1
Kumar Galac39f44d2011-01-31 22:18:47 -0600193#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */
Timur Tabic59e1b42010-06-14 15:28:24 -0500194
Matthew McClintockf45210d2013-02-18 10:02:19 +0000195/* These are used when DDR doesn't use SPD. */
196#define CONFIG_SYS_SDRAM_SIZE 2048
197#define CONFIG_SYS_SDRAM_SIZE_LAW LAW_SIZE_2G
198#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003F
199#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014202
200#define CONFIG_SYS_DDR_CS1_BNDS 0x0040007F
201#define CONFIG_SYS_DDR_CS1_CONFIG 0x80014202
202#define CONFIG_SYS_DDR_TIMING_3 0x00010000
203#define CONFIG_SYS_DDR_TIMING_0 0x40110104
204#define CONFIG_SYS_DDR_TIMING_1 0x5c5bd746
205#define CONFIG_SYS_DDR_TIMING_2 0x0fa8d4ca
206#define CONFIG_SYS_DDR_MODE_1 0x00441221
207#define CONFIG_SYS_DDR_MODE_2 0x00000000
208#define CONFIG_SYS_DDR_INTERVAL 0x0a280100
209#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef
210#define CONFIG_SYS_DDR_CLK_CTRL 0x02800000
211#define CONFIG_SYS_DDR_CONTROL 0xc7000008
212#define CONFIG_SYS_DDR_CONTROL_2 0x24401041
213#define CONFIG_SYS_DDR_TIMING_4 0x00220001
214#define CONFIG_SYS_DDR_TIMING_5 0x02401400
215#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600
216#define CONFIG_SYS_DDR_WRLVL_CONTROL 0x8675f608
217
218
Timur Tabic59e1b42010-06-14 15:28:24 -0500219/*
220 * Memory map
221 *
222 * 0x0000_0000 0x7fff_ffff DDR 2G Cacheable
223 * 0x8000_0000 0xdfff_ffff PCI Express Mem 1.5G non-cacheable
224 * 0xffc0_0000 0xffc2_ffff PCI IO range 192K non-cacheable
225 *
226 * Localbus cacheable (TBD)
227 * 0xXXXX_XXXX 0xXXXX_XXXX SRAM YZ M Cacheable
228 *
229 * Localbus non-cacheable
230 * 0xe000_0000 0xe80f_ffff Promjet/free 128M non-cacheable
231 * 0xe800_0000 0xefff_ffff FLASH 128M non-cacheable
Matthew McClintockf45210d2013-02-18 10:02:19 +0000232 * 0xff80_0000 0xff80_7fff NAND 32K non-cacheable
Timur Tabic59e1b42010-06-14 15:28:24 -0500233 * 0xffdf_0000 0xffdf_7fff PIXIS 32K non-cacheable TLB0
234 * 0xffd0_0000 0xffd0_3fff L1 for stack 16K Cacheable TLB0
235 * 0xffe0_0000 0xffef_ffff CCSR 1M non-cacheable
236 */
237
238/*
239 * Local Bus Definitions
240 */
Matthew McClintockf45210d2013-02-18 10:02:19 +0000241#define CONFIG_SYS_FLASH_BASE 0xe8000000 /* start of FLASH 128M */
Jiang Yutang9899ac12011-01-24 18:21:15 +0800242#ifdef CONFIG_PHYS_64BIT
Matthew McClintockf45210d2013-02-18 10:02:19 +0000243#define CONFIG_SYS_FLASH_BASE_PHYS 0xfe8000000ull
Jiang Yutang9899ac12011-01-24 18:21:15 +0800244#else
245#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
246#endif
Timur Tabic59e1b42010-06-14 15:28:24 -0500247
248#define CONFIG_FLASH_BR_PRELIM \
Matthew McClintockf45210d2013-02-18 10:02:19 +0000249 (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
Timur Tabic59e1b42010-06-14 15:28:24 -0500250#define CONFIG_FLASH_OR_PRELIM (OR_AM_128MB | 0xff7)
251
Matthew McClintockf45210d2013-02-18 10:02:19 +0000252#ifdef CONFIG_NAND
253#define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
254#define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
255#else
Timur Tabic59e1b42010-06-14 15:28:24 -0500256#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
257#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
Matthew McClintockf45210d2013-02-18 10:02:19 +0000258#endif
Timur Tabic59e1b42010-06-14 15:28:24 -0500259
Matthew McClintockf45210d2013-02-18 10:02:19 +0000260#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
Timur Tabic59e1b42010-06-14 15:28:24 -0500261#define CONFIG_SYS_FLASH_QUIET_TEST
262#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
263
Matthew McClintockf45210d2013-02-18 10:02:19 +0000264#define CONFIG_SYS_MAX_FLASH_BANKS 1
Timur Tabic59e1b42010-06-14 15:28:24 -0500265#define CONFIG_SYS_MAX_FLASH_SECT 1024
266
Matthew McClintockf45210d2013-02-18 10:02:19 +0000267#ifndef CONFIG_SYS_MONITOR_BASE
268#ifdef CONFIG_SPL_BUILD
269#define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE
270#else
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200271#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Matthew McClintockf45210d2013-02-18 10:02:19 +0000272#endif
273#endif
Timur Tabic59e1b42010-06-14 15:28:24 -0500274
275#define CONFIG_FLASH_CFI_DRIVER
276#define CONFIG_SYS_FLASH_CFI
277#define CONFIG_SYS_FLASH_EMPTY_INFO
278
Matthew McClintockf45210d2013-02-18 10:02:19 +0000279/* Nand Flash */
280#if defined(CONFIG_NAND_FSL_ELBC)
281#define CONFIG_SYS_NAND_BASE 0xff800000
282#ifdef CONFIG_PHYS_64BIT
283#define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull
284#else
285#define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE
286#endif
287
Ying Zhang5d97fe22013-08-16 15:16:16 +0800288#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE}
Matthew McClintockf45210d2013-02-18 10:02:19 +0000289#define CONFIG_SYS_MAX_NAND_DEVICE 1
290#define CONFIG_MTD_NAND_VERIFY_WRITE
291#define CONFIG_CMD_NAND 1
Ying Zhang5d97fe22013-08-16 15:16:16 +0800292#define CONFIG_SYS_NAND_BLOCK_SIZE (256 * 1024)
Matthew McClintockf45210d2013-02-18 10:02:19 +0000293#define CONFIG_ELBC_NAND_SPL_STATIC_PGSIZE
294
295/* NAND flash config */
296#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
297 | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
298 | BR_PS_8 /* Port Size = 8 bit */ \
299 | BR_MS_FCM /* MSEL = FCM */ \
300 | BR_V) /* valid */
301#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB /* length 256K */ \
302 | OR_FCM_PGS /* Large Page*/ \
303 | OR_FCM_CSCT \
304 | OR_FCM_CST \
305 | OR_FCM_CHT \
306 | OR_FCM_SCY_1 \
307 | OR_FCM_TRLX \
308 | OR_FCM_EHTR)
309#ifdef CONFIG_NAND
310#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
311#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
312#else
313#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
314#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
315#endif
316
317#endif /* CONFIG_NAND_FSL_ELBC */
318
Timur Tabic59e1b42010-06-14 15:28:24 -0500319#define CONFIG_BOARD_EARLY_INIT_F
320#define CONFIG_BOARD_EARLY_INIT_R
321#define CONFIG_MISC_INIT_R
Timur Tabia2d12f82010-07-21 16:56:19 -0500322#define CONFIG_HWCONFIG
Timur Tabic59e1b42010-06-14 15:28:24 -0500323
324#define CONFIG_FSL_NGPIXIS
325#define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
Jiang Yutang9899ac12011-01-24 18:21:15 +0800326#ifdef CONFIG_PHYS_64BIT
Timur Tabic59e1b42010-06-14 15:28:24 -0500327#define PIXIS_BASE_PHYS 0xfffdf0000ull
Jiang Yutang9899ac12011-01-24 18:21:15 +0800328#else
329#define PIXIS_BASE_PHYS PIXIS_BASE
330#endif
Timur Tabic59e1b42010-06-14 15:28:24 -0500331
332#define CONFIG_SYS_BR2_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
333#define CONFIG_SYS_OR2_PRELIM (OR_AM_32KB | 0x6ff7)
334
335#define PIXIS_LBMAP_SWITCH 7
York Sun29068452011-01-26 10:30:00 -0800336#define PIXIS_LBMAP_MASK 0xF0
Timur Tabic59e1b42010-06-14 15:28:24 -0500337#define PIXIS_LBMAP_ALTBANK 0x20
Matthew McClintockf45210d2013-02-18 10:02:19 +0000338#define PIXIS_SPD 0x07
339#define PIXIS_SPD_SYSCLK_MASK 0x07
Jiang Yutang9b6e9d12011-02-24 16:11:56 +0800340#define PIXIS_ELBC_SPI_MASK 0xc0
341#define PIXIS_SPI 0x80
Timur Tabic59e1b42010-06-14 15:28:24 -0500342
343#define CONFIG_SYS_INIT_RAM_LOCK
344#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200345#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */
Timur Tabic59e1b42010-06-14 15:28:24 -0500346
Timur Tabic59e1b42010-06-14 15:28:24 -0500347#define CONFIG_SYS_GBL_DATA_OFFSET \
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200348 (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Timur Tabic59e1b42010-06-14 15:28:24 -0500349#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
350
Prabhakar Kushwaha9307cba2014-03-31 15:31:48 +0530351#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
Jerry Huang07b5edc2011-11-02 09:16:44 +0800352#define CONFIG_SYS_MALLOC_LEN (10 * 1024 * 1024)
Timur Tabic59e1b42010-06-14 15:28:24 -0500353
354/*
Ying Zhang7c8eea52013-08-16 15:16:12 +0800355 * Config the L2 Cache as L2 SRAM
356*/
357#if defined(CONFIG_SPL_BUILD)
Ying Zhang382ce7e2013-08-16 15:16:14 +0800358#if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH)
Ying Zhang7c8eea52013-08-16 15:16:12 +0800359#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
360#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
361#define CONFIG_SYS_L2_SIZE (256 << 10)
362#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
363#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
Ying Zhang27585bd2014-01-24 15:50:08 +0800364#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 116 * 1024)
Ying Zhang7c8eea52013-08-16 15:16:12 +0800365#define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10)
Ying Zhang27585bd2014-01-24 15:50:08 +0800366#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 148 * 1024)
367#define CONFIG_SPL_RELOC_MALLOC_SIZE (108 << 10)
Ying Zhang7c8eea52013-08-16 15:16:12 +0800368#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024)
Ying Zhang5d97fe22013-08-16 15:16:16 +0800369#elif defined(CONFIG_NAND)
370#ifdef CONFIG_TPL_BUILD
371#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
372#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
373#define CONFIG_SYS_L2_SIZE (256 << 10)
374#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
375#define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000
376#define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 192 * 1024)
377#define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 208 * 1024)
378#define CONFIG_SPL_RELOC_MALLOC_SIZE (48 << 10)
379#define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 176 * 1024)
380#else
381#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000
382#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR
383#define CONFIG_SYS_L2_SIZE (256 << 10)
384#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE)
385#define CONFIG_SPL_RELOC_TEXT_BASE (CONFIG_SYS_INIT_L2_END - 0x2000)
386#define CONFIG_SPL_RELOC_STACK ((CONFIG_SYS_INIT_L2_END - 1) & ~0xF)
387#endif
Ying Zhang7c8eea52013-08-16 15:16:12 +0800388#endif
389#endif
390
391/*
Timur Tabic59e1b42010-06-14 15:28:24 -0500392 * Serial Port
393 */
394#define CONFIG_CONS_INDEX 1
395#define CONFIG_SYS_NS16550
396#define CONFIG_SYS_NS16550_SERIAL
397#define CONFIG_SYS_NS16550_REG_SIZE 1
398#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Ying Zhang7c8eea52013-08-16 15:16:12 +0800399#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_INIT_MINIMAL)
Matthew McClintockf45210d2013-02-18 10:02:19 +0000400#define CONFIG_NS16550_MIN_FUNCTIONS
401#endif
Timur Tabic59e1b42010-06-14 15:28:24 -0500402
403#define CONFIG_SYS_BAUDRATE_TABLE \
404 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
405
406#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
407#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
408
409/* Use the HUSH parser */
410#define CONFIG_SYS_HUSH_PARSER
Timur Tabic59e1b42010-06-14 15:28:24 -0500411
Timur Tabic59e1b42010-06-14 15:28:24 -0500412/* Video */
Timur Tabiba8e76b2011-04-11 14:18:22 -0500413
Timur Tabid5e01e42010-09-24 01:25:53 +0200414#ifdef CONFIG_FSL_DIU_FB
415#define CONFIG_SYS_DIU_ADDR (CONFIG_SYS_CCSRBAR + 0x10000)
416#define CONFIG_VIDEO
417#define CONFIG_CMD_BMP
Timur Tabic59e1b42010-06-14 15:28:24 -0500418#define CONFIG_CFB_CONSOLE
Timur Tabi7d3053f2011-02-15 17:09:19 -0600419#define CONFIG_VIDEO_SW_CURSOR
Timur Tabic59e1b42010-06-14 15:28:24 -0500420#define CONFIG_VGA_AS_SINGLE_DEVICE
Timur Tabid5e01e42010-09-24 01:25:53 +0200421#define CONFIG_VIDEO_LOGO
422#define CONFIG_VIDEO_BMP_LOGO
Timur Tabi55b05232010-09-16 16:35:44 -0500423#define CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS
424/*
425 * With CONFIG_CFI_FLASH_USE_WEAK_ACCESSORS, flash I/O is really slow, so
426 * disable empty flash sector detection, which is I/O-intensive.
427 */
428#undef CONFIG_SYS_FLASH_EMPTY_INFO
Timur Tabic59e1b42010-06-14 15:28:24 -0500429#endif
430
Timur Tabiba8e76b2011-04-11 14:18:22 -0500431#ifndef CONFIG_FSL_DIU_FB
Jiang Yutang218a7582011-01-24 18:21:19 +0800432#endif
433
434#ifdef CONFIG_ATI
435#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT
436#define CONFIG_VIDEO
437#define CONFIG_BIOSEMU
438#define CONFIG_VIDEO_SW_CURSOR
439#define CONFIG_ATI_RADEON_FB
440#define CONFIG_VIDEO_LOGO
441#define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET
442#define CONFIG_CFB_CONSOLE
443#define CONFIG_VGA_AS_SINGLE_DEVICE
444#endif
445
Timur Tabic59e1b42010-06-14 15:28:24 -0500446/*
447 * Pass open firmware flat tree
448 */
449#define CONFIG_OF_LIBFDT
450#define CONFIG_OF_BOARD_SETUP
451#define CONFIG_OF_STDOUT_VIA_ALIAS
452
453/* new uImage format support */
454#define CONFIG_FIT
455#define CONFIG_FIT_VERBOSE
456
457/* I2C */
Heiko Schocher00f792e2012-10-24 13:48:22 +0200458#define CONFIG_SYS_I2C
459#define CONFIG_SYS_I2C_FSL
460#define CONFIG_SYS_FSL_I2C_SPEED 400000
461#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
462#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
463#define CONFIG_SYS_FSL_I2C2_SPEED 400000
464#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
465#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100
Timur Tabic59e1b42010-06-14 15:28:24 -0500466#define CONFIG_SYS_I2C_NOPROBES {{0, 0x29}}
Timur Tabic59e1b42010-06-14 15:28:24 -0500467
468/*
469 * I2C2 EEPROM
470 */
471#define CONFIG_ID_EEPROM
472#define CONFIG_SYS_I2C_EEPROM_NXID
473#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
474#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
475#define CONFIG_SYS_EEPROM_BUS_NUM 1
476
477/*
Jiang Yutang9b6e9d12011-02-24 16:11:56 +0800478 * eSPI - Enhanced SPI
479 */
480#define CONFIG_SPI_FLASH
481#define CONFIG_SPI_FLASH_SPANSION
482
483#define CONFIG_HARD_SPI
484#define CONFIG_FSL_ESPI
485
486#define CONFIG_CMD_SF
487#define CONFIG_SF_DEFAULT_SPEED 10000000
488#define CONFIG_SF_DEFAULT_MODE 0
489
490/*
Timur Tabic59e1b42010-06-14 15:28:24 -0500491 * General PCI
492 * Memory space is mapped 1-1, but I/O space must start from 0.
493 */
494
495/* controller 1, Slot 2, tgtid 1, Base address a000 */
496#define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000
Jiang Yutang9899ac12011-01-24 18:21:15 +0800497#ifdef CONFIG_PHYS_64BIT
Timur Tabic59e1b42010-06-14 15:28:24 -0500498#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
499#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc40000000ull
Jiang Yutang9899ac12011-01-24 18:21:15 +0800500#else
501#define CONFIG_SYS_PCIE1_MEM_BUS 0xc0000000
502#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc0000000
503#endif
Timur Tabic59e1b42010-06-14 15:28:24 -0500504#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
505#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc20000
506#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
Jiang Yutang9899ac12011-01-24 18:21:15 +0800507#ifdef CONFIG_PHYS_64BIT
Timur Tabic59e1b42010-06-14 15:28:24 -0500508#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc20000ull
Jiang Yutang9899ac12011-01-24 18:21:15 +0800509#else
510#define CONFIG_SYS_PCIE1_IO_PHYS 0xffc20000
511#endif
Timur Tabic59e1b42010-06-14 15:28:24 -0500512#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
513
514/* controller 2, direct to uli, tgtid 2, Base address 9000 */
515#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
Jiang Yutang9899ac12011-01-24 18:21:15 +0800516#ifdef CONFIG_PHYS_64BIT
Timur Tabic59e1b42010-06-14 15:28:24 -0500517#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
518#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
Jiang Yutang9899ac12011-01-24 18:21:15 +0800519#else
520#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000
521#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000
522#endif
Timur Tabic59e1b42010-06-14 15:28:24 -0500523#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
524#define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000
525#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
Jiang Yutang9899ac12011-01-24 18:21:15 +0800526#ifdef CONFIG_PHYS_64BIT
Timur Tabic59e1b42010-06-14 15:28:24 -0500527#define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull
Jiang Yutang9899ac12011-01-24 18:21:15 +0800528#else
529#define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000
530#endif
Timur Tabic59e1b42010-06-14 15:28:24 -0500531#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
532
533/* controller 3, Slot 1, tgtid 3, Base address b000 */
534#define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000
Jiang Yutang9899ac12011-01-24 18:21:15 +0800535#ifdef CONFIG_PHYS_64BIT
Timur Tabic59e1b42010-06-14 15:28:24 -0500536#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
537#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc00000000ull
Jiang Yutang9899ac12011-01-24 18:21:15 +0800538#else
539#define CONFIG_SYS_PCIE3_MEM_BUS 0x80000000
540#define CONFIG_SYS_PCIE3_MEM_PHYS 0x80000000
541#endif
Timur Tabic59e1b42010-06-14 15:28:24 -0500542#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
543#define CONFIG_SYS_PCIE3_IO_VIRT 0xffc00000
544#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
Jiang Yutang9899ac12011-01-24 18:21:15 +0800545#ifdef CONFIG_PHYS_64BIT
Timur Tabic59e1b42010-06-14 15:28:24 -0500546#define CONFIG_SYS_PCIE3_IO_PHYS 0xfffc00000ull
Jiang Yutang9899ac12011-01-24 18:21:15 +0800547#else
548#define CONFIG_SYS_PCIE3_IO_PHYS 0xffc00000
549#endif
Timur Tabic59e1b42010-06-14 15:28:24 -0500550#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
551
552#ifdef CONFIG_PCI
Gabor Juhos842033e2013-05-30 07:06:12 +0000553#define CONFIG_PCI_INDIRECT_BRIDGE
Timur Tabic59e1b42010-06-14 15:28:24 -0500554#define CONFIG_PCI_PNP /* do pci plug-and-play */
555#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Kumar Gala16855ec2010-11-09 23:19:50 -0600556#define CONFIG_E1000 /* Define e1000 pci Ethernet card */
Timur Tabic59e1b42010-06-14 15:28:24 -0500557#endif
558
559/* SATA */
560#define CONFIG_LIBATA
561#define CONFIG_FSL_SATA
Zang Roy-R619119760b272012-11-26 00:05:38 +0000562#define CONFIG_FSL_SATA_V2
Timur Tabic59e1b42010-06-14 15:28:24 -0500563
564#define CONFIG_SYS_SATA_MAX_DEVICE 2
565#define CONFIG_SATA1
566#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
567#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
568#define CONFIG_SATA2
569#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
570#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
571
572#ifdef CONFIG_FSL_SATA
573#define CONFIG_LBA48
574#define CONFIG_CMD_SATA
575#define CONFIG_DOS_PARTITION
576#define CONFIG_CMD_EXT2
577#endif
578
579#define CONFIG_MMC
580#ifdef CONFIG_MMC
581#define CONFIG_CMD_MMC
582#define CONFIG_FSL_ESDHC
583#define CONFIG_GENERIC_MMC
584#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
585#endif
586
587#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI)
588#define CONFIG_CMD_EXT2
589#define CONFIG_CMD_FAT
590#define CONFIG_DOS_PARTITION
591#endif
592
593#define CONFIG_TSEC_ENET
594#ifdef CONFIG_TSEC_ENET
595
596#define CONFIG_TSECV2
Timur Tabic59e1b42010-06-14 15:28:24 -0500597
598#define CONFIG_MII /* MII PHY management */
599#define CONFIG_TSEC1 1
600#define CONFIG_TSEC1_NAME "eTSEC1"
601#define CONFIG_TSEC2 1
602#define CONFIG_TSEC2_NAME "eTSEC2"
603
604#define TSEC1_PHY_ADDR 1
605#define TSEC2_PHY_ADDR 2
606
607#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
608#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
609
610#define TSEC1_PHYIDX 0
611#define TSEC2_PHYIDX 0
612
613#define CONFIG_ETHPRIME "eTSEC1"
614
615#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
616#endif
617
618/*
619 * Environment
620 */
Ying Zhang382ce7e2013-08-16 15:16:14 +0800621#ifdef CONFIG_SPIFLASH
Matthew McClintockaf253602012-05-18 06:04:17 +0000622#define CONFIG_ENV_IS_IN_SPI_FLASH
623#define CONFIG_ENV_SPI_BUS 0
624#define CONFIG_ENV_SPI_CS 0
625#define CONFIG_ENV_SPI_MAX_HZ 10000000
626#define CONFIG_ENV_SPI_MODE 0
627#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
628#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
629#define CONFIG_ENV_SECT_SIZE 0x10000
Ying Zhang7c8eea52013-08-16 15:16:12 +0800630#elif defined(CONFIG_SDCARD)
Matthew McClintockaf253602012-05-18 06:04:17 +0000631#define CONFIG_ENV_IS_IN_MMC
Ying Zhang7c8eea52013-08-16 15:16:12 +0800632#define CONFIG_FSL_FIXED_MMC_LOCATION
Timur Tabic59e1b42010-06-14 15:28:24 -0500633#define CONFIG_ENV_SIZE 0x2000
Matthew McClintockaf253602012-05-18 06:04:17 +0000634#define CONFIG_SYS_MMC_ENV_DEV 0
Matthew McClintockf45210d2013-02-18 10:02:19 +0000635#elif defined(CONFIG_NAND)
Ying Zhang5d97fe22013-08-16 15:16:16 +0800636#ifdef CONFIG_TPL_BUILD
637#define CONFIG_ENV_SIZE 0x2000
638#define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10))
639#else
Matthew McClintockaf253602012-05-18 06:04:17 +0000640#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
Ying Zhang5d97fe22013-08-16 15:16:16 +0800641#endif
642#define CONFIG_ENV_IS_IN_NAND
643#define CONFIG_ENV_OFFSET (1024 * 1024)
Matthew McClintockaf253602012-05-18 06:04:17 +0000644#define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE)
Matthew McClintockf45210d2013-02-18 10:02:19 +0000645#elif defined(CONFIG_SYS_RAMBOOT)
Matthew McClintockaf253602012-05-18 06:04:17 +0000646#define CONFIG_ENV_IS_NOWHERE /* Store ENV in memory only */
647#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
648#define CONFIG_ENV_SIZE 0x2000
Matthew McClintockaf253602012-05-18 06:04:17 +0000649#else
650#define CONFIG_ENV_IS_IN_FLASH
Matthew McClintockaf253602012-05-18 06:04:17 +0000651#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
Matthew McClintockaf253602012-05-18 06:04:17 +0000652#define CONFIG_ENV_SIZE 0x2000
653#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
654#endif
Timur Tabic59e1b42010-06-14 15:28:24 -0500655
656#define CONFIG_LOADS_ECHO
657#define CONFIG_SYS_LOADS_BAUD_CHANGE
658
659/*
660 * Command line configuration.
661 */
662#include <config_cmd_default.h>
663
Kumar Gala79ee3442010-06-09 22:59:41 -0500664#define CONFIG_CMD_ELF
665#define CONFIG_CMD_ERRATA
Timur Tabic59e1b42010-06-14 15:28:24 -0500666#define CONFIG_CMD_IRQ
Timur Tabic59e1b42010-06-14 15:28:24 -0500667#define CONFIG_CMD_I2C
668#define CONFIG_CMD_MII
Kumar Gala79ee3442010-06-09 22:59:41 -0500669#define CONFIG_CMD_PING
Timur Tabic59e1b42010-06-14 15:28:24 -0500670#define CONFIG_CMD_SETEXPR
Matthew McClintockb8339e22010-12-17 17:26:41 -0600671#define CONFIG_CMD_REGINFO
Timur Tabic59e1b42010-06-14 15:28:24 -0500672
673#ifdef CONFIG_PCI
674#define CONFIG_CMD_PCI
675#define CONFIG_CMD_NET
676#endif
677
678/*
679 * USB
680 */
ramneek mehresh3d7506f2012-04-18 19:39:53 +0000681#define CONFIG_HAS_FSL_DR_USB
682#ifdef CONFIG_HAS_FSL_DR_USB
Timur Tabic59e1b42010-06-14 15:28:24 -0500683#define CONFIG_USB_EHCI
684
685#ifdef CONFIG_USB_EHCI
686#define CONFIG_CMD_USB
687#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
688#define CONFIG_USB_EHCI_FSL
689#define CONFIG_USB_STORAGE
690#define CONFIG_CMD_FAT
691#endif
ramneek mehresh3d7506f2012-04-18 19:39:53 +0000692#endif
Timur Tabic59e1b42010-06-14 15:28:24 -0500693
694/*
695 * Miscellaneous configurable options
696 */
697#define CONFIG_SYS_LONGHELP /* undef to save memory */
698#define CONFIG_CMDLINE_EDITING /* Command-line editing */
Kim Phillips5be58f52010-07-14 19:47:18 -0500699#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Timur Tabic59e1b42010-06-14 15:28:24 -0500700#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
Timur Tabic59e1b42010-06-14 15:28:24 -0500701#ifdef CONFIG_CMD_KGDB
702#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
703#else
704#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
705#endif
706/* Print Buffer Size */
707#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
708#define CONFIG_SYS_MAXARGS 16
709#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
Timur Tabic59e1b42010-06-14 15:28:24 -0500710
711/*
712 * For booting Linux, the board info and command line data
Kumar Galaa832ac42011-04-28 10:13:41 -0500713 * have to be in the first 64 MB of memory, since this is
Timur Tabic59e1b42010-06-14 15:28:24 -0500714 * the maximum mapped by the Linux kernel during initialization.
715 */
Kumar Galaa832ac42011-04-28 10:13:41 -0500716#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/
717#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
Timur Tabic59e1b42010-06-14 15:28:24 -0500718
Timur Tabic59e1b42010-06-14 15:28:24 -0500719#ifdef CONFIG_CMD_KGDB
720#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
Timur Tabic59e1b42010-06-14 15:28:24 -0500721#endif
722
723/*
724 * Environment Configuration
725 */
726
727#define CONFIG_HOSTNAME p1022ds
Joe Hershberger8b3637c2011-10-13 13:03:47 +0000728#define CONFIG_ROOTPATH "/opt/nfsroot"
Joe Hershbergerb3f44c22011-10-13 13:03:48 +0000729#define CONFIG_BOOTFILE "uImage"
Timur Tabic59e1b42010-06-14 15:28:24 -0500730#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
731
732#define CONFIG_LOADADDR 1000000
733
734#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
Timur Tabic59e1b42010-06-14 15:28:24 -0500735
736#define CONFIG_BAUDRATE 115200
737
Timur Tabi84e34b62012-05-04 12:21:29 +0000738#define CONFIG_EXTRA_ENV_SETTINGS \
739 "netdev=eth0\0" \
Marek Vasut5368c552012-09-23 17:41:24 +0200740 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
741 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
Timur Tabi84e34b62012-05-04 12:21:29 +0000742 "tftpflash=tftpboot $loadaddr $uboot && " \
743 "protect off $ubootaddr +$filesize && " \
744 "erase $ubootaddr +$filesize && " \
745 "cp.b $loadaddr $ubootaddr $filesize && " \
746 "protect on $ubootaddr +$filesize && " \
747 "cmp.b $loadaddr $ubootaddr $filesize\0" \
748 "consoledev=ttyS0\0" \
749 "ramdiskaddr=2000000\0" \
750 "ramdiskfile=rootfs.ext2.gz.uboot\0" \
751 "fdtaddr=c00000\0" \
752 "fdtfile=p1022ds.dtb\0" \
753 "bdev=sda3\0" \
Timur Tabiba8e76b2011-04-11 14:18:22 -0500754 "hwconfig=esdhc;audclk:12\0"
Timur Tabic59e1b42010-06-14 15:28:24 -0500755
756#define CONFIG_HDBOOT \
757 "setenv bootargs root=/dev/$bdev rw " \
Timur Tabi84e34b62012-05-04 12:21:29 +0000758 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \
Timur Tabic59e1b42010-06-14 15:28:24 -0500759 "tftp $loadaddr $bootfile;" \
760 "tftp $fdtaddr $fdtfile;" \
761 "bootm $loadaddr - $fdtaddr"
762
763#define CONFIG_NFSBOOTCOMMAND \
764 "setenv bootargs root=/dev/nfs rw " \
765 "nfsroot=$serverip:$rootpath " \
766 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
Timur Tabi84e34b62012-05-04 12:21:29 +0000767 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \
Timur Tabic59e1b42010-06-14 15:28:24 -0500768 "tftp $loadaddr $bootfile;" \
769 "tftp $fdtaddr $fdtfile;" \
770 "bootm $loadaddr - $fdtaddr"
771
772#define CONFIG_RAMBOOTCOMMAND \
773 "setenv bootargs root=/dev/ram rw " \
Timur Tabi84e34b62012-05-04 12:21:29 +0000774 "console=$consoledev,$baudrate $othbootargs $videobootargs;" \
Timur Tabic59e1b42010-06-14 15:28:24 -0500775 "tftp $ramdiskaddr $ramdiskfile;" \
776 "tftp $loadaddr $bootfile;" \
777 "tftp $fdtaddr $fdtfile;" \
778 "bootm $loadaddr $ramdiskaddr $fdtaddr"
779
780#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND
781
782#endif