blob: 13f4bd3c539fae5629ec1adc374f875ec0417bdc [file] [log] [blame]
Chunhe Lan0b2e13d2014-04-14 18:42:06 +08001/*
2 * Copyright 2014 Freescale Semiconductor, Inc.
3 *
4 * SPDX-License-Identifier: GPL-2.0+
5 */
6
7/*
8 * T4240 RDB board configuration file
9 */
10#ifndef __CONFIG_H
11#define __CONFIG_H
12
13#define CONFIG_T4240RDB
14#define CONFIG_PHYS_64BIT
15
16#define CONFIG_FSL_SATA_V2
17#define CONFIG_PCIE4
18
19#define CONFIG_ICS307_REFCLK_HZ 25000000 /* ICS307 ref clk freq */
20
21#ifdef CONFIG_RAMBOOT_PBL
22#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE
23#define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc
24#define CONFIG_SYS_FSL_PBL_PBI $(SRCTREE)/board/freescale/t4rdb/t4_pbi.cfg
25#define CONFIG_SYS_FSL_PBL_RCW $(SRCTREE)/board/freescale/t4rdb/t4_rcw.cfg
26#endif
27
28#define CONFIG_DDR_ECC
29
30#define CONFIG_CMD_REGINFO
31
32/* High Level Configuration Options */
33#define CONFIG_BOOKE
34#define CONFIG_E500 /* BOOKE e500 family */
35#define CONFIG_E500MC /* BOOKE e500mc family */
36#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */
37#define CONFIG_MP /* support multiple processors */
38
39#ifndef CONFIG_SYS_TEXT_BASE
40#define CONFIG_SYS_TEXT_BASE 0xeff40000
41#endif
42
43#ifndef CONFIG_RESET_VECTOR_ADDRESS
44#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc
45#endif
46
47#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */
48#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS
49#define CONFIG_FSL_IFC /* Enable IFC Support */
Ruchika Gupta737537e2014-10-15 11:35:31 +053050#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */
Chunhe Lan0b2e13d2014-04-14 18:42:06 +080051#define CONFIG_PCI /* Enable PCI/PCIE */
52#define CONFIG_PCIE1 /* PCIE controler 1 */
53#define CONFIG_PCIE2 /* PCIE controler 2 */
54#define CONFIG_PCIE3 /* PCIE controler 3 */
55#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */
56#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
57
58#define CONFIG_FSL_LAW /* Use common FSL init code */
59
60#define CONFIG_ENV_OVERWRITE
61
62/*
63 * These can be toggled for performance analysis, otherwise use default.
64 */
65#define CONFIG_SYS_CACHE_STASHING
66#define CONFIG_BTB /* toggle branch predition */
67#ifdef CONFIG_DDR_ECC
68#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER
69#define CONFIG_MEM_INIT_VALUE 0xdeadbeef
70#endif
71
72#define CONFIG_ENABLE_36BIT_PHYS
73
74#define CONFIG_ADDR_MAP
75#define CONFIG_SYS_NUM_ADDR_MAP 64 /* number of TLB1 entries */
76
77#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */
78#define CONFIG_SYS_MEMTEST_END 0x00400000
79#define CONFIG_SYS_ALT_MEMTEST
80#define CONFIG_PANIC_HANG /* do not reset board on panic */
81
82/*
83 * Config the L3 Cache as L3 SRAM
84 */
85#define CONFIG_SYS_INIT_L3_ADDR CONFIG_RAMBOOT_TEXT_BASE
86
87#define CONFIG_SYS_DCSRBAR 0xf0000000
88#define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
89
90/*
91 * DDR Setup
92 */
93#define CONFIG_VERY_BIG_RAM
94#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000
95#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
96
97/* CONFIG_NUM_DDR_CONTROLLERS is defined in include/asm/config_mpc85xx.h */
98#define CONFIG_DIMM_SLOTS_PER_CTLR 1
99#define CONFIG_CHIP_SELECTS_PER_CTRL 4
100#define CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE
101
102#define CONFIG_DDR_SPD
103#define CONFIG_SYS_FSL_DDR3
104
105
106/*
107 * IFC Definitions
108 */
109#define CONFIG_SYS_FLASH_BASE 0xe0000000
110#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE)
111
112
113#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
114
115#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */
116#define CONFIG_MISC_INIT_R
117
118#define CONFIG_HWCONFIG
119
120/* define to use L1 as initial stack */
121#define CONFIG_L1_INIT_RAM
122#define CONFIG_SYS_INIT_RAM_LOCK
123#define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */
124#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf
125#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe0ec000
126/* The assembler doesn't like typecast */
127#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \
128 ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \
129 CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW)
130#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000
131
132#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - \
133 GENERATED_GBL_DATA_SIZE)
134#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
135
136#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
137#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
138
139/* Serial Port - controlled on board with jumper J8
140 * open - index 2
141 * shorted - index 1
142 */
143#define CONFIG_CONS_INDEX 1
144#define CONFIG_SYS_NS16550
145#define CONFIG_SYS_NS16550_SERIAL
146#define CONFIG_SYS_NS16550_REG_SIZE 1
147#define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2)
148
149#define CONFIG_SYS_BAUDRATE_TABLE \
150 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
151
152#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x11C500)
153#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x11C600)
154#define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500)
155#define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600)
156
157/* Use the HUSH parser */
158#define CONFIG_SYS_HUSH_PARSER
159#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
160
161/* pass open firmware flat tree */
162#define CONFIG_OF_LIBFDT
163#define CONFIG_OF_BOARD_SETUP
164#define CONFIG_OF_STDOUT_VIA_ALIAS
165
166/* new uImage format support */
167#define CONFIG_FIT
168#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */
169
170/* I2C */
171#define CONFIG_SYS_I2C
172#define CONFIG_SYS_I2C_FSL
173#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
174#define CONFIG_SYS_FSL_I2C_OFFSET 0x118000
175#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F
176#define CONFIG_SYS_FSL_I2C2_OFFSET 0x118100
177
178/*
179 * General PCI
180 * Memory space is mapped 1-1, but I/O space must start from 0.
181 */
182
183/* controller 1, direct to uli, tgtid 3, Base address 20000 */
184#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000
185#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000
186#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull
187#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */
188#define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000
189#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000
190#define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull
191#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
192
193/* controller 2, Slot 2, tgtid 2, Base address 201000 */
194#define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000
195#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000
196#define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull
197#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */
198#define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000
199#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000
200#define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull
201#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
202
203/* controller 3, Slot 1, tgtid 1, Base address 202000 */
204#define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000
205#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000
206#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull
207#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */
208#define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000
209#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000
210#define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull
211#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
212
213/* controller 4, Base address 203000 */
214#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000
215#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull
216#define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */
217#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000
218#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
219#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
220
221#ifdef CONFIG_PCI
222#define CONFIG_PCI_INDIRECT_BRIDGE
223#define CONFIG_NET_MULTI
224#define CONFIG_PCI_PNP /* do pci plug-and-play */
225#define CONFIG_E1000
226
227#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
228#define CONFIG_DOS_PARTITION
229#endif /* CONFIG_PCI */
230
231/* SATA */
232#ifdef CONFIG_FSL_SATA_V2
233#define CONFIG_LIBATA
234#define CONFIG_FSL_SATA
235
236#define CONFIG_SYS_SATA_MAX_DEVICE 2
237#define CONFIG_SATA1
238#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
239#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
240#define CONFIG_SATA2
241#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
242#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
243
244#define CONFIG_LBA48
245#define CONFIG_CMD_SATA
246#define CONFIG_DOS_PARTITION
247#define CONFIG_CMD_EXT2
248#endif
249
250#ifdef CONFIG_FMAN_ENET
251#define CONFIG_MII /* MII PHY management */
252#define CONFIG_ETHPRIME "FM1@DTSEC1"
253#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
254#endif
255
256/*
257 * Environment
258 */
259#define CONFIG_LOADS_ECHO /* echo on for serial download */
260#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */
261
262/*
263 * Command line configuration.
264 */
265#include <config_cmd_default.h>
266
267#define CONFIG_CMD_DHCP
268#define CONFIG_CMD_ELF
269#define CONFIG_CMD_ERRATA
270#define CONFIG_CMD_GREPENV
271#define CONFIG_CMD_IRQ
272#define CONFIG_CMD_I2C
273#define CONFIG_CMD_MII
274#define CONFIG_CMD_PING
275#define CONFIG_CMD_SETEXPR
276
277#ifdef CONFIG_PCI
278#define CONFIG_CMD_PCI
279#define CONFIG_CMD_NET
280#endif
281
282/*
283 * Miscellaneous configurable options
284 */
285#define CONFIG_SYS_LONGHELP /* undef to save memory */
286#define CONFIG_CMDLINE_EDITING /* Command-line editing */
287#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
288#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
289#ifdef CONFIG_CMD_KGDB
290#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
291#else
292#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
293#endif
294#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16)
295#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
296#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */
297
298/*
299 * For booting Linux, the board info and command line data
300 * have to be in the first 64 MB of memory, since this is
301 * the maximum mapped by the Linux kernel during initialization.
302 */
303#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial map for Linux*/
304#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
305
306#ifdef CONFIG_CMD_KGDB
307#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
308#endif
309
310/*
311 * Environment Configuration
312 */
313#define CONFIG_ROOTPATH "/opt/nfsroot"
314#define CONFIG_BOOTFILE "uImage"
315#define CONFIG_UBOOTPATH "u-boot.bin" /* U-Boot image on TFTP server*/
316
317/* default location for tftp and bootm */
318#define CONFIG_LOADADDR 1000000
319
320
321#define CONFIG_BAUDRATE 115200
322
323#define CONFIG_HVBOOT \
324 "setenv bootargs config-addr=0x60000000; " \
325 "bootm 0x01000000 - 0x00f00000"
326
327#ifdef CONFIG_SYS_NO_FLASH
328#ifndef CONFIG_RAMBOOT_PBL
329#define CONFIG_ENV_IS_NOWHERE
330#endif
331#else
332#define CONFIG_FLASH_CFI_DRIVER
333#define CONFIG_SYS_FLASH_CFI
334#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE
335#endif
336
337#if defined(CONFIG_SPIFLASH)
338#define CONFIG_SYS_EXTRA_ENV_RELOC
339#define CONFIG_ENV_IS_IN_SPI_FLASH
340#define CONFIG_ENV_SPI_BUS 0
341#define CONFIG_ENV_SPI_CS 0
342#define CONFIG_ENV_SPI_MAX_HZ 10000000
343#define CONFIG_ENV_SPI_MODE 0
344#define CONFIG_ENV_SIZE 0x2000 /* 8KB */
345#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */
346#define CONFIG_ENV_SECT_SIZE 0x10000
347#elif defined(CONFIG_SDCARD)
348#define CONFIG_SYS_EXTRA_ENV_RELOC
349#define CONFIG_ENV_IS_IN_MMC
350#define CONFIG_SYS_MMC_ENV_DEV 0
351#define CONFIG_ENV_SIZE 0x2000
352#define CONFIG_ENV_OFFSET (512 * 1658)
353#elif defined(CONFIG_NAND)
354#define CONFIG_SYS_EXTRA_ENV_RELOC
355#define CONFIG_ENV_IS_IN_NAND
356#define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE
357#define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE)
358#elif defined(CONFIG_ENV_IS_NOWHERE)
359#define CONFIG_ENV_SIZE 0x2000
360#else
361#define CONFIG_ENV_IS_IN_FLASH
362#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
363#define CONFIG_ENV_SIZE 0x2000
364#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */
365#endif
366
367#define CONFIG_SYS_CLK_FREQ 66666666
368#define CONFIG_DDR_CLK_FREQ 133333333
369
370#ifndef __ASSEMBLY__
371unsigned long get_board_sys_clk(void);
372unsigned long get_board_ddr_clk(void);
373#endif
374
375/*
376 * DDR Setup
377 */
378#define CONFIG_SYS_SPD_BUS_NUM 0
379#define SPD_EEPROM_ADDRESS1 0x52
380#define SPD_EEPROM_ADDRESS2 0x54
381#define SPD_EEPROM_ADDRESS3 0x56
382#define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 /* for p3041/p5010 */
383#define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */
384
385/*
386 * IFC Definitions
387 */
388#define CONFIG_SYS_NOR0_CSPR_EXT (0xf)
389#define CONFIG_SYS_NOR0_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS \
390 + 0x8000000) | \
391 CSPR_PORT_SIZE_16 | \
392 CSPR_MSEL_NOR | \
393 CSPR_V)
394#define CONFIG_SYS_NOR1_CSPR_EXT (0xf)
395#define CONFIG_SYS_NOR1_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \
396 CSPR_PORT_SIZE_16 | \
397 CSPR_MSEL_NOR | \
398 CSPR_V)
399#define CONFIG_SYS_NOR_AMASK IFC_AMASK(128*1024*1024)
400/* NOR Flash Timing Params */
401#define CONFIG_SYS_NOR_CSOR CSOR_NAND_TRHZ_80
402
403#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \
404 FTIM0_NOR_TEADC(0x5) | \
405 FTIM0_NOR_TEAHC(0x5))
406#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x35) | \
407 FTIM1_NOR_TRAD_NOR(0x1A) |\
408 FTIM1_NOR_TSEQRAD_NOR(0x13))
409#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \
410 FTIM2_NOR_TCH(0x4) | \
411 FTIM2_NOR_TWPH(0x0E) | \
412 FTIM2_NOR_TWP(0x1c))
413#define CONFIG_SYS_NOR_FTIM3 0x0
414
415#define CONFIG_SYS_FLASH_QUIET_TEST
416#define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */
417
418#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */
419#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
420#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
421#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
422
423#define CONFIG_SYS_FLASH_EMPTY_INFO
424#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS \
425 + 0x8000000, CONFIG_SYS_FLASH_BASE_PHYS}
426
427/* NAND Flash on IFC */
428#define CONFIG_NAND_FSL_IFC
429#define CONFIG_SYS_NAND_MAX_ECCPOS 256
430#define CONFIG_SYS_NAND_MAX_OOBFREE 2
431#define CONFIG_SYS_NAND_BASE 0xff800000
432#define CONFIG_SYS_NAND_BASE_PHYS (0xf00000000ull | CONFIG_SYS_NAND_BASE)
433
434#define CONFIG_SYS_NAND_CSPR_EXT (0xf)
435#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
436 | CSPR_PORT_SIZE_8 /* Port Size = 8 bit */ \
437 | CSPR_MSEL_NAND /* MSEL = NAND */ \
438 | CSPR_V)
439#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024)
440
441#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \
442 | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \
443 | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \
444 | CSOR_NAND_RAL_3 /* RAL = 2Byes */ \
445 | CSOR_NAND_PGS_4K /* Page Size = 4K */ \
446 | CSOR_NAND_SPRZ_224 /* Spare size = 224 */ \
447 | CSOR_NAND_PB(128)) /*Page Per Block = 128*/
448
449#define CONFIG_SYS_NAND_ONFI_DETECTION
450
451/* ONFI NAND Flash mode0 Timing Params */
452#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07) | \
453 FTIM0_NAND_TWP(0x18) | \
454 FTIM0_NAND_TWCHT(0x07) | \
455 FTIM0_NAND_TWH(0x0a))
456#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x32) | \
457 FTIM1_NAND_TWBE(0x39) | \
458 FTIM1_NAND_TRR(0x0e) | \
459 FTIM1_NAND_TRP(0x18))
460#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0f) | \
461 FTIM2_NAND_TREH(0x0a) | \
462 FTIM2_NAND_TWHRE(0x1e))
463#define CONFIG_SYS_NAND_FTIM3 0x0
464
465#define CONFIG_SYS_NAND_DDR_LAW 11
466#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
467#define CONFIG_SYS_MAX_NAND_DEVICE 1
468#define CONFIG_MTD_NAND_VERIFY_WRITE
469#define CONFIG_CMD_NAND
470
471#define CONFIG_SYS_NAND_BLOCK_SIZE (512 * 1024)
472
473#if defined(CONFIG_NAND)
474#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT
475#define CONFIG_SYS_CSPR0 CONFIG_SYS_NAND_CSPR
476#define CONFIG_SYS_AMASK0 CONFIG_SYS_NAND_AMASK
477#define CONFIG_SYS_CSOR0 CONFIG_SYS_NAND_CSOR
478#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NAND_FTIM0
479#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NAND_FTIM1
480#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NAND_FTIM2
481#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NAND_FTIM3
482#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR0_CSPR_EXT
483#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR0_CSPR
484#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
485#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
486#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
487#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
488#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
489#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
490#else
491#define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NOR0_CSPR_EXT
492#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR0_CSPR
493#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK
494#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR
495#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0
496#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1
497#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2
498#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3
499#define CONFIG_SYS_CSPR1_EXT CONFIG_SYS_NAND_CSPR_EXT
500#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR
501#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK
502#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR
503#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0
504#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1
505#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2
506#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
507#endif
508#define CONFIG_SYS_CSPR2_EXT CONFIG_SYS_NOR1_CSPR_EXT
509#define CONFIG_SYS_CSPR2 CONFIG_SYS_NOR1_CSPR
510#define CONFIG_SYS_AMASK2 CONFIG_SYS_NOR_AMASK
511#define CONFIG_SYS_CSOR2 CONFIG_SYS_NOR_CSOR
512#define CONFIG_SYS_CS2_FTIM0 CONFIG_SYS_NOR_FTIM0
513#define CONFIG_SYS_CS2_FTIM1 CONFIG_SYS_NOR_FTIM1
514#define CONFIG_SYS_CS2_FTIM2 CONFIG_SYS_NOR_FTIM2
515#define CONFIG_SYS_CS2_FTIM3 CONFIG_SYS_NOR_FTIM3
516
517#if defined(CONFIG_RAMBOOT_PBL)
518#define CONFIG_SYS_RAMBOOT
519#endif
520
521
522/* I2C */
523#define CONFIG_SYS_FSL_I2C_SPEED 100000 /* I2C speed */
524#define CONFIG_SYS_FSL_I2C2_SPEED 100000 /* I2C2 speed */
525#define I2C_MUX_PCA_ADDR_PRI 0x77 /* I2C bus multiplexer,primary */
526#define I2C_MUX_PCA_ADDR_SEC 0x76 /* I2C bus multiplexer,secondary */
527
528#define I2C_MUX_CH_DEFAULT 0x8
529#define I2C_MUX_CH_VOL_MONITOR 0xa
530#define I2C_MUX_CH_VSC3316_FS 0xc
531#define I2C_MUX_CH_VSC3316_BS 0xd
532
533/* Voltage monitor on channel 2*/
534#define I2C_VOL_MONITOR_ADDR 0x40
535#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
536#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
537#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
538
539/*
540 * eSPI - Enhanced SPI
541 */
542#define CONFIG_FSL_ESPI
543#define CONFIG_SPI_FLASH
544#define CONFIG_SPI_FLASH_SST
545#define CONFIG_CMD_SF
546#define CONFIG_SF_DEFAULT_SPEED 10000000
547#define CONFIG_SF_DEFAULT_MODE 0
548
549
550/* Qman/Bman */
551#ifndef CONFIG_NOBQFMAN
552#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */
553#define CONFIG_SYS_BMAN_NUM_PORTALS 50
554#define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000
555#define CONFIG_SYS_BMAN_MEM_PHYS 0xff4000000ull
556#define CONFIG_SYS_BMAN_MEM_SIZE 0x02000000
557#define CONFIG_SYS_QMAN_NUM_PORTALS 50
558#define CONFIG_SYS_QMAN_MEM_BASE 0xf6000000
559#define CONFIG_SYS_QMAN_MEM_PHYS 0xff6000000ull
560#define CONFIG_SYS_QMAN_MEM_SIZE 0x02000000
561
562#define CONFIG_SYS_DPAA_FMAN
563#define CONFIG_SYS_DPAA_PME
564#define CONFIG_SYS_PMAN
565#define CONFIG_SYS_DPAA_DCE
566#define CONFIG_SYS_DPAA_RMAN
567#define CONFIG_SYS_INTERLAKEN
568
569/* Default address of microcode for the Linux Fman driver */
570#if defined(CONFIG_SPIFLASH)
571/*
572 * env is stored at 0x100000, sector size is 0x10000, ucode is stored after
573 * env, so we got 0x110000.
574 */
575#define CONFIG_SYS_QE_FW_IN_SPIFLASH
576#define CONFIG_SYS_FMAN_FW_ADDR 0x110000
577#elif defined(CONFIG_SDCARD)
578/*
579 * PBL SD boot image should stored at 0x1000(8 blocks), the size of the image is
580 * about 825KB (1650 blocks), Env is stored after the image, and the env size is
581 * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680.
582 */
583#define CONFIG_SYS_QE_FMAN_FW_IN_MMC
584#define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680)
585#elif defined(CONFIG_NAND)
586#define CONFIG_SYS_QE_FMAN_FW_IN_NAND
587#define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE)
588#else
589#define CONFIG_SYS_QE_FMAN_FW_IN_NOR
590#define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000
591#endif
592#define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000
593#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH)
594#endif /* CONFIG_NOBQFMAN */
595
596#ifdef CONFIG_SYS_DPAA_FMAN
597#define CONFIG_FMAN_ENET
598#define CONFIG_PHYLIB_10G
599#define CONFIG_PHY_VITESSE
600#define CONFIG_PHY_CORTINA
601#define CONFIG_CORTINA_FW_ADDR 0xefe00000
602#define CONFIG_CORTINA_FW_LENGTH 0x40000
603#define CONFIG_PHY_TERANETICS
604#define SGMII_PHY_ADDR1 0x0
605#define SGMII_PHY_ADDR2 0x1
606#define SGMII_PHY_ADDR3 0x2
607#define SGMII_PHY_ADDR4 0x3
608#define SGMII_PHY_ADDR5 0x4
609#define SGMII_PHY_ADDR6 0x5
610#define SGMII_PHY_ADDR7 0x6
611#define SGMII_PHY_ADDR8 0x7
612#define FM1_10GEC1_PHY_ADDR 0x10
613#define FM1_10GEC2_PHY_ADDR 0x11
614#define FM2_10GEC1_PHY_ADDR 0x12
615#define FM2_10GEC2_PHY_ADDR 0x13
616#define CORTINA_PHY_ADDR1 FM1_10GEC1_PHY_ADDR
617#define CORTINA_PHY_ADDR2 FM1_10GEC2_PHY_ADDR
618#define CORTINA_PHY_ADDR3 FM2_10GEC1_PHY_ADDR
619#define CORTINA_PHY_ADDR4 FM2_10GEC2_PHY_ADDR
620#endif
621
622
623/* SATA */
624#ifdef CONFIG_FSL_SATA_V2
625#define CONFIG_LIBATA
626#define CONFIG_FSL_SATA
627
628#define CONFIG_SYS_SATA_MAX_DEVICE 2
629#define CONFIG_SATA1
630#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR
631#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
632#define CONFIG_SATA2
633#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR
634#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
635
636#define CONFIG_LBA48
637#define CONFIG_CMD_SATA
638#define CONFIG_DOS_PARTITION
639#define CONFIG_CMD_EXT2
640#endif
641
642#ifdef CONFIG_FMAN_ENET
643#define CONFIG_MII /* MII PHY management */
644#define CONFIG_ETHPRIME "FM1@DTSEC1"
645#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */
646#endif
647
648/*
649* USB
650*/
651#define CONFIG_CMD_USB
652#define CONFIG_USB_STORAGE
653#define CONFIG_USB_EHCI
654#define CONFIG_USB_EHCI_FSL
655#define CONFIG_EHCI_HCD_INIT_AFTER_RESET
656#define CONFIG_CMD_EXT2
657#define CONFIG_HAS_FSL_DR_USB
658
659#define CONFIG_MMC
660
661#ifdef CONFIG_MMC
662#define CONFIG_FSL_ESDHC
663#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR
664#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT
665#define CONFIG_CMD_MMC
666#define CONFIG_GENERIC_MMC
667#define CONFIG_CMD_EXT2
668#define CONFIG_CMD_FAT
669#define CONFIG_DOS_PARTITION
670#endif
671
Ruchika Gupta737537e2014-10-15 11:35:31 +0530672/* Hash command with SHA acceleration supported in hardware */
673#ifdef CONFIG_FSL_CAAM
674#define CONFIG_CMD_HASH
675#define CONFIG_SHA_HW_ACCEL
676#endif
677
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800678#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */
679
680#define __USB_PHY_TYPE utmi
681
682/*
683 * T4240 has 3 DDR controllers. Default to 3-way interleaving. It can be
684 * 3way_1KB, 3way_4KB, 3way_8KB. T4160 has 2 DDR controllers. Default to 2-way
685 * interleaving. It can be cacheline, page, bank, superbank.
686 * See doc/README.fsl-ddr for details.
687 */
Chunhe Lan1a344452014-05-07 10:56:18 +0800688#ifdef CONFIG_PPC_T4240
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800689#define CTRL_INTLV_PREFERED 3way_4KB
Chunhe Lan1a344452014-05-07 10:56:18 +0800690#else
691#define CTRL_INTLV_PREFERED cacheline
692#endif
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800693
694#define CONFIG_EXTRA_ENV_SETTINGS \
695 "hwconfig=fsl_ddr:" \
696 "ctlr_intlv=" __stringify(CTRL_INTLV_PREFERED) "," \
697 "bank_intlv=auto;" \
698 "usb1:dr_mode=host,phy_type=" __stringify(__USB_PHY_TYPE) "\0"\
699 "netdev=eth0\0" \
700 "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \
701 "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \
702 "tftpflash=tftpboot $loadaddr $uboot && " \
703 "protect off $ubootaddr +$filesize && " \
704 "erase $ubootaddr +$filesize && " \
705 "cp.b $loadaddr $ubootaddr $filesize && " \
706 "protect on $ubootaddr +$filesize && " \
707 "cmp.b $loadaddr $ubootaddr $filesize\0" \
708 "consoledev=ttyS0\0" \
709 "ramdiskaddr=2000000\0" \
710 "ramdiskfile=t4240rdb/ramdisk.uboot\0" \
711 "fdtaddr=c00000\0" \
712 "fdtfile=t4240rdb/t4240rdb.dtb\0" \
713 "bdev=sda3\0"
714
715#define CONFIG_HVBOOT \
716 "setenv bootargs config-addr=0x60000000; " \
717 "bootm 0x01000000 - 0x00f00000"
718
719#define CONFIG_LINUX \
720 "setenv bootargs root=/dev/ram rw " \
721 "console=$consoledev,$baudrate $othbootargs;" \
722 "setenv ramdiskaddr 0x02000000;" \
723 "setenv fdtaddr 0x00c00000;" \
724 "setenv loadaddr 0x1000000;" \
725 "bootm $loadaddr $ramdiskaddr $fdtaddr"
726
727#define CONFIG_HDBOOT \
728 "setenv bootargs root=/dev/$bdev rw " \
729 "console=$consoledev,$baudrate $othbootargs;" \
730 "tftp $loadaddr $bootfile;" \
731 "tftp $fdtaddr $fdtfile;" \
732 "bootm $loadaddr - $fdtaddr"
733
734#define CONFIG_NFSBOOTCOMMAND \
735 "setenv bootargs root=/dev/nfs rw " \
736 "nfsroot=$serverip:$rootpath " \
737 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
738 "console=$consoledev,$baudrate $othbootargs;" \
739 "tftp $loadaddr $bootfile;" \
740 "tftp $fdtaddr $fdtfile;" \
741 "bootm $loadaddr - $fdtaddr"
742
743#define CONFIG_RAMBOOTCOMMAND \
744 "setenv bootargs root=/dev/ram rw " \
745 "console=$consoledev,$baudrate $othbootargs;" \
746 "tftp $ramdiskaddr $ramdiskfile;" \
747 "tftp $loadaddr $bootfile;" \
748 "tftp $fdtaddr $fdtfile;" \
749 "bootm $loadaddr $ramdiskaddr $fdtaddr"
750
751#define CONFIG_BOOTCOMMAND CONFIG_LINUX
752
753#include <asm/fsl_secure_boot.h>
754
755#ifdef CONFIG_SECURE_BOOT
756/* Secure Boot target was not getting build for T4240 because of
757 * increased binary size. So the size is being reduced by removing USB
758 * which is anyways not used in Secure Environment.
759 */
760#undef CONFIG_CMD_USB
Ruchika Gupta789490b2014-10-07 15:48:46 +0530761#define CONFIG_CMD_BLOB
Chunhe Lan0b2e13d2014-04-14 18:42:06 +0800762#endif
763
764#endif /* __CONFIG_H */