| Dirk Eibach | d494cdb | 2019-03-29 10:18:19 +0100 | [diff] [blame] | 1 | CONFIG_PPC=y |
| 2 | CONFIG_SYS_TEXT_BASE=0xFE000000 |
| 3 | CONFIG_SYS_MALLOC_F_LEN=0x600 |
| Tom Rini | a09fea1 | 2019-11-18 20:02:10 -0500 | [diff] [blame] | 4 | CONFIG_ENV_SIZE=0x2000 |
| 5 | CONFIG_ENV_SECT_SIZE=0x10000 |
| Tom Rini | 052170c | 2020-01-22 13:38:00 -0500 | [diff] [blame] | 6 | CONFIG_DM_GPIO=y |
| Dirk Eibach | d494cdb | 2019-03-29 10:18:19 +0100 | [diff] [blame] | 7 | CONFIG_IDENT_STRING=" gazerbeam 0.01" |
| 8 | CONFIG_SYS_CLK_FREQ=33333333 |
| 9 | CONFIG_MPC83xx=y |
| 10 | CONFIG_TARGET_GAZERBEAM=y |
| 11 | CONFIG_SYSTEM_PLL_VCO_DIV_2=y |
| 12 | CONFIG_SYSTEM_PLL_FACTOR_4_1=y |
| 13 | CONFIG_CORE_PLL_RATIO_3_1=y |
| 14 | CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y |
| 15 | CONFIG_TSEC1_MODE_RGMII=y |
| 16 | CONFIG_TSEC2_MODE_RGMII=y |
| 17 | CONFIG_BAT0=y |
| 18 | CONFIG_BAT0_NAME="SDRAM" |
| 19 | CONFIG_BAT0_BASE=0x00000000 |
| 20 | CONFIG_BAT0_LENGTH_128_MBYTES=y |
| 21 | CONFIG_BAT0_ACCESS_RW=y |
| 22 | CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y |
| 23 | CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y |
| 24 | CONFIG_BAT0_USER_MODE_VALID=y |
| 25 | CONFIG_BAT0_SUPERVISOR_MODE_VALID=y |
| 26 | CONFIG_BAT1=y |
| 27 | CONFIG_BAT1_NAME="IMMR" |
| 28 | CONFIG_BAT1_BASE=0xE0000000 |
| 29 | CONFIG_BAT1_LENGTH_8_MBYTES=y |
| 30 | CONFIG_BAT1_ACCESS_RW=y |
| 31 | CONFIG_BAT1_ICACHE_INHIBITED=y |
| 32 | CONFIG_BAT1_ICACHE_GUARDED=y |
| 33 | CONFIG_BAT1_DCACHE_INHIBITED=y |
| 34 | CONFIG_BAT1_DCACHE_GUARDED=y |
| 35 | CONFIG_BAT1_USER_MODE_VALID=y |
| 36 | CONFIG_BAT1_SUPERVISOR_MODE_VALID=y |
| 37 | CONFIG_BAT2=y |
| 38 | CONFIG_BAT2_NAME="FLASH" |
| 39 | CONFIG_BAT2_BASE=0xFE000000 |
| 40 | CONFIG_BAT2_LENGTH_8_MBYTES=y |
| 41 | CONFIG_BAT2_ACCESS_RW=y |
| 42 | CONFIG_BAT2_ICACHE_MEMORYCOHERENCE=y |
| 43 | CONFIG_BAT2_DCACHE_INHIBITED=y |
| 44 | CONFIG_BAT2_DCACHE_GUARDED=y |
| 45 | CONFIG_BAT2_USER_MODE_VALID=y |
| 46 | CONFIG_BAT2_SUPERVISOR_MODE_VALID=y |
| 47 | CONFIG_BAT3=y |
| 48 | CONFIG_BAT3_NAME="INIT_RAM" |
| 49 | CONFIG_BAT3_BASE=0xE6000000 |
| 50 | CONFIG_BAT3_ACCESS_RW=y |
| 51 | CONFIG_BAT3_USER_MODE_VALID=y |
| 52 | CONFIG_BAT3_SUPERVISOR_MODE_VALID=y |
| 53 | CONFIG_LBLAW0=y |
| 54 | CONFIG_LBLAW0_BASE=0xFE000000 |
| 55 | CONFIG_LBLAW0_NAME="FLASH" |
| 56 | CONFIG_LBLAW0_LENGTH_8_MBYTES=y |
| 57 | CONFIG_LBLAW1=y |
| 58 | CONFIG_LBLAW1_BASE=0xE0600000 |
| 59 | CONFIG_LBLAW1_NAME="FPGA0" |
| 60 | CONFIG_LBLAW1_LENGTH_1_MBYTES=y |
| 61 | CONFIG_LBLAW2=y |
| 62 | CONFIG_LBLAW2_BASE=0xE0700000 |
| 63 | CONFIG_LBLAW2_NAME="FPGA1" |
| 64 | CONFIG_LBLAW2_LENGTH_1_MBYTES=y |
| 65 | CONFIG_ELBC_BR0_OR0=y |
| 66 | CONFIG_BR0_OR0_NAME="FLASH" |
| 67 | CONFIG_BR0_OR0_BASE=0xFE000000 |
| 68 | CONFIG_BR0_PORTSIZE_16BIT=y |
| 69 | CONFIG_OR0_AM_8_MBYTES=y |
| 70 | CONFIG_OR0_SCY_15=y |
| 71 | CONFIG_OR0_CSNT_EARLIER=y |
| 72 | CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y |
| 73 | CONFIG_OR0_XACS_EXTENDED=y |
| 74 | CONFIG_OR0_TRLX_RELAXED=y |
| 75 | CONFIG_OR0_EHTR_8_CYCLE=y |
| 76 | CONFIG_ELBC_BR1_OR1=y |
| 77 | CONFIG_BR1_OR1_NAME="FPGA0" |
| 78 | CONFIG_BR1_OR1_BASE=0xE0600000 |
| 79 | CONFIG_BR1_PORTSIZE_16BIT=y |
| 80 | CONFIG_OR1_AM_1_MBYTES=y |
| 81 | CONFIG_OR1_SCY_5=y |
| 82 | CONFIG_OR1_CSNT_EARLIER=y |
| 83 | CONFIG_ELBC_BR2_OR2=y |
| 84 | CONFIG_BR2_OR2_NAME="FPGA1" |
| 85 | CONFIG_BR2_OR2_BASE=0xE0700000 |
| 86 | CONFIG_BR2_PORTSIZE_16BIT=y |
| 87 | CONFIG_OR2_AM_1_MBYTES=y |
| 88 | CONFIG_OR2_SCY_5=y |
| 89 | CONFIG_OR2_CSNT_EARLIER=y |
| 90 | CONFIG_HID0_FINAL_EMCP=y |
| 91 | CONFIG_HID0_FINAL_DPM=y |
| 92 | CONFIG_HID0_FINAL_ICE=y |
| 93 | CONFIG_HID2_HBE=y |
| 94 | CONFIG_SICR_ETSEC1_A_TSEC_GTX_CLK125=y |
| 95 | CONFIG_SICR_GPIO_A_TSEC2=y |
| 96 | CONFIG_SICR_GPIO_B_TSEC_GTX_CLK125=y |
| 97 | CONFIG_SICR_IEEE1588_A_GPIO=y |
| 98 | CONFIG_SICR_GTM_GPIO=y |
| 99 | CONFIG_SICR_ETSEC2_GPIO=y |
| 100 | CONFIG_SICR_GPIOSEL_IEEE1588=y |
| 101 | CONFIG_SICR_TMSOBI1_2_5_V=y |
| 102 | CONFIG_SICR_TMSOBI2_2_5_V=y |
| 103 | CONFIG_ACR_PIPE_DEP_4=y |
| 104 | CONFIG_ACR_RPTCNT_4=y |
| 105 | CONFIG_SPCR_TSECEP_3=y |
| 106 | CONFIG_LCRR_DBYP_PLL_BYPASSED=y |
| 107 | CONFIG_LCRR_CLKDIV_2=y |
| 108 | CONFIG_SYS_FPGA_FLAVOR_GAZERBEAM=y |
| 109 | CONFIG_CMD_IOLOOP=y |
| 110 | CONFIG_FIT=y |
| 111 | CONFIG_FIT_SIGNATURE=y |
| 112 | CONFIG_FIT_VERBOSE=y |
| 113 | CONFIG_OF_BOARD_SETUP=y |
| 114 | CONFIG_OF_STDOUT_VIA_ALIAS=y |
| 115 | CONFIG_BOOTDELAY=5 |
| 116 | # CONFIG_CONSOLE_MUX is not set |
| 117 | CONFIG_SYS_CONSOLE_INFO_QUIET=y |
| 118 | CONFIG_DISPLAY_CPUINFO=y |
| 119 | # CONFIG_DISPLAY_BOARDINFO is not set |
| 120 | CONFIG_DISPLAY_BOARDINFO_LATE=y |
| 121 | CONFIG_BOARD_EARLY_INIT_R=y |
| 122 | CONFIG_LAST_STAGE_INIT=y |
| 123 | CONFIG_HUSH_PARSER=y |
| 124 | CONFIG_AUTOBOOT_KEYED=y |
| 125 | CONFIG_AUTOBOOT_STOP_STR=" " |
| 126 | CONFIG_CMD_CPU=y |
| 127 | CONFIG_CMD_BINOP=y |
| 128 | CONFIG_CMD_MEMTEST=y |
| 129 | CONFIG_SYS_ALT_MEMTEST=y |
| 130 | CONFIG_CMD_GPIO=y |
| 131 | CONFIG_CMD_I2C=y |
| 132 | CONFIG_CMD_MMC=y |
| 133 | CONFIG_CMD_AXI=y |
| 134 | # CONFIG_CMD_SETEXPR is not set |
| 135 | # CONFIG_CMD_NFS is not set |
| 136 | CONFIG_CMD_MII=y |
| Dirk Eibach | d494cdb | 2019-03-29 10:18:19 +0100 | [diff] [blame] | 137 | CONFIG_CMD_PING=y |
| 138 | CONFIG_CMD_CACHE=y |
| 139 | CONFIG_CMD_HASH=y |
| 140 | CONFIG_CMD_TPM=y |
| 141 | CONFIG_CMD_EXT2=y |
| 142 | CONFIG_DOS_PARTITION=y |
| 143 | CONFIG_OF_CONTROL=y |
| 144 | CONFIG_OF_LIVE=y |
| 145 | CONFIG_DEFAULT_DEVICE_TREE="gazerbeam" |
| Tom Rini | cb6617a | 2019-11-10 11:28:03 -0500 | [diff] [blame] | 146 | CONFIG_SYS_REDUNDAND_ENVIRONMENT=y |
| Tom Rini | a09fea1 | 2019-11-18 20:02:10 -0500 | [diff] [blame] | 147 | CONFIG_ENV_ADDR=0xFE080000 |
| 148 | CONFIG_ENV_ADDR_REDUND=0xFE090000 |
| Dirk Eibach | d494cdb | 2019-03-29 10:18:19 +0100 | [diff] [blame] | 149 | CONFIG_DM=y |
| 150 | CONFIG_REGMAP=y |
| 151 | CONFIG_AXI=y |
| 152 | CONFIG_IHS_AXI=y |
| 153 | CONFIG_CLK=y |
| 154 | CONFIG_ICS8N3QV01=y |
| 155 | CONFIG_CPU=y |
| 156 | CONFIG_CPU_MPC83XX=y |
| 157 | CONFIG_BOARD=y |
| 158 | CONFIG_BOARD_GAZERBEAM=y |
| Dirk Eibach | d494cdb | 2019-03-29 10:18:19 +0100 | [diff] [blame] | 159 | CONFIG_DM_PCA953X=y |
| 160 | CONFIG_MPC8XXX_GPIO=y |
| 161 | CONFIG_DM_I2C=y |
| 162 | CONFIG_SYS_I2C_FSL=y |
| 163 | CONFIG_SYS_I2C_IHS=y |
| 164 | CONFIG_MISC=y |
| 165 | CONFIG_GDSYS_RXAUI_CTRL=y |
| 166 | CONFIG_GDSYS_IOEP=y |
| 167 | CONFIG_MPC83XX_SERDES=y |
| 168 | CONFIG_GDSYS_SOC=y |
| 169 | CONFIG_IHS_FPGA=y |
| 170 | CONFIG_DM_MMC=y |
| 171 | CONFIG_FSL_ESDHC=y |
| Miquel Raynal | 1de770d | 2019-10-03 19:50:04 +0200 | [diff] [blame] | 172 | CONFIG_DM_MTD=y |
| Dirk Eibach | d494cdb | 2019-03-29 10:18:19 +0100 | [diff] [blame] | 173 | CONFIG_MTD_NOR_FLASH=y |
| 174 | CONFIG_FLASH_CFI_DRIVER=y |
| 175 | CONFIG_CFI_FLASH=y |
| 176 | CONFIG_SYS_FLASH_PROTECTION=y |
| 177 | CONFIG_SYS_FLASH_CFI=y |
| 178 | CONFIG_PHYLIB_10G=y |
| 179 | CONFIG_PHY_MARVELL=y |
| 180 | CONFIG_DM_ETH=y |
| 181 | CONFIG_TSEC_ENET=y |
| 182 | # CONFIG_PCI is not set |
| 183 | CONFIG_RAM=y |
| 184 | CONFIG_MPC83XX_SDRAM=y |
| 185 | CONFIG_DM_RESET=y |
| 186 | CONFIG_DM_SERIAL=y |
| 187 | CONFIG_SYS_NS16550=y |
| 188 | CONFIG_SYSRESET=y |
| Rasmus Villemoes | 875669d | 2019-12-13 15:47:58 +0000 | [diff] [blame] | 189 | CONFIG_SYSRESET_MPC83XX=y |
| Dirk Eibach | d494cdb | 2019-03-29 10:18:19 +0100 | [diff] [blame] | 190 | CONFIG_TIMER=y |
| 191 | CONFIG_MPC83XX_TIMER=y |
| 192 | CONFIG_TPM_ATMEL_TWI=y |
| 193 | CONFIG_TPM_AUTH_SESSIONS=y |
| 194 | # CONFIG_TPM_V2 is not set |
| 195 | CONFIG_DM_VIDEO=y |
| Dirk Eibach | d494cdb | 2019-03-29 10:18:19 +0100 | [diff] [blame] | 196 | CONFIG_DISPLAY=y |
| 197 | CONFIG_LOGICORE_DP_TX=y |
| 198 | CONFIG_OSD=y |
| 199 | CONFIG_IHS_VIDEO_OUT=y |
| 200 | CONFIG_TPM=y |