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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Andy Fleming50586ef2008-10-30 16:47:16 -05002/*
3 * FSL SD/MMC Defines
4 *-------------------------------------------------------------------
5 *
Priyanka Jain32c8cfb2011-02-09 09:24:10 +05306 * Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc
Andy Fleming50586ef2008-10-30 16:47:16 -05007 */
8
9#ifndef __FSL_ESDHC_H__
10#define __FSL_ESDHC_H__
11
Masahiro Yamada1221ce42016-09-21 11:28:55 +090012#include <linux/errno.h>
Stefano Babicc67bee12010-02-05 15:11:27 +010013#include <asm/byteorder.h>
Anton Vorontsovb33433a2009-06-10 00:25:29 +040014
Pantelis Antoniou93bfd612014-03-11 19:34:20 +020015/* needed for the mmc_cfg definition */
16#include <mmc.h>
17
Yangbo Lu5a8dbdc2015-04-22 13:57:00 +080018#ifdef CONFIG_FSL_ESDHC_ADAPTER_IDENT
19#include "../board/freescale/common/qixis.h"
20#endif
21
Andy Fleming50586ef2008-10-30 16:47:16 -050022/* FSL eSDHC-specific constants */
23#define SYSCTL 0x0002e02c
24#define SYSCTL_INITA 0x08000000
25#define SYSCTL_TIMEOUT_MASK 0x000f0000
Li Yang1118cdb2010-01-07 16:00:13 +080026#define SYSCTL_CLOCK_MASK 0x0000fff0
Stefano Babicc67bee12010-02-05 15:11:27 +010027#define SYSCTL_CKEN 0x00000008
Andy Fleming50586ef2008-10-30 16:47:16 -050028#define SYSCTL_PEREN 0x00000004
29#define SYSCTL_HCKEN 0x00000002
30#define SYSCTL_IPGEN 0x00000001
Jerry Huang48bb3bb2010-03-18 15:57:06 -050031#define SYSCTL_RSTA 0x01000000
Dirk Behme7a5b8022012-03-26 03:13:05 +000032#define SYSCTL_RSTC 0x02000000
33#define SYSCTL_RSTD 0x04000000
Andy Fleming50586ef2008-10-30 16:47:16 -050034
35#define IRQSTAT 0x0002e030
36#define IRQSTAT_DMAE (0x10000000)
37#define IRQSTAT_AC12E (0x01000000)
38#define IRQSTAT_DEBE (0x00400000)
39#define IRQSTAT_DCE (0x00200000)
40#define IRQSTAT_DTOE (0x00100000)
41#define IRQSTAT_CIE (0x00080000)
42#define IRQSTAT_CEBE (0x00040000)
43#define IRQSTAT_CCE (0x00020000)
44#define IRQSTAT_CTOE (0x00010000)
45#define IRQSTAT_CINT (0x00000100)
46#define IRQSTAT_CRM (0x00000080)
47#define IRQSTAT_CINS (0x00000040)
48#define IRQSTAT_BRR (0x00000020)
49#define IRQSTAT_BWR (0x00000010)
50#define IRQSTAT_DINT (0x00000008)
51#define IRQSTAT_BGE (0x00000004)
52#define IRQSTAT_TC (0x00000002)
53#define IRQSTAT_CC (0x00000001)
54
55#define CMD_ERR (IRQSTAT_CIE | IRQSTAT_CEBE | IRQSTAT_CCE)
Andrew Gabbasov9b74dc52013-04-07 23:06:08 +000056#define DATA_ERR (IRQSTAT_DEBE | IRQSTAT_DCE | IRQSTAT_DTOE | \
57 IRQSTAT_DMAE)
58#define DATA_COMPLETE (IRQSTAT_TC | IRQSTAT_DINT)
Andy Fleming50586ef2008-10-30 16:47:16 -050059
60#define IRQSTATEN 0x0002e034
61#define IRQSTATEN_DMAE (0x10000000)
62#define IRQSTATEN_AC12E (0x01000000)
63#define IRQSTATEN_DEBE (0x00400000)
64#define IRQSTATEN_DCE (0x00200000)
65#define IRQSTATEN_DTOE (0x00100000)
66#define IRQSTATEN_CIE (0x00080000)
67#define IRQSTATEN_CEBE (0x00040000)
68#define IRQSTATEN_CCE (0x00020000)
69#define IRQSTATEN_CTOE (0x00010000)
70#define IRQSTATEN_CINT (0x00000100)
71#define IRQSTATEN_CRM (0x00000080)
72#define IRQSTATEN_CINS (0x00000040)
73#define IRQSTATEN_BRR (0x00000020)
74#define IRQSTATEN_BWR (0x00000010)
75#define IRQSTATEN_DINT (0x00000008)
76#define IRQSTATEN_BGE (0x00000004)
77#define IRQSTATEN_TC (0x00000002)
78#define IRQSTATEN_CC (0x00000001)
79
Yangbo Lu2d9ca2c2015-04-22 13:57:40 +080080#define ESDHCCTL 0x0002e40c
81#define ESDHCCTL_PCS (0x00080000)
82
Andy Fleming50586ef2008-10-30 16:47:16 -050083#define PRSSTAT 0x0002e024
Dirk Behme7a5b8022012-03-26 03:13:05 +000084#define PRSSTAT_DAT0 (0x01000000)
Andy Fleming50586ef2008-10-30 16:47:16 -050085#define PRSSTAT_CLSL (0x00800000)
86#define PRSSTAT_WPSPL (0x00080000)
87#define PRSSTAT_CDPL (0x00040000)
88#define PRSSTAT_CINS (0x00010000)
89#define PRSSTAT_BREN (0x00000800)
Dipen Dudhat77c14582009-10-05 15:41:58 +053090#define PRSSTAT_BWEN (0x00000400)
Yangbo Lu2d9ca2c2015-04-22 13:57:40 +080091#define PRSSTAT_SDSTB (0X00000008)
Andy Fleming50586ef2008-10-30 16:47:16 -050092#define PRSSTAT_DLA (0x00000004)
93#define PRSSTAT_CICHB (0x00000002)
94#define PRSSTAT_CIDHB (0x00000001)
95
96#define PROCTL 0x0002e028
97#define PROCTL_INIT 0x00000020
98#define PROCTL_DTW_4 0x00000002
99#define PROCTL_DTW_8 0x00000004
Angelo Dureghello1f15cb82019-01-19 10:40:38 +0100100#define PROCTL_D3CD 0x00000008
Andy Fleming50586ef2008-10-30 16:47:16 -0500101
102#define CMDARG 0x0002e008
103
104#define XFERTYP 0x0002e00c
105#define XFERTYP_CMD(x) ((x & 0x3f) << 24)
106#define XFERTYP_CMDTYP_NORMAL 0x0
107#define XFERTYP_CMDTYP_SUSPEND 0x00400000
108#define XFERTYP_CMDTYP_RESUME 0x00800000
109#define XFERTYP_CMDTYP_ABORT 0x00c00000
110#define XFERTYP_DPSEL 0x00200000
111#define XFERTYP_CICEN 0x00100000
112#define XFERTYP_CCCEN 0x00080000
113#define XFERTYP_RSPTYP_NONE 0
114#define XFERTYP_RSPTYP_136 0x00010000
115#define XFERTYP_RSPTYP_48 0x00020000
116#define XFERTYP_RSPTYP_48_BUSY 0x00030000
117#define XFERTYP_MSBSEL 0x00000020
118#define XFERTYP_DTDSEL 0x00000010
Volodymyr Riazantsev0e1bf612015-01-20 10:16:44 -0500119#define XFERTYP_DDREN 0x00000008
Andy Fleming50586ef2008-10-30 16:47:16 -0500120#define XFERTYP_AC12EN 0x00000004
121#define XFERTYP_BCEN 0x00000002
122#define XFERTYP_DMAEN 0x00000001
123
124#define CINS_TIMEOUT 1000
Benoît Thébaudeaubcfb3652017-10-29 22:08:58 +0100125#define PIO_TIMEOUT 500
Andy Fleming50586ef2008-10-30 16:47:16 -0500126
127#define DSADDR 0x2e004
128
129#define CMDRSP0 0x2e010
130#define CMDRSP1 0x2e014
131#define CMDRSP2 0x2e018
132#define CMDRSP3 0x2e01c
133
134#define DATPORT 0x2e020
135
136#define WML 0x2e044
137#define WML_WRITE 0x00010000
Priyanka Jain32c8cfb2011-02-09 09:24:10 +0530138#ifdef CONFIG_FSL_SDHC_V2_3
139#define WML_RD_WML_MAX 0x80
140#define WML_WR_WML_MAX 0x80
141#define WML_RD_WML_MAX_VAL 0x0
142#define WML_WR_WML_MAX_VAL 0x0
143#define WML_RD_WML_MASK 0x7f
144#define WML_WR_WML_MASK 0x7f0000
145#else
146#define WML_RD_WML_MAX 0x10
147#define WML_WR_WML_MAX 0x80
148#define WML_RD_WML_MAX_VAL 0x10
149#define WML_WR_WML_MAX_VAL 0x80
Roy Zangab467c52010-02-09 18:23:33 +0800150#define WML_RD_WML_MASK 0xff
151#define WML_WR_WML_MASK 0xff0000
Priyanka Jain32c8cfb2011-02-09 09:24:10 +0530152#endif
Andy Fleming50586ef2008-10-30 16:47:16 -0500153
154#define BLKATTR 0x2e004
155#define BLKATTR_CNT(x) ((x & 0xffff) << 16)
156#define BLKATTR_SIZE(x) (x & 0x1fff)
157#define MAX_BLK_CNT 0x7fff /* so malloc will have enough room with 32M */
158
Yangbo Lu5b05fc02019-10-31 18:54:21 +0800159/* Host controller capabilities register */
160#define HOSTCAPBLT_VS18 0x04000000
161#define HOSTCAPBLT_VS30 0x02000000
162#define HOSTCAPBLT_VS33 0x01000000
163#define HOSTCAPBLT_SRS 0x00800000
164#define HOSTCAPBLT_DMAS 0x00400000
165#define HOSTCAPBLT_HSS 0x00200000
Andy Fleming50586ef2008-10-30 16:47:16 -0500166
Stefano Babicc67bee12010-02-05 15:11:27 +0100167struct fsl_esdhc_cfg {
Peng Fan5330c7d2016-03-15 17:57:50 +0800168 phys_addr_t esdhc_base;
Benoît Thébaudeaua2ac1b32012-10-01 08:36:25 +0000169 u32 sdhc_clk;
Abbas Razaaad46592013-03-25 09:13:34 +0000170 u8 max_bus_width;
Peng Fan32a91792017-06-12 17:50:53 +0800171 int vs18_enable; /* Use 1.8V if set to 1 */
Pantelis Antoniou93bfd612014-03-11 19:34:20 +0200172 struct mmc_config cfg;
Stefano Babicc67bee12010-02-05 15:11:27 +0100173};
174
175/* Select the correct accessors depending on endianess */
Wang Huanc82e9de2014-09-05 13:52:39 +0800176#if defined CONFIG_SYS_FSL_ESDHC_LE
177#define esdhc_read32 in_le32
178#define esdhc_write32 out_le32
179#define esdhc_clrsetbits32 clrsetbits_le32
180#define esdhc_clrbits32 clrbits_le32
181#define esdhc_setbits32 setbits_le32
182#elif defined(CONFIG_SYS_FSL_ESDHC_BE)
183#define esdhc_read32 in_be32
184#define esdhc_write32 out_be32
185#define esdhc_clrsetbits32 clrsetbits_be32
186#define esdhc_clrbits32 clrbits_be32
187#define esdhc_setbits32 setbits_be32
188#elif __BYTE_ORDER == __LITTLE_ENDIAN
Stefano Babicc67bee12010-02-05 15:11:27 +0100189#define esdhc_read32 in_le32
190#define esdhc_write32 out_le32
191#define esdhc_clrsetbits32 clrsetbits_le32
192#define esdhc_clrbits32 clrbits_le32
193#define esdhc_setbits32 setbits_le32
194#elif __BYTE_ORDER == __BIG_ENDIAN
195#define esdhc_read32 in_be32
196#define esdhc_write32 out_be32
197#define esdhc_clrsetbits32 clrsetbits_be32
198#define esdhc_clrbits32 clrbits_be32
199#define esdhc_setbits32 setbits_be32
200#else
201#error "Endianess is not defined: please fix to continue"
202#endif
203
Anton Vorontsovb33433a2009-06-10 00:25:29 +0400204#ifdef CONFIG_FSL_ESDHC
Andy Fleming50586ef2008-10-30 16:47:16 -0500205int fsl_esdhc_mmc_init(bd_t *bis);
Stefano Babicc67bee12010-02-05 15:11:27 +0100206int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg);
Anton Vorontsovb33433a2009-06-10 00:25:29 +0400207void fdt_fixup_esdhc(void *blob, bd_t *bd);
Yinbo Zhu6f883e52019-07-16 15:09:11 +0800208#ifdef MMC_SUPPORTS_TUNING
209static inline int fsl_esdhc_execute_tuning(struct udevice *dev,
210 uint32_t opcode) {return 0; }
211#endif
Anton Vorontsovb33433a2009-06-10 00:25:29 +0400212#else
213static inline int fsl_esdhc_mmc_init(bd_t *bis) { return -ENOSYS; }
214static inline void fdt_fixup_esdhc(void *blob, bd_t *bd) {}
215#endif /* CONFIG_FSL_ESDHC */
Ying Zhangbb0dc102013-08-16 15:16:11 +0800216void __noreturn mmc_boot(void);
Prabhakar Kushwaha1eaa7422014-04-08 19:13:22 +0530217void mmc_spl_load_image(uint32_t offs, unsigned int size, void *vdst);
Andy Fleming50586ef2008-10-30 16:47:16 -0500218
219#endif /* __FSL_ESDHC_H__ */