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Andy Fleming67431052007-04-23 02:54:25 -05001/*
2 * Copyright 2007 Freescale Semiconductor.
3 *
Wolfgang Denk3765b3e2013-10-07 13:07:26 +02004 * SPDX-License-Identifier: GPL-2.0+
Andy Fleming67431052007-04-23 02:54:25 -05005 */
6
7#include <common.h>
Anton Vorontsovad162242007-10-22 18:12:46 +04008#include <asm/io.h>
9
Andy Fleming67431052007-04-23 02:54:25 -050010#include "bcsr.h"
11
Kim Phillipse56143e2012-10-29 13:34:38 +000012void enable_8568mds_duart(void)
Andy Fleming67431052007-04-23 02:54:25 -050013{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020014 volatile uint* duart_mux = (uint *)(CONFIG_SYS_CCSRBAR + 0xe0060);
15 volatile uint* devices = (uint *)(CONFIG_SYS_CCSRBAR + 0xe0070);
16 volatile u8 *bcsr = (u8 *)(CONFIG_SYS_BCSR);
Andy Fleming67431052007-04-23 02:54:25 -050017
18 *duart_mux = 0x80000000; /* Set the mux to Duart on PMUXCR */
19 *devices = 0; /* Enable all peripheral devices */
20 bcsr[5] |= 0x01; /* Enable Duart in BCSR*/
21}
22
Kim Phillipse56143e2012-10-29 13:34:38 +000023void enable_8568mds_flash_write(void)
Andy Fleming67431052007-04-23 02:54:25 -050024{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020025 volatile u8 *bcsr = (u8 *)(CONFIG_SYS_BCSR);
Andy Fleming67431052007-04-23 02:54:25 -050026
27 bcsr[9] |= 0x01;
28}
29
Kim Phillipse56143e2012-10-29 13:34:38 +000030void disable_8568mds_flash_write(void)
Andy Fleming67431052007-04-23 02:54:25 -050031{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020032 volatile u8 *bcsr = (u8 *)(CONFIG_SYS_BCSR);
Andy Fleming67431052007-04-23 02:54:25 -050033
34 bcsr[9] &= ~(0x01);
35}
Andy Flemingda9d4612007-08-14 00:14:25 -050036
Kim Phillipse56143e2012-10-29 13:34:38 +000037void enable_8568mds_qe_mdio(void)
Andy Flemingda9d4612007-08-14 00:14:25 -050038{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020039 u8 *bcsr = (u8 *)(CONFIG_SYS_BCSR);
Andy Flemingda9d4612007-08-14 00:14:25 -050040
41 bcsr[7] |= 0x01;
42}
Anton Vorontsovad162242007-10-22 18:12:46 +040043
44#if defined(CONFIG_UEC_ETH1) || defined(CONFIG_UEC_ETH2)
45void reset_8568mds_uccs(void)
46{
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020047 volatile u8 *bcsr = (u8 *)(CONFIG_SYS_BCSR);
Anton Vorontsovad162242007-10-22 18:12:46 +040048
49 /* Turn off UCC1 & UCC2 */
50 out_8(&bcsr[8], in_8(&bcsr[8]) & ~BCSR_UCC1_GETH_EN);
51 out_8(&bcsr[9], in_8(&bcsr[9]) & ~BCSR_UCC2_GETH_EN);
52
53 /* Mode is RGMII, all bits clear */
54 out_8(&bcsr[11], in_8(&bcsr[11]) & ~(BCSR_UCC1_MODE_MSK |
55 BCSR_UCC2_MODE_MSK));
56
57 /* Turn UCC1 & UCC2 on */
58 out_8(&bcsr[8], in_8(&bcsr[8]) | BCSR_UCC1_GETH_EN);
59 out_8(&bcsr[9], in_8(&bcsr[9]) | BCSR_UCC2_GETH_EN);
60}
61#endif