Masahiro Yamada | dd84058 | 2014-07-30 14:08:14 +0900 | [diff] [blame] | 1 | CONFIG_PPC=y |
Tom Rini | 278b90c | 2018-02-03 12:10:38 -0500 | [diff] [blame] | 2 | CONFIG_SYS_TEXT_BASE=0xFEF00000 |
Mario Six | ff3bb0c | 2019-01-21 09:17:53 +0100 | [diff] [blame] | 3 | CONFIG_SYS_CLK_FREQ=66666666 |
Masahiro Yamada | dd84058 | 2014-07-30 14:08:14 +0900 | [diff] [blame] | 4 | CONFIG_MPC83xx=y |
Mario Six | 93de253 | 2019-01-21 09:17:56 +0100 | [diff] [blame] | 5 | CONFIG_HIGH_BATS=y |
Masahiro Yamada | dd84058 | 2014-07-30 14:08:14 +0900 | [diff] [blame] | 6 | CONFIG_TARGET_MPC8349ITX=y |
Mario Six | 21c1502 | 2019-01-21 09:17:54 +0100 | [diff] [blame] | 7 | CONFIG_DDR_MC_CLOCK_MODE_1_1=y |
| 8 | CONFIG_SYSTEM_PLL_FACTOR_4_1=y |
| 9 | CONFIG_CORE_PLL_RATIO_2_1=y |
| 10 | CONFIG_PCI_HOST_MODE_ENABLE=y |
| 11 | CONFIG_PCI_INT_ARBITER1_ENABLE=y |
| 12 | CONFIG_PCI_INT_ARBITER2_ENABLE=y |
| 13 | CONFIG_BOOT_ROM_INTERFACE_GPCM_16BIT=y |
| 14 | CONFIG_TSEC1_MODE_GMII=y |
| 15 | CONFIG_TSEC2_MODE_GMII=y |
Mario Six | 30915ab | 2019-01-21 09:17:57 +0100 | [diff] [blame] | 16 | CONFIG_BAT0=y |
| 17 | CONFIG_BAT0_NAME="SDRAM" |
| 18 | CONFIG_BAT0_BASE=0x00000000 |
| 19 | CONFIG_BAT0_LENGTH_256_MBYTES=y |
| 20 | CONFIG_BAT0_ACCESS_RW=y |
| 21 | CONFIG_BAT0_ICACHE_MEMORYCOHERENCE=y |
| 22 | CONFIG_BAT0_DCACHE_MEMORYCOHERENCE=y |
| 23 | CONFIG_BAT0_USER_MODE_VALID=y |
| 24 | CONFIG_BAT0_SUPERVISOR_MODE_VALID=y |
| 25 | CONFIG_BAT1=y |
| 26 | CONFIG_BAT1_NAME="PCI1_MEM" |
| 27 | CONFIG_BAT1_BASE=0x80000000 |
| 28 | CONFIG_BAT1_LENGTH_256_MBYTES=y |
| 29 | CONFIG_BAT1_ACCESS_RW=y |
| 30 | CONFIG_BAT1_ICACHE_MEMORYCOHERENCE=y |
| 31 | CONFIG_BAT1_DCACHE_MEMORYCOHERENCE=y |
| 32 | CONFIG_BAT1_USER_MODE_VALID=y |
| 33 | CONFIG_BAT1_SUPERVISOR_MODE_VALID=y |
| 34 | CONFIG_BAT2=y |
| 35 | CONFIG_BAT2_NAME="PCI1_MMIO" |
| 36 | CONFIG_BAT2_BASE=0x90000000 |
| 37 | CONFIG_BAT2_LENGTH_256_MBYTES=y |
| 38 | CONFIG_BAT2_ACCESS_RW=y |
| 39 | CONFIG_BAT2_ICACHE_INHIBITED=y |
| 40 | CONFIG_BAT2_ICACHE_GUARDED=y |
| 41 | CONFIG_BAT2_DCACHE_INHIBITED=y |
| 42 | CONFIG_BAT2_DCACHE_GUARDED=y |
| 43 | CONFIG_BAT2_USER_MODE_VALID=y |
| 44 | CONFIG_BAT2_SUPERVISOR_MODE_VALID=y |
| 45 | CONFIG_BAT3=y |
| 46 | CONFIG_BAT3_NAME="PCI2_MEM" |
| 47 | CONFIG_BAT3_BASE=0xA0000000 |
| 48 | CONFIG_BAT3_LENGTH_256_MBYTES=y |
| 49 | CONFIG_BAT3_ACCESS_RW=y |
| 50 | CONFIG_BAT3_ICACHE_MEMORYCOHERENCE=y |
| 51 | CONFIG_BAT3_DCACHE_MEMORYCOHERENCE=y |
| 52 | CONFIG_BAT3_USER_MODE_VALID=y |
| 53 | CONFIG_BAT3_SUPERVISOR_MODE_VALID=y |
| 54 | CONFIG_BAT4=y |
| 55 | CONFIG_BAT4_NAME="PCI2_MMIO" |
| 56 | CONFIG_BAT4_BASE=0xB0000000 |
| 57 | CONFIG_BAT4_LENGTH_256_MBYTES=y |
| 58 | CONFIG_BAT4_ACCESS_RW=y |
| 59 | CONFIG_BAT4_ICACHE_INHIBITED=y |
| 60 | CONFIG_BAT4_ICACHE_GUARDED=y |
| 61 | CONFIG_BAT4_DCACHE_INHIBITED=y |
| 62 | CONFIG_BAT4_DCACHE_GUARDED=y |
| 63 | CONFIG_BAT4_USER_MODE_VALID=y |
| 64 | CONFIG_BAT4_SUPERVISOR_MODE_VALID=y |
| 65 | CONFIG_BAT5=y |
| 66 | CONFIG_BAT5_NAME="IMMR" |
| 67 | CONFIG_BAT5_BASE=0xE0000000 |
| 68 | CONFIG_BAT5_LENGTH_256_MBYTES=y |
| 69 | CONFIG_BAT5_ACCESS_RW=y |
| 70 | CONFIG_BAT5_ICACHE_INHIBITED=y |
| 71 | CONFIG_BAT5_ICACHE_GUARDED=y |
| 72 | CONFIG_BAT5_DCACHE_INHIBITED=y |
| 73 | CONFIG_BAT5_DCACHE_GUARDED=y |
| 74 | CONFIG_BAT5_USER_MODE_VALID=y |
| 75 | CONFIG_BAT5_SUPERVISOR_MODE_VALID=y |
| 76 | CONFIG_BAT6=y |
| 77 | CONFIG_BAT6_NAME="STACK_IN_DCACHE" |
| 78 | CONFIG_BAT6_BASE=0xF0000000 |
| 79 | CONFIG_BAT6_LENGTH_256_MBYTES=y |
| 80 | CONFIG_BAT6_ACCESS_RW=y |
| 81 | CONFIG_BAT6_ICACHE_MEMORYCOHERENCE=y |
| 82 | CONFIG_BAT6_ICACHE_GUARDED=y |
| 83 | CONFIG_BAT6_DCACHE_MEMORYCOHERENCE=y |
| 84 | CONFIG_BAT6_DCACHE_GUARDED=y |
| 85 | CONFIG_BAT6_USER_MODE_VALID=y |
| 86 | CONFIG_BAT6_SUPERVISOR_MODE_VALID=y |
Mario Six | 9c5df7a | 2019-01-21 09:17:58 +0100 | [diff] [blame] | 87 | CONFIG_LBLAW0=y |
| 88 | CONFIG_LBLAW0_BASE=0xFE000000 |
| 89 | CONFIG_LBLAW0_NAME="FLASH" |
| 90 | CONFIG_LBLAW0_LENGTH_16_MBYTES=y |
| 91 | CONFIG_LBLAW1=y |
| 92 | CONFIG_LBLAW1_BASE=0xF8000000 |
| 93 | CONFIG_LBLAW1_NAME="VSC7385" |
| 94 | CONFIG_LBLAW1_LENGTH_128_KBYTES=y |
| 95 | CONFIG_LBLAW3=y |
| 96 | CONFIG_LBLAW3_BASE=0xF0000000 |
| 97 | CONFIG_LBLAW3_NAME="CF" |
| 98 | CONFIG_LBLAW3_LENGTH_64_KBYTES=y |
Mario Six | be5abb0 | 2019-01-21 09:18:09 +0100 | [diff] [blame] | 99 | CONFIG_HID0_FINAL_ICE=y |
| 100 | CONFIG_HID2_HBE=y |
Mario Six | 73df96a | 2019-01-21 09:18:12 +0100 | [diff] [blame^] | 101 | CONFIG_ACR_PIPE_DEP_4=y |
| 102 | CONFIG_ACR_RPTCNT_4=y |
Simon Glass | 73223f0 | 2016-02-22 22:55:43 -0700 | [diff] [blame] | 103 | CONFIG_OF_BOARD_SETUP=y |
| 104 | CONFIG_OF_STDOUT_VIA_ALIAS=y |
Heiko Schocher | bb597c0 | 2016-06-07 08:31:14 +0200 | [diff] [blame] | 105 | CONFIG_BOOTDELAY=6 |
Sam Protsenko | 5abc1a4 | 2017-08-14 20:22:17 +0300 | [diff] [blame] | 106 | CONFIG_USE_BOOTARGS=y |
| 107 | CONFIG_BOOTARGS="root=/dev/nfs rw nfsroot=:/nfsroot/rootfs ip=::::mpc8349emitx:eth0:off console=ttyS0,115200" |
Adam Ford | 8ccf98b | 2018-07-29 13:13:29 -0500 | [diff] [blame] | 108 | CONFIG_MISC_INIT_R=y |
Tom Rini | adad96e | 2016-04-21 21:37:19 -0400 | [diff] [blame] | 109 | CONFIG_HUSH_PARSER=y |
Nikita Kiryanov | 181bd9d | 2015-08-03 12:36:58 +0300 | [diff] [blame] | 110 | CONFIG_SYS_PROMPT="MPC8349E-mITX> " |
Tuomas Tynkkynen | ad12dc1 | 2017-10-08 21:48:01 +0300 | [diff] [blame] | 111 | CONFIG_CMD_IMLS=y |
Simon Glass | 75eb997 | 2017-05-17 03:25:29 -0600 | [diff] [blame] | 112 | CONFIG_CMD_IDE=y |
Tom Rini | 78d1e1d | 2016-04-22 16:41:25 -0400 | [diff] [blame] | 113 | CONFIG_CMD_I2C=y |
Simon Glass | 6500ec7 | 2017-08-04 16:34:34 -0600 | [diff] [blame] | 114 | CONFIG_CMD_PCI=y |
Tom Rini | 8866312 | 2017-08-14 19:58:53 -0400 | [diff] [blame] | 115 | CONFIG_CMD_SATA=y |
Simon Glass | efce244 | 2017-08-04 16:34:45 -0600 | [diff] [blame] | 116 | CONFIG_CMD_SDRAM=y |
Tom Rini | 8866312 | 2017-08-14 19:58:53 -0400 | [diff] [blame] | 117 | CONFIG_CMD_USB=y |
Bin Meng | 80df691 | 2015-09-28 05:14:15 -0700 | [diff] [blame] | 118 | # CONFIG_CMD_SETEXPR is not set |
Tom Rini | 78d1e1d | 2016-04-22 16:41:25 -0400 | [diff] [blame] | 119 | CONFIG_CMD_DHCP=y |
| 120 | CONFIG_CMD_PING=y |
Tom Rini | 89cb2b5 | 2016-04-24 17:29:26 -0400 | [diff] [blame] | 121 | CONFIG_CMD_CACHE=y |
Chris Packham | c9032ce | 2017-04-29 15:20:28 +1200 | [diff] [blame] | 122 | CONFIG_CMD_DATE=y |
Tom Rini | 89cb2b5 | 2016-04-24 17:29:26 -0400 | [diff] [blame] | 123 | CONFIG_CMD_EXT2=y |
| 124 | CONFIG_CMD_FAT=y |
Tuomas Tynkkynen | 32f0398 | 2017-12-08 15:36:15 +0200 | [diff] [blame] | 125 | CONFIG_SATA_SIL3114=y |
Tom Rini | 8728c97 | 2017-03-13 13:48:42 -0400 | [diff] [blame] | 126 | # CONFIG_MMC is not set |
Masahiro Yamada | e856bdc | 2017-02-11 22:43:54 +0900 | [diff] [blame] | 127 | CONFIG_MTD_NOR_FLASH=y |
Adam Ford | 2fe88d4 | 2018-10-14 15:10:50 -0500 | [diff] [blame] | 128 | CONFIG_FLASH_CFI_DRIVER=y |
| 129 | CONFIG_SYS_FLASH_PROTECTION=y |
| 130 | CONFIG_SYS_FLASH_CFI=y |
Mario Six | a8ca5c8 | 2018-04-27 14:52:21 +0200 | [diff] [blame] | 131 | CONFIG_PHY_MARVELL=y |
Adam Ford | d7869b2 | 2018-07-20 23:03:57 -0500 | [diff] [blame] | 132 | CONFIG_MII=y |
Mario Six | 1715105 | 2018-03-28 14:38:18 +0200 | [diff] [blame] | 133 | CONFIG_TSEC_ENET=y |
Thomas Chou | 9e39003 | 2015-11-19 21:48:14 +0800 | [diff] [blame] | 134 | CONFIG_SYS_NS16550=y |
Tom Rini | 645176d | 2016-09-08 16:31:26 -0400 | [diff] [blame] | 135 | CONFIG_USB=y |
Tom Rini | 64d6ac5 | 2017-05-12 22:33:28 -0400 | [diff] [blame] | 136 | CONFIG_USB_EHCI_HCD=y |
Tom Rini | 645176d | 2016-09-08 16:31:26 -0400 | [diff] [blame] | 137 | CONFIG_USB_STORAGE=y |
Simon Glass | 69e173e | 2016-02-22 22:55:42 -0700 | [diff] [blame] | 138 | CONFIG_OF_LIBFDT=y |
Mario Six | fe7d654 | 2019-01-21 09:18:03 +0100 | [diff] [blame] | 139 | CONFIG_ELBC_BR0_OR0=y |
| 140 | CONFIG_BR0_OR0_NAME="FLASH" |
| 141 | CONFIG_BR0_OR0_BASE=0xFE000000 |
| 142 | CONFIG_BR0_MACHINE_GPCM=y |
| 143 | CONFIG_BR0_PORTSIZE_16BIT=y |
| 144 | CONFIG_OR0_AM_16_MBYTES=y |
| 145 | CONFIG_OR0_ACS_HALF_CYCLE_EARLIER=y |
| 146 | CONFIG_OR0_CSNT_EARLIER=y |
| 147 | CONFIG_OR0_EAD_EXTRA=y |
| 148 | CONFIG_OR0_SCY_15=y |
| 149 | CONFIG_OR0_XACS_EXTENDED=y |
| 150 | CONFIG_OR0_XAM_SET=y |
| 151 | CONFIG_OR0_TRLX_RELAXED=y |
| 152 | CONFIG_OR0_EHTR_8_CYCLE=y |
| 153 | CONFIG_ELBC_BR1_OR1=y |
| 154 | CONFIG_BR1_OR1_NAME="VSC7385" |
| 155 | CONFIG_BR1_OR1_BASE=0xF8000000 |
| 156 | CONFIG_BR1_MACHINE_GPCM=y |
| 157 | CONFIG_BR1_PORTSIZE_8BIT=y |
| 158 | CONFIG_OR1_AM_128_KBYTES=y |
| 159 | CONFIG_OR1_CSNT_EARLIER=y |
| 160 | CONFIG_OR1_EAD_EXTRA=y |
| 161 | CONFIG_OR1_SCY_15=y |
| 162 | CONFIG_OR1_SETA_EXTERNAL=y |
| 163 | CONFIG_OR1_XACS_EXTENDED=y |
| 164 | CONFIG_OR1_TRLX_RELAXED=y |
| 165 | CONFIG_OR1_EHTR_8_CYCLE=y |
| 166 | CONFIG_ELBC_BR2_OR2=y |
| 167 | CONFIG_BR2_OR2_NAME="LED" |
| 168 | CONFIG_BR2_OR2_BASE=0xF9000000 |
| 169 | CONFIG_BR2_MACHINE_GPCM=y |
| 170 | CONFIG_BR2_PORTSIZE_8BIT=y |
| 171 | CONFIG_OR2_AM_2_MBYTES=y |
| 172 | CONFIG_OR2_ACS_HALF_CYCLE_EARLIER=y |
| 173 | CONFIG_OR2_CSNT_EARLIER=y |
| 174 | CONFIG_OR2_EAD_EXTRA=y |
| 175 | CONFIG_OR2_SCY_9=y |
| 176 | CONFIG_OR2_XACS_EXTENDED=y |
| 177 | CONFIG_OR2_TRLX_RELAXED=y |
| 178 | CONFIG_OR2_EHTR_8_CYCLE=y |
| 179 | CONFIG_ELBC_BR3_OR3=y |
| 180 | CONFIG_BR3_OR3_NAME="CF" |
| 181 | CONFIG_BR3_OR3_BASE=0xF0000000 |
| 182 | CONFIG_BR3_MACHINE_UPMA=y |
| 183 | CONFIG_BR3_PORTSIZE_16BIT=y |
| 184 | CONFIG_OR3_AM_32_KBYTES=y |
| 185 | CONFIG_OR3_BI_BURSTINHIBIT=y |