Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
Dirk Eibach | 6008326 | 2017-02-22 16:07:23 +0100 | [diff] [blame] | 2 | /* |
| 3 | * Copyright (C) 2014 Stefan Roese <sr@denx.de> |
| 4 | * Copyright (C) 2016 Mario Six <mario.six@gdsys.cc> |
Dirk Eibach | 6008326 | 2017-02-22 16:07:23 +0100 | [diff] [blame] | 5 | */ |
| 6 | |
| 7 | #ifndef _CONFIG_CONTROLCENTERDC_H |
| 8 | #define _CONFIG_CONTROLCENTERDC_H |
| 9 | |
| 10 | /* |
| 11 | * High Level Configuration Options (easy to change) |
| 12 | */ |
| 13 | #define CONFIG_CUSTOMER_BOARD_SUPPORT |
| 14 | |
| 15 | #define CONFIG_SKIP_LOWLEVEL_INIT /* disable board lowlevel_init */ |
Dirk Eibach | 6008326 | 2017-02-22 16:07:23 +0100 | [diff] [blame] | 16 | |
| 17 | /* |
| 18 | * TEXT_BASE needs to be below 16MiB, since this area is scrubbed |
| 19 | * for DDR ECC byte filling in the SPL before loading the main |
| 20 | * U-Boot into it. |
| 21 | */ |
Dirk Eibach | 6008326 | 2017-02-22 16:07:23 +0100 | [diff] [blame] | 22 | |
| 23 | #define CONFIG_SYS_TCLK 250000000 /* 250MHz */ |
| 24 | |
| 25 | #define CONFIG_LOADADDR 1000000 |
| 26 | |
Dirk Eibach | 6008326 | 2017-02-22 16:07:23 +0100 | [diff] [blame] | 27 | /* |
| 28 | * SDIO/MMC Card Configuration |
| 29 | */ |
| 30 | #define CONFIG_SYS_MMC_BASE MVEBU_SDIO_BASE |
| 31 | |
| 32 | /* |
| 33 | * SATA/SCSI/AHCI configuration |
| 34 | */ |
Dirk Eibach | 6008326 | 2017-02-22 16:07:23 +0100 | [diff] [blame] | 35 | #define CONFIG_SCSI_AHCI_PLAT |
| 36 | #define CONFIG_SYS_SCSI_MAX_SCSI_ID 2 |
| 37 | #define CONFIG_SYS_SCSI_MAX_LUN 1 |
| 38 | #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \ |
| 39 | CONFIG_SYS_SCSI_MAX_LUN) |
| 40 | |
Dirk Eibach | 6008326 | 2017-02-22 16:07:23 +0100 | [diff] [blame] | 41 | /* USB/EHCI configuration */ |
| 42 | #define CONFIG_EHCI_IS_TDI |
| 43 | |
| 44 | /* Environment in SPI NOR flash */ |
Dirk Eibach | 6008326 | 2017-02-22 16:07:23 +0100 | [diff] [blame] | 45 | |
Dirk Eibach | 6008326 | 2017-02-22 16:07:23 +0100 | [diff] [blame] | 46 | #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ |
| 47 | |
| 48 | /* PCIe support */ |
| 49 | #ifndef CONFIG_SPL_BUILD |
Dirk Eibach | 6008326 | 2017-02-22 16:07:23 +0100 | [diff] [blame] | 50 | #define CONFIG_PCI_SCAN_SHOW |
| 51 | #endif |
| 52 | |
Dirk Eibach | 6008326 | 2017-02-22 16:07:23 +0100 | [diff] [blame] | 53 | /* |
| 54 | * Software (bit-bang) MII driver configuration |
| 55 | */ |
Dirk Eibach | 6008326 | 2017-02-22 16:07:23 +0100 | [diff] [blame] | 56 | #define CONFIG_BITBANGMII_MULTI |
| 57 | |
| 58 | /* SPL */ |
| 59 | /* |
| 60 | * Select the boot device here |
| 61 | * |
| 62 | * Currently supported are: |
| 63 | * SPL_BOOT_SPI_NOR_FLASH - Booting via SPI NOR flash |
| 64 | * SPL_BOOT_SDIO_MMC_CARD - Booting via SDIO/MMC card (partition 1) |
| 65 | */ |
| 66 | #define SPL_BOOT_SPI_NOR_FLASH 1 |
| 67 | #define SPL_BOOT_SDIO_MMC_CARD 2 |
| 68 | #define CONFIG_SPL_BOOT_DEVICE SPL_BOOT_SPI_NOR_FLASH |
| 69 | |
| 70 | /* Defines for SPL */ |
Dirk Eibach | 6008326 | 2017-02-22 16:07:23 +0100 | [diff] [blame] | 71 | #define CONFIG_SPL_SIZE (160 << 10) |
| 72 | |
| 73 | #if defined(CONFIG_SECURED_MODE_IMAGE) |
Dirk Eibach | 6008326 | 2017-02-22 16:07:23 +0100 | [diff] [blame] | 74 | #define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - 0x2614) |
| 75 | #else |
Dirk Eibach | 6008326 | 2017-02-22 16:07:23 +0100 | [diff] [blame] | 76 | #define CONFIG_SPL_MAX_SIZE (CONFIG_SPL_SIZE - 0x30) |
| 77 | #endif |
| 78 | |
| 79 | #define CONFIG_SPL_BSS_START_ADDR (0x40000000 + CONFIG_SPL_SIZE) |
| 80 | #define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) |
| 81 | |
| 82 | #ifdef CONFIG_SPL_BUILD |
| 83 | #define CONFIG_SYS_MALLOC_SIMPLE |
| 84 | #endif |
| 85 | |
| 86 | #define CONFIG_SPL_STACK (0x40000000 + ((212 - 16) << 10)) |
| 87 | #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) |
| 88 | |
| 89 | #define CONFIG_SPL_LIBCOMMON_SUPPORT |
| 90 | #define CONFIG_SPL_LIBGENERIC_SUPPORT |
Dirk Eibach | 6008326 | 2017-02-22 16:07:23 +0100 | [diff] [blame] | 91 | #define CONFIG_SPL_I2C_SUPPORT |
| 92 | |
| 93 | #if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SPI_NOR_FLASH |
| 94 | /* SPL related SPI defines */ |
Dirk Eibach | 6008326 | 2017-02-22 16:07:23 +0100 | [diff] [blame] | 95 | #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS |
| 96 | #endif |
| 97 | |
| 98 | #if CONFIG_SPL_BOOT_DEVICE == SPL_BOOT_SDIO_MMC_CARD |
| 99 | /* SPL related MMC defines */ |
| 100 | #define CONFIG_SPL_MMC_SUPPORT |
| 101 | #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 1 |
| 102 | #define CONFIG_SYS_MMC_U_BOOT_OFFS (168 << 10) |
| 103 | #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_MMC_U_BOOT_OFFS |
| 104 | #define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR (CONFIG_SYS_U_BOOT_OFFS / 512) |
| 105 | #ifdef CONFIG_SPL_BUILD |
| 106 | #define CONFIG_FIXED_SDHCI_ALIGNED_BUFFER 0x00180000 /* in SDRAM */ |
| 107 | #endif |
| 108 | #endif |
| 109 | |
| 110 | /* |
| 111 | * Environment Configuration |
| 112 | */ |
| 113 | #define CONFIG_ENV_OVERWRITE |
| 114 | |
| 115 | #define CONFIG_BAUDRATE 115200 |
| 116 | |
Mario Six | 5bc0543 | 2018-03-28 14:38:20 +0200 | [diff] [blame] | 117 | #define CONFIG_HOSTNAME "ccdc" |
Dirk Eibach | 6008326 | 2017-02-22 16:07:23 +0100 | [diff] [blame] | 118 | #define CONFIG_ROOTPATH "/opt/nfsroot" |
| 119 | #define CONFIG_BOOTFILE "ccdc.img" |
| 120 | |
Dirk Eibach | 6008326 | 2017-02-22 16:07:23 +0100 | [diff] [blame] | 121 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
| 122 | "netdev=eth1\0" \ |
| 123 | "consoledev=ttyS1\0" \ |
| 124 | "u-boot=u-boot.bin\0" \ |
| 125 | "bootfile_addr=1000000\0" \ |
| 126 | "keyprogram_addr=3000000\0" \ |
| 127 | "keyprogram_file=keyprogram.img\0" \ |
| 128 | "fdtfile=controlcenterdc.dtb\0" \ |
| 129 | "load=tftpboot ${loadaddr} ${u-boot}\0" \ |
| 130 | "mmcdev=0:2\0" \ |
| 131 | "update=sf probe 1:0;" \ |
| 132 | " sf erase 0 +${filesize};" \ |
| 133 | " sf write ${fileaddr} 0 ${filesize}\0" \ |
| 134 | "upd=run load update\0" \ |
| 135 | "fdt_high=0x10000000\0" \ |
| 136 | "initrd_high=0x10000000\0" \ |
| 137 | "loadkeyprogram=tpm flush_keys;" \ |
| 138 | " mmc rescan;" \ |
| 139 | " ext4load mmc ${mmcdev} ${keyprogram_addr} ${keyprogram_file};"\ |
| 140 | " source ${keyprogram_addr}:script@1\0" \ |
| 141 | "gpio1=gpio@22_25\0" \ |
| 142 | "gpio2=A29\0" \ |
| 143 | "blinkseq='0 0 0 0 2 0 2 2 3 1 3 1 0 0 2 2 3 1 3 3 2 0 2 2 3 1 1 1 " \ |
| 144 | "2 0 2 2 3 1 3 1 0 0 2 0 3 3 3 1 2 0 0 0 3 1 1 1 0 0 0 0'\0" \ |
| 145 | "bootfail=for i in ${blinkseq}; do" \ |
| 146 | " if test $i -eq 0; then" \ |
| 147 | " gpio clear ${gpio1}; gpio set ${gpio2};" \ |
| 148 | " elif test $i -eq 1; then" \ |
| 149 | " gpio clear ${gpio1}; gpio clear ${gpio2};" \ |
| 150 | " elif test $i -eq 2; then" \ |
| 151 | " gpio set ${gpio1}; gpio set ${gpio2};" \ |
| 152 | " else;" \ |
| 153 | " gpio clear ${gpio1}; gpio set ${gpio2};" \ |
| 154 | " fi; sleep 0.12; done\0" |
| 155 | |
| 156 | #define CONFIG_NFSBOOTCOMMAND \ |
| 157 | "setenv bootargs root=/dev/nfs rw " \ |
| 158 | "nfsroot=${serverip}:${rootpath} " \ |
| 159 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:${netdev}:off " \ |
| 160 | "console=${consoledev},${baudrate} ${othbootargs}; " \ |
| 161 | "tftpboot ${bootfile_addr} ${bootfile}; " \ |
| 162 | "bootm ${bootfile_addr}" |
| 163 | |
| 164 | #define CONFIG_MMCBOOTCOMMAND \ |
| 165 | "setenv bootargs root=/dev/mmcblk0p3 rw rootwait " \ |
| 166 | "console=${consoledev},${baudrate} ${othbootargs}; " \ |
| 167 | "ext2load mmc 0:2 ${bootfile_addr} ${bootfile}; " \ |
| 168 | "bootm ${bootfile_addr}" |
| 169 | |
| 170 | #define CONFIG_BOOTCOMMAND \ |
| 171 | "if env exists keyprogram; then;" \ |
| 172 | " setenv keyprogram; run nfsboot;" \ |
| 173 | " fi;" \ |
| 174 | " run dobootfail" |
| 175 | |
| 176 | /* |
| 177 | * mv-common.h should be defined after CMD configs since it used them |
| 178 | * to enable certain macros |
| 179 | */ |
| 180 | #include "mv-common.h" |
| 181 | |
| 182 | #endif /* _CONFIG_CONTROLCENTERDC_H */ |