| Michal Simek | fa822ad | 2023-09-27 11:53:33 +0200 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
| 2 | /* |
| 3 | * dts file for Xilinx ZynqMP Generic System Controller |
| 4 | * |
| 5 | * Copyright (C) 2021 - 2022, Xilinx, Inc. |
| 6 | * Copyright (C) 2022 - 2023, Advanced Micro Devices, Inc. |
| 7 | * |
| 8 | * Michal Simek <michal.simek@amd.com> |
| 9 | */ |
| 10 | |
| 11 | #include "zynqmp-sc-revB.dts" |
| 12 | |
| 13 | / { |
| 14 | model = "ZynqMP Generic System Controller"; |
| 15 | compatible = "xlnx,zynqmp-sc-revC", "xlnx,zynqmp-sc", "xlnx,zynqmp"; |
| 16 | }; |
| 17 | |
| 18 | &gem1 { /* gem1 MIO38-49, MDIO MIO50/51 */ |
| 19 | /delete-node/ mdio; |
| 20 | |
| 21 | mdio: mdio { |
| 22 | #address-cells = <1>; |
| 23 | #size-cells = <0>; |
| 24 | |
| 25 | phy0: ethernet-phy@1 { /* ADI1300 */ |
| 26 | #phy-cells = <1>; |
| 27 | compatible = "ethernet-phy-id0283.bc30"; |
| 28 | reg = <1>; |
| 29 | adi,rx-internal-delay-ps = <2400>; |
| 30 | adi,tx-internal-delay-ps = <2400>; |
| 31 | adi,fifo-depth-bits = <8>; |
| 32 | reset-gpios = <&gpio 77 GPIO_ACTIVE_LOW>; |
| 33 | reset-assert-us = <10>; |
| 34 | reset-deassert-us = <5000>; |
| 35 | }; |
| 36 | }; |
| 37 | }; |