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wdenkefa329c2004-03-23 20:18:25 +00001/*
2 * (C) Copyright 2002
3 * Kyle Harris, Nexus Technologies, Inc. kharris@nexus-tech.net
4 *
5 * (C) Copyright 2002
6 * Sysgo Real-Time Solutions, GmbH <www.elinos.com>
7 * Marius Groeger <mgroeger@sysgo.de>
8 *
9 * See file CREDITS for list of people who contributed to this
10 * project.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License as
14 * published by the Free Software Foundation; either version 2 of
15 * the License, or (at your option) any later version.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 * MA 02111-1307 USA
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
wdenkefa329c2004-03-23 20:18:25 +000032 * High Level Configuration Options
33 * (easy to change)
34 */
35#define CONFIG_PXA250 1 /* This is an PXA250 CPU */
36#define CONFIG_XM250 1 /* on a MicroSys XM250 Board */
37#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
Marek Vasut6a880e32010-10-20 21:57:34 +020038#define CONFIG_SYS_TEXT_BASE 0x0
wdenkefa329c2004-03-23 20:18:25 +000039
Jean-Christophe PLAGNIOL-VILLARDb3acb6c2009-04-05 13:06:31 +020040/* we will never enable dcache, because we have to setup MMU first */
Aneesh Ve47f2db2011-06-16 23:30:48 +000041#define CONFIG_SYS_DCACHE_OFF
Jean-Christophe PLAGNIOL-VILLARDb3acb6c2009-04-05 13:06:31 +020042
wdenkefa329c2004-03-23 20:18:25 +000043/*
44 * Size of malloc() pool; this lives below the uppermost 128 KiB which are
45 * used for the RAM copy of the uboot code
46 *
47 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020048#define CONFIG_SYS_MALLOC_LEN (256*1024)
wdenkefa329c2004-03-23 20:18:25 +000049
50/*
51 * Hardware drivers
52 */
Ben Warren7194ab82009-10-04 22:37:03 -070053#define CONFIG_NET_MULTI
54#define CONFIG_SMC91111
wdenkefa329c2004-03-23 20:18:25 +000055#define CONFIG_SMC91111_BASE 0x04000300
56#undef CONFIG_SMC91111_EXT_PHY
57#define CONFIG_SMC_USE_32_BIT
58#undef CONFIG_SHOW_ACTIVITY
59#define CONFIG_NET_RETRY_COUNT 10 /* # of retries */
60
61/*
62 * I2C bus
63 */
Lei Wen68432c22011-04-13 23:48:16 +053064#define CONFIG_I2C_MV 1
Lei Wen3df619e2011-04-13 23:48:31 +053065#define CONFIG_MV_I2C_REG 0x40301680
wdenkefa329c2004-03-23 20:18:25 +000066#define CONFIG_HARD_I2C 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020067#define CONFIG_SYS_I2C_SPEED 50000
68#define CONFIG_SYS_I2C_SLAVE 0xfe
wdenkefa329c2004-03-23 20:18:25 +000069
70#define CONFIG_RTC_PCF8563 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020071#define CONFIG_SYS_I2C_RTC_ADDR 0x51
wdenkefa329c2004-03-23 20:18:25 +000072
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020073#define CONFIG_SYS_I2C_EEPROM_ADDR 0x58 /* A0 = 0 (hardwired) */
74#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4 /* 4 bits = 16 octets */
75#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* between stop and start */
76#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* length of address */
77#define CONFIG_SYS_EEPROM_SIZE 2048 /* size in bytes */
78#undef CONFIG_SYS_I2C_INIT_BOARD /* board has no own init */
wdenkefa329c2004-03-23 20:18:25 +000079
80/*
81 * select serial console configuration
82 */
Jean-Christophe PLAGNIOL-VILLARD379be582009-05-16 22:48:46 +020083#define CONFIG_PXA_SERIAL
wdenkefa329c2004-03-23 20:18:25 +000084#define CONFIG_FFUART 1 /* we use FFUART */
85
86/* allow to overwrite serial and ethaddr */
87#define CONFIG_ENV_OVERWRITE
88
89#define CONFIG_BAUDRATE 115200
90
wdenkefa329c2004-03-23 20:18:25 +000091
Jon Loeligerdca3b3d2007-07-04 22:33:46 -050092/*
Jon Loeliger079a1362007-07-10 10:12:10 -050093 * BOOTP options
94 */
95#define CONFIG_BOOTP_BOOTFILESIZE
96#define CONFIG_BOOTP_BOOTPATH
97#define CONFIG_BOOTP_GATEWAY
98#define CONFIG_BOOTP_HOSTNAME
99
100
101/*
Jon Loeligerdca3b3d2007-07-04 22:33:46 -0500102 * Command line configuration.
103 */
104#include <config_cmd_default.h>
105
106#define CONFIG_CMD_ELF
107#define CONFIG_CMD_EEPROM
108#define CONFIG_CMD_DATE
109#define CONFIG_CMD_I2C
110
wdenkefa329c2004-03-23 20:18:25 +0000111
112#define CONFIG_BOOTDELAY 3
113
114/*
115 * Miscellaneous configurable options
116 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200117#define CONFIG_SYS_LONGHELP /* undef to save memory */
118#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
119#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
120#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
121#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
122#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenkefa329c2004-03-23 20:18:25 +0000123
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200124#define CONFIG_SYS_MEMTEST_START 0xa0400000 /* memtest works on */
125#define CONFIG_SYS_MEMTEST_END 0xa0800000 /* 4 ... 8 MB in DRAM */
wdenkefa329c2004-03-23 20:18:25 +0000126
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200127#define CONFIG_SYS_LOAD_ADDR 0xa3000000 /* default load address */
wdenkefa329c2004-03-23 20:18:25 +0000128
Micha Kalfon94a33122009-02-11 19:50:11 +0200129#define CONFIG_SYS_HZ 1000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200130#define CONFIG_SYS_CPUSPEED 0x161 /* set core clock to 400/400/100 MHz */
wdenkefa329c2004-03-23 20:18:25 +0000131
132 /* valid baudrates */
133
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200134#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
wdenkefa329c2004-03-23 20:18:25 +0000135
136/*
137 * Definitions related to passing arguments to kernel.
138 */
Wolfgang Denk2c33a382006-07-21 11:36:48 +0200139#define CONFIG_CMDLINE_TAG 1 /* send commandline to Kernel */
140#define CONFIG_SETUP_MEMORY_TAGS 1 /* send memory definition to kernel */
141#define CONFIG_INITRD_TAG 1 /* do not send initrd params */
wdenkefa329c2004-03-23 20:18:25 +0000142
143/*
144 * Stack sizes
145 *
146 * The stack sizes are set up in start.S using the settings below
147 */
148#define CONFIG_STACKSIZE (128*1024) /* regular stack */
149#ifdef CONFIG_USE_IRQ
150#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */
151#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */
152#endif
153
154/*
155 * Physical Memory Map
156 */
157#define CONFIG_NR_DRAM_BANKS 4
158#define PHYS_SDRAM_1 0xa0000000 /* SDRAM Bank #1 */
159#define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */
160#define PHYS_SDRAM_2 0xa4000000 /* SDRAM Bank #2 */
161#define PHYS_SDRAM_2_SIZE 0x00000000 /* 0 MB */
162#define PHYS_SDRAM_3 0xa8000000 /* SDRAM Bank #3 */
163#define PHYS_SDRAM_3_SIZE 0x00000000 /* 0 MB */
164#define PHYS_SDRAM_4 0xac000000 /* SDRAM Bank #4 */
165#define PHYS_SDRAM_4_SIZE 0x00000000 /* 0 MB */
166
167#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
168#define PHYS_FLASH_2 0x04000000 /* Flash Bank #1 */
169#define PHYS_FLASH_SIZE 0x01000000 /* 16 MB */
170#define PHYS_FLASH_BANK_SIZE 0x01000000 /* 16 MB Banks */
171#define PHYS_FLASH_SECT_SIZE 0x00040000 /* 256 KB sectors (x2) */
172
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173#define CONFIG_SYS_DRAM_BASE 0xa0000000
174#define CONFIG_SYS_DRAM_SIZE 0x04000000
wdenkefa329c2004-03-23 20:18:25 +0000175
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200176#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
wdenkefa329c2004-03-23 20:18:25 +0000177
Marek Vasut6ef6eb92010-09-23 09:46:57 +0200178#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200179#define CONFIG_SYS_INIT_SP_ADDR (GENERATED_GBL_DATA_SIZE + PHYS_SDRAM_1)
Marek Vasut6ef6eb92010-09-23 09:46:57 +0200180
wdenkefa329c2004-03-23 20:18:25 +0000181/*
182 * FLASH and environment organization
183 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200184#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
185#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
wdenkefa329c2004-03-23 20:18:25 +0000186
187/* timeout values are in ticks */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200188#define CONFIG_SYS_FLASH_ERASE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Erase */
189#define CONFIG_SYS_FLASH_WRITE_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Write */
190#define CONFIG_SYS_FLASH_LOCK_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Set Lock Bit */
191#define CONFIG_SYS_FLASH_UNLOCK_TOUT (2*CONFIG_SYS_HZ) /* Timeout for Flash Clear Lock Bits */
192#define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */
wdenkefa329c2004-03-23 20:18:25 +0000193
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200194#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200195#define CONFIG_ENV_ADDR (PHYS_FLASH_1 + 0x40000) /* Addr of Environment Sector */
196#define CONFIG_ENV_SIZE 0x4000
197#define CONFIG_ENV_SECT_SIZE 0x40000 /* Size of the Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200198#define CONFIG_SYS_MONITOR_LEN 0x20000 /* 128 KiB */
wdenkefa329c2004-03-23 20:18:25 +0000199
200/******************************************************************************
201 *
202 * CPU specific defines
203 *
204 ******************************************************************************/
205
206/*
207 * GPIO settings
208 *
209 * GPIO pin assignments
210 * GPIO Name Dir Out AF
211 * 0 NC
212 * 1 NC
213 * 2 SIRQ1 I
214 * 3 SIRQ2 I
215 * 4 SIRQ3 I
216 * 5 DMAACK1 O 0
217 * 6 DMAACK2 O 0
218 * 7 DMAACK3 O 0
219 * 8 TC1 O 0
220 * 9 TC2 O 0
221 * 10 TC3 O 0
222 * 11 nDMAEN O 1
223 * 12 AENCTRL O 0
224 * 13 PLDTC O 0
225 * 14 ETHIRQ I
226 * 15 NC
227 * 16 NC
228 * 17 NC
229 * 18 RDY I
230 * 19 DMASIO I
231 * 20 ETHIRQ NC
232 * 21 NC
233 * 22 PGMEN O 1 FIXME for debug only enable flash
234 * 23 NC
235 * 24 NC
236 * 25 NC
237 * 26 NC
238 * 27 NC
239 * 28 NC
240 * 29 NC
241 * 30 NC
242 * 31 NC
243 * 32 NC
244 * 33 NC
245 * 34 FFRXD I 01
246 * 35 FFCTS I 01
247 * 36 FFDCD I 01
248 * 37 FFDSR I 01
249 * 38 FFRI I 01
250 * 39 FFTXD O 1 10
251 * 40 FFDTR O 0 10
252 * 41 FFRTS O 0 10
253 * 42 RS232FOFF O 0 00
254 * 43 NC
255 * 44 NC
256 * 45 IRSL0 O 0
257 * 46 IRRX0 I 01
258 * 47 IRTX0 O 0 10
259 * 48 NC
260 * 49 nIOWE O 0
261 * 50 NC
262 * 51 NC
263 * 52 NC
264 * 53 NC
265 * 54 NC
266 * 55 NC
267 * 56 NC
268 * 57 NC
269 * 58 DKDIRQ I
270 * 59 NC
271 * 60 NC
272 * 61 NC
273 * 62 NC
274 * 63 NC
275 * 64 COMLED O 0
276 * 65 COMLED O 0
277 * 66 COMLED O 0
278 * 67 COMLED O 0
279 * 68 COMLED O 0
280 * 69 COMLED O 0
281 * 70 COMLED O 0
282 * 71 COMLED O 0
283 * 72 NC
284 * 73 NC
285 * 74 NC
286 * 75 NC
287 * 76 NC
288 * 77 NC
289 * 78 CSIO O 1
290 * 79 NC
291 * 80 CSETH O 1
292 *
293 * NOTE: All NC's are defined to be outputs
294 *
295 */
296/* Pin direction control */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200297#define CONFIG_SYS_GPDR0_VAL 0xd3808000
298#define CONFIG_SYS_GPDR1_VAL 0xfcffab83
299#define CONFIG_SYS_GPDR2_VAL 0x0001ffff
wdenkefa329c2004-03-23 20:18:25 +0000300/* Set and Clear registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200301#define CONFIG_SYS_GPSR0_VAL 0x00008000
302#define CONFIG_SYS_GPSR1_VAL 0x00ff0002
303#define CONFIG_SYS_GPSR2_VAL 0x0001c000
304#define CONFIG_SYS_GPCR0_VAL 0x00000000
305#define CONFIG_SYS_GPCR1_VAL 0x00000000
306#define CONFIG_SYS_GPCR2_VAL 0x00000000
wdenkefa329c2004-03-23 20:18:25 +0000307/* Edge detect registers (these are set by the kernel) */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200308#define CONFIG_SYS_GRER0_VAL 0x00002180
309#define CONFIG_SYS_GRER1_VAL 0x00000000
310#define CONFIG_SYS_GRER2_VAL 0x00000000
311#define CONFIG_SYS_GFER0_VAL 0x000043e0
312#define CONFIG_SYS_GFER1_VAL 0x00000000
313#define CONFIG_SYS_GFER2_VAL 0x00000000
wdenkefa329c2004-03-23 20:18:25 +0000314/* Alternate function registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200315#define CONFIG_SYS_GAFR0_L_VAL 0x80000004
316#define CONFIG_SYS_GAFR0_U_VAL 0x595a8010
317#define CONFIG_SYS_GAFR1_L_VAL 0x699a9559
318#define CONFIG_SYS_GAFR1_U_VAL 0xaaa5aaaa
319#define CONFIG_SYS_GAFR2_L_VAL 0xaaaaaaaa
320#define CONFIG_SYS_GAFR2_U_VAL 0x00000002
wdenkefa329c2004-03-23 20:18:25 +0000321
322/*
323 * Clocks, power control and interrupts
324 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200325#define CONFIG_SYS_PSSR_VAL 0x00000030
Marek Vasut6a880e32010-10-20 21:57:34 +0200326#define CONFIG_SYS_CCCR 0x00000161 /* 100 MHz memory, 400 MHz CPU, 400 Turbo */
327#define CONFIG_SYS_CKEN 0x000141ec /* FFUART and STUART enabled */
328#define CONFIG_SYS_ICMR 0x00000000 /* No interrupts enabled */
wdenkefa329c2004-03-23 20:18:25 +0000329
330/* FIXME
331 *
332 * RTC settings
333 * Watchdog
334 *
335 */
336
337/*
338 * Memory settings
339 *
340 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200341#define CONFIG_SYS_MSC0_VAL 0x122423f0 /* FLASH / LAN (cs0)/(cS1) */
342#define CONFIG_SYS_MSC1_VAL 0x35f4aa4c /* USB / ST3+ST5 (cs2)/(cS3) */
343#define CONFIG_SYS_MSC2_VAL 0x35f435fc /* IDE / BCR + WatchDog (cs4)/(cS5) */
344#define CONFIG_SYS_MDCNFG_VAL 0x000009c9
345#define CONFIG_SYS_MDMRS_VAL 0x00220022
346#define CONFIG_SYS_MDREFR_VAL 0x000da018 /* Initial setting, individual bits set in lowlevel_init.S */
Marek Vasut6a880e32010-10-20 21:57:34 +0200347#define CONFIG_SYS_FLYCNFG_VAL 0x00000000
348#define CONFIG_SYS_SXCNFG_VAL 0x00000000
wdenkefa329c2004-03-23 20:18:25 +0000349
350/*
351 * PCMCIA and CF Interfaces (NOT USED, these values from lubbock init)
352 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200353#define CONFIG_SYS_MECR_VAL 0x00000000
354#define CONFIG_SYS_MCMEM0_VAL 0x00010504
355#define CONFIG_SYS_MCMEM1_VAL 0x00010504
356#define CONFIG_SYS_MCATT0_VAL 0x00010504
357#define CONFIG_SYS_MCATT1_VAL 0x00010504
358#define CONFIG_SYS_MCIO0_VAL 0x00004715
359#define CONFIG_SYS_MCIO1_VAL 0x00004715
wdenkefa329c2004-03-23 20:18:25 +0000360
361/* Board specific defines */
362
363#ifndef __ASSEMBLY__
364
365/* global prototypes */
366void led_code(int code, int color);
367
368#endif
369
370#endif /* __CONFIG_H */