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wdenkc6097192002-11-03 00:24:07 +00001/*
wdenk414eec32005-04-02 22:37:54 +00002 * (C) Copyright 2001-2005
wdenkc6097192002-11-03 00:24:07 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/* ------------------------------------------------------------------------- */
25
26/*
27 * board/config.h - configuration options, board specific
28 */
29
30#ifndef __CONFIG_H
31#define __CONFIG_H
32
33/*
34 * High Level Configuration Options
35 * (easy to change)
36 */
37
38#define CONFIG_MPC824X 1
39#define CONFIG_MPC8245 1
40#define CONFIG_SANDPOINT 1
41
42#if 0
43#define USE_DINK32 1
44#else
45#undef USE_DINK32
46#endif
47
48#define CONFIG_CONS_INDEX 3 /* set to '3' for on-chip DUART */
49#define CONFIG_BAUDRATE 9600
50#define CONFIG_DRAM_SPEED 100 /* MHz */
51
wdenk414eec32005-04-02 22:37:54 +000052#define CONFIG_TIMESTAMP /* Print image info with timestamp */
53
wdenkc6097192002-11-03 00:24:07 +000054
Jon Loeligerfe7f7822007-07-08 15:02:44 -050055/*
Jon Loeligera1aa0bb2007-07-10 09:22:23 -050056 * BOOTP options
57 */
58#define CONFIG_BOOTP_BOOTFILESIZE
59#define CONFIG_BOOTP_BOOTPATH
60#define CONFIG_BOOTP_GATEWAY
61#define CONFIG_BOOTP_HOSTNAME
62
63
64/*
Jon Loeligerfe7f7822007-07-08 15:02:44 -050065 * Command line configuration.
66 */
67#include <config_cmd_default.h>
68
69#define CONFIG_CMD_DHCP
70#define CONFIG_CMD_ELF
71#define CONFIG_CMD_I2C
72#define CONFIG_CMD_EEPROM
73#define CONFIG_CMD_NFS
74#define CONFIG_CMD_PCI
75#define CONFIG_CMD_SNTP
wdenkc6097192002-11-03 00:24:07 +000076
77
78/*
79 * Miscellaneous configurable options
80 */
81#define CFG_LONGHELP 1 /* undef to save memory */
82#define CFG_PROMPT "=> " /* Monitor Command Prompt */
83#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
84#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
85#define CFG_MAXARGS 16 /* max number of command args */
86#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
87#define CFG_LOAD_ADDR 0x00100000 /* default load address */
88#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
89
90/*-----------------------------------------------------------------------
91 * PCI stuff
92 *-----------------------------------------------------------------------
93 */
94#define CONFIG_PCI /* include pci support */
95#undef CONFIG_PCI_PNP
96
97#define CONFIG_NET_MULTI /* Multi ethernet cards support */
98
99#define CONFIG_EEPRO100
stroese53cf9432003-06-05 15:39:44 +0000100#define CFG_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
wdenkc6097192002-11-03 00:24:07 +0000101#define CONFIG_NATSEMI
102#define CONFIG_NS8382X
103
104#define PCI_ENET0_IOADDR 0x80000000
105#define PCI_ENET0_MEMADDR 0x80000000
106#define PCI_ENET1_IOADDR 0x81000000
107#define PCI_ENET1_MEMADDR 0x81000000
108
109
110/*-----------------------------------------------------------------------
111 * Start addresses for the final memory configuration
112 * (Set up by the startup code)
113 * Please note that CFG_SDRAM_BASE _must_ start at 0
114 */
115#define CFG_SDRAM_BASE 0x00000000
116#define CFG_MAX_RAM_SIZE 0x10000000
117
118#define CFG_RESET_ADDRESS 0xFFF00100
119
120#if defined (USE_DINK32)
121#define CFG_MONITOR_LEN 0x00030000
122#define CFG_MONITOR_BASE 0x00090000
123#define CFG_RAMBOOT 1
124#define CFG_INIT_RAM_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN)
125#define CFG_INIT_RAM_END 0x10000
126#define CFG_GBL_DATA_SIZE 256 /* size in bytes reserved for initial data */
127#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
128#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
129#else
130#undef CFG_RAMBOOT
131#define CFG_MONITOR_LEN 0x00030000
132#define CFG_MONITOR_BASE TEXT_BASE
133
134/*#define CFG_GBL_DATA_SIZE 256*/
135#define CFG_GBL_DATA_SIZE 128
136
137#define CFG_INIT_RAM_ADDR 0x40000000
138#define CFG_INIT_RAM_END 0x1000
139#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
140
141#endif
142
143#define CFG_FLASH_BASE 0xFFF00000
144#if 0
145#define CFG_FLASH_SIZE (512 * 1024) /* sandpoint has tiny eeprom */
146#else
147#define CFG_FLASH_SIZE (1024 * 1024) /* Unity has onboard 1MByte flash */
148#endif
149#define CFG_ENV_IS_IN_FLASH 1
150#define CFG_ENV_OFFSET 0x00004000 /* Offset of Environment Sector */
151#define CFG_ENV_SIZE 0x00002000 /* Total Size of Environment Sector */
152
153#define CFG_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */
154
155#define CFG_MEMTEST_START 0x00000000 /* memtest works on */
156#define CFG_MEMTEST_END 0x04000000 /* 0 ... 32 MB in DRAM */
157
158#define CFG_EUMB_ADDR 0xFC000000
159
160#define CFG_ISA_MEM 0xFD000000
161#define CFG_ISA_IO 0xFE000000
162
163#define CFG_FLASH_RANGE_BASE 0xFF000000 /* flash memory address range */
164#define CFG_FLASH_RANGE_SIZE 0x01000000
165#define FLASH_BASE0_PRELIM 0xFFF00000 /* sandpoint flash */
166#define FLASH_BASE1_PRELIM 0xFF000000 /* PMC onboard flash */
167
168/*
169 * select i2c support configuration
170 *
171 * Supported configurations are {none, software, hardware} drivers.
172 * If the software driver is chosen, there are some additional
173 * configuration items that the driver uses to drive the port pins.
174 */
175#define CONFIG_HARD_I2C 1 /* To enable I2C support */
176#undef CONFIG_SOFT_I2C /* I2C bit-banged */
177#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
178#define CFG_I2C_SLAVE 0x7F
179
180#ifdef CONFIG_SOFT_I2C
181#error "Soft I2C is not configured properly. Please review!"
182#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
183#define I2C_ACTIVE (iop->pdir |= 0x00010000)
184#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
185#define I2C_READ ((iop->pdat & 0x00010000) != 0)
186#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
187 else iop->pdat &= ~0x00010000
188#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
189 else iop->pdat &= ~0x00020000
190#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
191#endif /* CONFIG_SOFT_I2C */
192
193#define CFG_I2C_EEPROM_ADDR 0x57 /* EEPROM IS24C02 */
194#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
195#define CFG_EEPROM_PAGE_WRITE_BITS 3
196#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
197
198#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
199#define CFG_FLASH_BANKS { FLASH_BASE0_PRELIM , FLASH_BASE1_PRELIM }
200
201/*-----------------------------------------------------------------------
202 * Definitions for initial stack pointer and data area (in DPRAM)
203 */
204
205
206#define CFG_WINBOND_83C553 1 /*has a winbond bridge */
207#define CFG_USE_WINBOND_IDE 0 /*use winbond 83c553 internal IDE ctrlr */
208#define CFG_WINBOND_ISA_CFG_ADDR 0x80005800 /*pci-isa bridge config addr */
209#define CFG_WINBOND_IDE_CFG_ADDR 0x80005900 /*ide config addr */
210
211#define CFG_IDE_MAXBUS 2 /* max. 2 IDE busses */
212#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
213
214/*
215 * NS87308 Configuration
216 */
217#define CFG_NS87308 /* Nat Semi super-io controller on ISA bus */
218
219#define CFG_NS87308_BADDR_10 1
220
221#define CFG_NS87308_DEVS ( CFG_NS87308_UART1 | \
222 CFG_NS87308_UART2 | \
223 CFG_NS87308_POWRMAN | \
224 CFG_NS87308_RTC_APC )
225
226#undef CFG_NS87308_PS2MOD
227
228#define CFG_NS87308_CS0_BASE 0x0076
229#define CFG_NS87308_CS0_CONF 0x30
230#define CFG_NS87308_CS1_BASE 0x0075
231#define CFG_NS87308_CS1_CONF 0x30
232#define CFG_NS87308_CS2_BASE 0x0074
233#define CFG_NS87308_CS2_CONF 0x30
234
235/*
236 * NS16550 Configuration
237 */
238#define CFG_NS16550
239#define CFG_NS16550_SERIAL
240
241#define CFG_NS16550_REG_SIZE 1
242
wdenkf832d8a2004-06-10 21:55:33 +0000243#if (CONFIG_CONS_INDEX > 2)
244#define CFG_NS16550_CLK CONFIG_DRAM_SPEED*1000000
245#else
246#define CFG_NS16550_CLK 1843200
247#endif
wdenk49822e22004-06-19 21:19:10 +0000248
wdenkc6097192002-11-03 00:24:07 +0000249#define CFG_NS16550_COM1 (CFG_ISA_IO + CFG_NS87308_UART1_BASE)
250#define CFG_NS16550_COM2 (CFG_ISA_IO + CFG_NS87308_UART2_BASE)
251#define CFG_NS16550_COM3 (CFG_EUMB_ADDR + 0x4500)
252#define CFG_NS16550_COM4 (CFG_EUMB_ADDR + 0x4600)
253
254/*
255 * Low Level Configuration Settings
256 * (address mappings, register initial values, etc.)
257 * You should know what you are doing if you make changes here.
258 */
259
260#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
261
262#define CFG_ROMNAL 7 /*rom/flash next access time */
263#define CFG_ROMFAL 11 /*rom/flash access time */
264
265#define CFG_REFINT 430 /* no of clock cycles between CBR refresh cycles */
266
267/* the following are for SDRAM only*/
268#define CFG_BSTOPRE 121 /* Burst To Precharge, sets open page interval */
269#define CFG_REFREC 8 /* Refresh to activate interval */
270#define CFG_RDLAT 4 /* data latency from read command */
271#define CFG_PRETOACT 3 /* Precharge to activate interval */
272#define CFG_ACTTOPRE 5 /* Activate to Precharge interval */
273#define CFG_ACTORW 3 /* Activate to R/W */
274#define CFG_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */
275#define CFG_SDMODE_WRAP 0 /* SDMODE wrap type */
276#if 0
277#define CFG_SDMODE_BURSTLEN 2 /* OBSOLETE! SDMODE Burst length 2=4, 3=8 */
278#endif
279
280#define CFG_REGISTERD_TYPE_BUFFER 1
281#define CFG_EXTROM 1
282#define CFG_REGDIMM 0
283
284
285/* memory bank settings*/
286/*
287 * only bits 20-29 are actually used from these vales to set the
288 * start/end address the upper two bits will be 0, and the lower 20
289 * bits will be set to 0x00000 for a start address, or 0xfffff for an
290 * end address
291 */
292#define CFG_BANK0_START 0x00000000
293#define CFG_BANK0_END (CFG_MAX_RAM_SIZE - 1)
294#define CFG_BANK0_ENABLE 1
295#define CFG_BANK1_START 0x3ff00000
296#define CFG_BANK1_END 0x3fffffff
297#define CFG_BANK1_ENABLE 0
298#define CFG_BANK2_START 0x3ff00000
299#define CFG_BANK2_END 0x3fffffff
300#define CFG_BANK2_ENABLE 0
301#define CFG_BANK3_START 0x3ff00000
302#define CFG_BANK3_END 0x3fffffff
303#define CFG_BANK3_ENABLE 0
304#define CFG_BANK4_START 0x00000000
305#define CFG_BANK4_END 0x00000000
306#define CFG_BANK4_ENABLE 0
307#define CFG_BANK5_START 0x00000000
308#define CFG_BANK5_END 0x00000000
309#define CFG_BANK5_ENABLE 0
310#define CFG_BANK6_START 0x00000000
311#define CFG_BANK6_END 0x00000000
312#define CFG_BANK6_ENABLE 0
313#define CFG_BANK7_START 0x00000000
314#define CFG_BANK7_END 0x00000000
315#define CFG_BANK7_ENABLE 0
316/*
317 * Memory bank enable bitmask, specifying which of the banks defined above
318 are actually present. MSB is for bank #7, LSB is for bank #0.
319 */
320#define CFG_BANK_ENABLE 0x01
321
322#define CFG_ODCR 0xff /* configures line driver impedances, */
323 /* see 8240 book for bit definitions */
324#define CFG_PGMAX 0x32 /* how long the 8240 retains the */
325 /* currently accessed page in memory */
326 /* see 8240 book for details */
327
328/* SDRAM 0 - 256MB */
329#define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
330#define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
331
332/* stack in DCACHE @ 1GB (no backing mem) */
333#if defined(USE_DINK32)
334#define CFG_IBAT1L (0x40000000 | BATL_PP_00 )
335#define CFG_IBAT1U (0x40000000 | BATU_BL_128K )
336#else
337#define CFG_IBAT1L (CFG_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
338#define CFG_IBAT1U (CFG_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
339#endif
340
341/* PCI memory */
342#define CFG_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
343#define CFG_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
344
345/* Flash, config addrs, etc */
346#define CFG_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
347#define CFG_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
348
349#define CFG_DBAT0L CFG_IBAT0L
350#define CFG_DBAT0U CFG_IBAT0U
351#define CFG_DBAT1L CFG_IBAT1L
352#define CFG_DBAT1U CFG_IBAT1U
353#define CFG_DBAT2L CFG_IBAT2L
354#define CFG_DBAT2U CFG_IBAT2U
355#define CFG_DBAT3L CFG_IBAT3L
356#define CFG_DBAT3U CFG_IBAT3U
357
358/*
359 * For booting Linux, the board info and command line data
360 * have to be in the first 8 MB of memory, since this is
361 * the maximum mapped by the Linux kernel during initialization.
362 */
363#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
364/*-----------------------------------------------------------------------
365 * FLASH organization
366 */
367#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
368#define CFG_MAX_FLASH_SECT 20 /* max number of sectors on one chip */
369
370#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
371#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
372
373/*-----------------------------------------------------------------------
374 * Cache Configuration
375 */
376#define CFG_CACHELINE_SIZE 32 /* For MPC8240 CPU */
Jon Loeligerfe7f7822007-07-08 15:02:44 -0500377#if defined(CONFIG_CMD_KGDB)
wdenkc6097192002-11-03 00:24:07 +0000378# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
379#endif
380
381
382/*
383 * Internal Definitions
384 *
385 * Boot Flags
386 */
387#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
388#define BOOTFLAG_WARM 0x02 /* Software reboot */
389
390
391/* values according to the manual */
392
393#define CONFIG_DRAM_50MHZ 1
394#define CONFIG_SDRAM_50MHZ
395
396#undef NR_8259_INTS
397#define NR_8259_INTS 1
398
399
400#define CONFIG_DISK_SPINUP_TIME 1000000
401
402
403#endif /* __CONFIG_H */