Tom Rini | 83d290c | 2018-05-06 17:58:06 -0400 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0 |
Kever Yang | 6ba5405 | 2017-11-03 15:16:12 +0800 | [diff] [blame] | 2 | /* |
| 3 | * (C) Copyright 2017 Rockchip Electronics Co., Ltd |
Kever Yang | 6ba5405 | 2017-11-03 15:16:12 +0800 | [diff] [blame] | 4 | */ |
| 5 | |
| 6 | #include <common.h> |
| 7 | #include <dm.h> |
| 8 | #include <errno.h> |
| 9 | #include <sysreset.h> |
| 10 | #include <asm/io.h> |
| 11 | #include <asm/arch/clock.h> |
| 12 | #include <asm/arch/cru_rk3328.h> |
| 13 | #include <asm/arch/hardware.h> |
| 14 | #include <linux/err.h> |
| 15 | |
| 16 | int rockchip_sysreset_request(struct udevice *dev, enum sysreset_t type) |
| 17 | { |
| 18 | struct sysreset_reg *offset = dev_get_priv(dev); |
| 19 | unsigned long cru_base = (unsigned long)rockchip_get_cru(); |
| 20 | |
| 21 | if (IS_ERR_VALUE(cru_base)) |
| 22 | return (int)cru_base; |
| 23 | |
| 24 | switch (type) { |
| 25 | case SYSRESET_WARM: |
| 26 | writel(0xeca8, cru_base + offset->glb_srst_snd_value); |
| 27 | break; |
| 28 | case SYSRESET_COLD: |
| 29 | writel(0xfdb9, cru_base + offset->glb_srst_fst_value); |
| 30 | break; |
| 31 | default: |
| 32 | return -EPROTONOSUPPORT; |
| 33 | } |
| 34 | |
| 35 | return -EINPROGRESS; |
| 36 | } |
| 37 | |
| 38 | static struct sysreset_ops rockchip_sysreset = { |
| 39 | .request = rockchip_sysreset_request, |
| 40 | }; |
| 41 | |
| 42 | U_BOOT_DRIVER(sysreset_rockchip) = { |
| 43 | .name = "rockchip_sysreset", |
| 44 | .id = UCLASS_SYSRESET, |
| 45 | .ops = &rockchip_sysreset, |
| 46 | }; |