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Stefan Roese5fef24c2020-06-30 12:08:58 +02001/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright (C) 2019-2020
4 * Marvell <www.marvell.com>
5 */
6
7#ifndef __OCTEON_COMMON_H__
8#define __OCTEON_COMMON_H__
9
Stefan Roese63051d62020-09-02 08:29:10 +020010#if defined(CONFIG_RAM_OCTEON)
Stefan Roese63051d62020-09-02 08:29:10 +020011#define CONFIG_SYS_INIT_SP_OFFSET 0x20100000
12#else
13/* No DDR init -> run in L2 cache with limited resources */
Stefan Roese63051d62020-09-02 08:29:10 +020014#define CONFIG_SYS_INIT_SP_OFFSET 0x00180000
15#endif
16
Stefan Roese5fef24c2020-06-30 12:08:58 +020017#define CONFIG_SYS_SDRAM_BASE 0xffffffff80000000
Stefan Roese5fef24c2020-06-30 12:08:58 +020018
Stefan Roese14715602020-08-20 07:22:04 +020019#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* 64M */
20
Stefan Roese5fef24c2020-06-30 12:08:58 +020021#endif /* __OCTEON_COMMON_H__ */