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Wolfgang Denk875c7892005-09-25 16:44:21 +02001/*
2 * (C) Copyright 2002
3 * Rich Ireland, Enterasys Networks, rireland@enterasys.com.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 *
23 */
24
25#ifndef _SPARTAN3_H_
26#define _SPARTAN3_H_
27
28#include <xilinx.h>
29
30extern int Spartan3_load( Xilinx_desc *desc, void *image, size_t size );
31extern int Spartan3_dump( Xilinx_desc *desc, void *buf, size_t bsize );
32extern int Spartan3_info( Xilinx_desc *desc );
33extern int Spartan3_reloc( Xilinx_desc *desc, ulong reloc_off );
34
35/* Slave Parallel Implementation function table */
36typedef struct {
37 Xilinx_pre_fn pre;
38 Xilinx_pgm_fn pgm;
39 Xilinx_init_fn init;
40 Xilinx_err_fn err;
41 Xilinx_done_fn done;
42 Xilinx_clk_fn clk;
43 Xilinx_cs_fn cs;
44 Xilinx_wr_fn wr;
45 Xilinx_rdata_fn rdata;
46 Xilinx_wdata_fn wdata;
47 Xilinx_busy_fn busy;
48 Xilinx_abort_fn abort;
49 Xilinx_post_fn post;
Wolfgang Denk53677ef2008-05-20 16:00:29 +020050 int relocated;
Wolfgang Denk875c7892005-09-25 16:44:21 +020051} Xilinx_Spartan3_Slave_Parallel_fns;
52
53/* Slave Serial Implementation function table */
54typedef struct {
55 Xilinx_pre_fn pre;
56 Xilinx_pgm_fn pgm;
57 Xilinx_clk_fn clk;
58 Xilinx_init_fn init;
59 Xilinx_done_fn done;
60 Xilinx_wr_fn wr;
Matthias Fuchs21d39d52007-12-27 17:12:43 +010061 Xilinx_post_fn post;
Wolfgang Denk53677ef2008-05-20 16:00:29 +020062 int relocated;
Wolfgang Denk875c7892005-09-25 16:44:21 +020063} Xilinx_Spartan3_Slave_Serial_fns;
64
65/* Device Image Sizes
66 *********************************************************************/
67/* Spartan-III (1.2V) */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020068#define XILINX_XC3S50_SIZE 439264/8
69#define XILINX_XC3S200_SIZE 1047616/8
70#define XILINX_XC3S400_SIZE 1699136/8
71#define XILINX_XC3S1000_SIZE 3223488/8
72#define XILINX_XC3S1500_SIZE 5214784/8
73#define XILINX_XC3S2000_SIZE 7673024/8
74#define XILINX_XC3S4000_SIZE 11316864/8
75#define XILINX_XC3S5000_SIZE 13271936/8
Wolfgang Denk875c7892005-09-25 16:44:21 +020076
Bruce Adler923efd22007-08-10 14:54:47 -070077/* Spartan-3E (v3.4) */
78#define XILINX_XC3S100E_SIZE 581344/8
79#define XILINX_XC3S250E_SIZE 1353728/8
80#define XILINX_XC3S500E_SIZE 2270208/8
81#define XILINX_XC3S1200E_SIZE 3841184/8
82#define XILINX_XC3S1600E_SIZE 5969696/8
83
Wolfgang Denk875c7892005-09-25 16:44:21 +020084/* Descriptor Macros
85 *********************************************************************/
Matthias Fuchs3bff4ff2007-12-27 17:12:56 +010086/* Spartan-III devices */
Wolfgang Denk875c7892005-09-25 16:44:21 +020087#define XILINX_XC3S50_DESC(iface, fn_table, cookie) \
88{ Xilinx_Spartan3, iface, XILINX_XC3S50_SIZE, fn_table, cookie }
89
90#define XILINX_XC3S200_DESC(iface, fn_table, cookie) \
91{ Xilinx_Spartan3, iface, XILINX_XC3S200_SIZE, fn_table, cookie }
92
93#define XILINX_XC3S400_DESC(iface, fn_table, cookie) \
94{ Xilinx_Spartan3, iface, XILINX_XC3S400_SIZE, fn_table, cookie }
95
96#define XILINX_XC3S1000_DESC(iface, fn_table, cookie) \
97{ Xilinx_Spartan3, iface, XILINX_XC3S1000_SIZE, fn_table, cookie }
98
99#define XILINX_XC3S1500_DESC(iface, fn_table, cookie) \
100{ Xilinx_Spartan3, iface, XILINX_XC3S1500_SIZE, fn_table, cookie }
101
102#define XILINX_XC3S2000_DESC(iface, fn_table, cookie) \
Laurent Pincharta07faf72008-09-17 17:57:34 +0200103{ Xilinx_Spartan3, iface, XILINX_XC3S2000_SIZE, fn_table, cookie }
Wolfgang Denk875c7892005-09-25 16:44:21 +0200104
105#define XILINX_XC3S4000_DESC(iface, fn_table, cookie) \
Laurent Pincharta07faf72008-09-17 17:57:34 +0200106{ Xilinx_Spartan3, iface, XILINX_XC3S4000_SIZE, fn_table, cookie }
Wolfgang Denk875c7892005-09-25 16:44:21 +0200107
108#define XILINX_XC3S5000_DESC(iface, fn_table, cookie) \
Laurent Pincharta07faf72008-09-17 17:57:34 +0200109{ Xilinx_Spartan3, iface, XILINX_XC3S5000_SIZE, fn_table, cookie }
Wolfgang Denk875c7892005-09-25 16:44:21 +0200110
Bruce Adler923efd22007-08-10 14:54:47 -0700111/* Spartan-3E devices */
112#define XILINX_XC3S100E_DESC(iface, fn_table, cookie) \
113{ Xilinx_Spartan3, iface, XILINX_XC3S100E_SIZE, fn_table, cookie }
114
115#define XILINX_XC3S250E_DESC(iface, fn_table, cookie) \
116{ Xilinx_Spartan3, iface, XILINX_XC3S250E_SIZE, fn_table, cookie }
117
118#define XILINX_XC3S500E_DESC(iface, fn_table, cookie) \
119{ Xilinx_Spartan3, iface, XILINX_XC3S500E_SIZE, fn_table, cookie }
120
121#define XILINX_XC3S1200E_DESC(iface, fn_table, cookie) \
122{ Xilinx_Spartan3, iface, XILINX_XC3S1200E_SIZE, fn_table, cookie }
123
124#define XILINX_XC3S1600E_DESC(iface, fn_table, cookie) \
125{ Xilinx_Spartan3, iface, XILINX_XC3S1600E_SIZE, fn_table, cookie }
126
Wolfgang Denk875c7892005-09-25 16:44:21 +0200127#endif /* _SPARTAN3_H_ */