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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / e51f2b14c4936daf3e3040bddb15f63d35e6d988 / . / drivers / pci / Kconfig
blob: c20a0cc06077833a1db854f473ae32c206df9fe6 [file] [log] [blame]
Tom Riniaf273822016-10-26 17:15:37 -0400[diff] [blame]1menuconfig PCI
2 bool "PCI support"
Bin Meng6bf89de2017-07-30 06:23:09 -0700[diff] [blame]3 default y if PPC
Tom Riniaf273822016-10-26 17:15:37 -0400[diff] [blame]4 help
5 Enable support for PCI (Peripheral Interconnect Bus), a type of bus
6 used on some devices to allow the CPU to communicate with its
7 peripherals.
8
9if PCI
Simon Glassff3e0772015-03-05 12:25:25 -0700[diff] [blame]10
11config DM_PCI
Marcel Ziswilere090fdb2016-12-19 15:38:05 +0100[diff] [blame]12 bool "Enable driver model for PCI"
Simon Glassff3e0772015-03-05 12:25:25 -0700[diff] [blame]13 depends on DM
14 help
15 Use driver model for PCI. Driver model is the new method for
16 orgnising devices in U-Boot. For PCI, driver model keeps track of
17 available PCI devices, allows scanning of PCI buses and provides
18 device configuration support.
19
Simon Glass3ba5f742015-11-26 19:51:30 -0700[diff] [blame]20config DM_PCI_COMPAT
21 bool "Enable compatible functions for PCI"
22 depends on DM_PCI
23 help
24 Enable compatibility functions for PCI so that old code can be used
25 with CONFIG_DM_PCI enabled. This should be used as an interim
26 measure when porting a board to use driver model for PCI. Once the
27 board is fully supported, this option should be disabled.
28
Wilson Dinge51f2b12018-03-26 15:57:29 +0800[diff] [blame^]29config PCI_AARDVARK
30 bool "Enable Aardvark PCIe driver"
31 default n
32 depends on DM_PCI
33 depends on ARMADA_3700
34 help
35 Say Y here if you want to enable PCIe controller support on
36 Armada37x0 SoCs. The PCIe controller on Armada37x0 is based on
37 Aardvark hardware.
38
Bin Mengc4762152016-10-16 23:35:18 -0700[diff] [blame]39config PCI_PNP
40 bool "Enable Plug & Play support for PCI"
41 depends on PCI || DM_PCI
42 default y
43 help
44 Enable PCI memory and I/O space resource allocation and assignment.
45
Tuomas Tynkkynen3675cb02017-09-19 23:18:06 +0300[diff] [blame]46config PCIE_ECAM_GENERIC
47 bool "Generic ECAM-based PCI host controller support"
48 default n
49 depends on DM_PCI
50 help
51 Say Y here if you want to enable support for generic ECAM-based
52 PCIe host controllers, such as the one emulated by QEMU.
53
Shadi Ammouri182ba1a2016-10-27 13:29:41 +0200[diff] [blame]54config PCIE_DW_MVEBU
55 bool "Enable Armada-8K PCIe driver (DesignWare core)"
Shadi Ammouri182ba1a2016-10-27 13:29:41 +0200[diff] [blame]56 depends on DM_PCI
57 depends on ARMADA_8K
58 help
59 Say Y here if you want to enable PCIe controller support on
60 Armada-8K SoCs. The PCIe controller on Armada-8K is based on
61 DesignWare hardware.
62
Marek Vasut5f14f7d2018-01-18 14:35:35 +0100[diff] [blame]63config PCI_RCAR_GEN2
64 bool "Renesas RCar Gen2 PCIe driver"
65 depends on DM_PCI
66 depends on RCAR_32
67 help
68 Say Y here if you want to enable PCIe controller support on
69 Renesas RCar Gen2 SoCs. The PCIe controller on RCar Gen2 is
70 also used to access EHCI USB controller on the SoC.
71
Simon Glass537849a2015-03-05 12:25:27 -0700[diff] [blame]72config PCI_SANDBOX
73 bool "Sandbox PCI support"
74 depends on SANDBOX && DM_PCI
75 help
76 Support PCI on sandbox, as an emulated bus. This permits testing of
77 PCI feature such as bus scanning, device configuration and device
78 access. The available (emulated) devices are defined statically in
79 the device tree but the normal PCI scan technique is used to find
80 then.
81
Simon Glassfde7e182015-11-19 20:26:55 -0700[diff] [blame]82config PCI_TEGRA
83 bool "Tegra PCI support"
84 depends on TEGRA
Stephen Warrenbbc5b362016-08-05 16:10:34 -0600[diff] [blame]85 depends on (TEGRA186 && POWER_DOMAIN) || (!TEGRA186)
Simon Glassfde7e182015-11-19 20:26:55 -0700[diff] [blame]86 help
87 Enable support for the PCIe controller found on some generations of
88 Tegra. Tegra20 has 2 root ports with a total of 4 lanes, Tegra30 has
89 3 root ports with a total of 6 lanes and Tegra124 has 2 root ports
90 with a total of 5 lanes. Some boards require this for Ethernet
91 support to work (e.g. beaver, jetson-tk1).
92
Paul Burtona29e45a2016-09-08 07:47:31 +0100[diff] [blame]93config PCI_XILINX
94 bool "Xilinx AXI Bridge for PCI Express"
95 depends on DM_PCI
96 help
97 Enable support for the Xilinx AXI bridge for PCI express, an IP block
98 which can be used on some generations of Xilinx FPGAs.
99
Minghuan Lian80afc632016-12-13 14:54:17 +0800[diff] [blame]100config PCIE_LAYERSCAPE
101 bool "Layerscape PCIe support"
102 depends on DM_PCI
103 help
104 Support Layerscape PCIe. The Layerscape SoC may have one or several
105 PCIe controllers. The PCIe may works in RC or EP mode according to
106 RCW[HOST_AGT_PEX] setting.
107
Tom Riniaf273822016-10-26 17:15:37 -0400[diff] [blame]108endif