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Bryan Wudf3443d2014-06-24 11:45:29 +09001/*
Alexandre Courbot871d78e2015-07-09 16:33:00 +09002 * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved.
Bryan Wudf3443d2014-06-24 11:45:29 +09003 *
Tom Rini5b8031c2016-01-14 22:05:13 -05004 * SPDX-License-Identifier: GPL-2.0
Bryan Wudf3443d2014-06-24 11:45:29 +09005 */
6
7/* Tegra vpr routines */
8
9#include <common.h>
10#include <asm/io.h>
11#include <asm/arch/tegra.h>
12#include <asm/arch/mc.h>
13
Alexandre Courbot871d78e2015-07-09 16:33:00 +090014#include <fdt_support.h>
15
16static bool _configured;
17
Alexandre Courboteca676b2015-10-19 13:57:03 +090018void tegra_gpu_config(void)
Bryan Wudf3443d2014-06-24 11:45:29 +090019{
20 struct mc_ctlr *mc = (struct mc_ctlr *)NV_PA_MC_BASE;
21
22 /* Turn VPR off */
23 writel(0, &mc->mc_video_protect_size_mb);
24 writel(TEGRA_MC_VIDEO_PROTECT_REG_WRITE_ACCESS_DISABLED,
25 &mc->mc_video_protect_reg_ctrl);
26 /* read back to ensure the write went through */
27 readl(&mc->mc_video_protect_reg_ctrl);
Alexandre Courbot871d78e2015-07-09 16:33:00 +090028
29 debug("configured VPR\n");
30
31 _configured = true;
32}
33
Alexandre Courbota38a3c42015-07-09 16:33:01 +090034#if defined(CONFIG_OF_LIBFDT)
35
Alexandre Courboteca676b2015-10-19 13:57:03 +090036int tegra_gpu_enable_node(void *blob, const char *gpupath)
Alexandre Courbota38a3c42015-07-09 16:33:01 +090037{
38 int offset;
39
Alexandre Courbot36e5f7c2015-10-19 13:57:01 +090040 if (_configured) {
Alexandre Courbota38a3c42015-07-09 16:33:01 +090041 offset = fdt_path_offset(blob, gpupath);
42 if (offset > 0) {
43 fdt_status_okay(blob, offset);
44 debug("enabled GPU node %s\n", gpupath);
45 }
46 }
47
48 return 0;
49}
50
51#endif