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wdenk7ebf7442002-11-02 23:17:16 +00001/*
2 * (C) Copyright 2001 Sysgo Real-Time Solutions, GmbH <www.elinos.com>
3 * Andreas Heppel <aheppel@sysgo.de>
4 * (C) Copyright 2001 ELTEC Elektronik AG
5 * Frank Gottschling <fgottschling@eltec.de>
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26#include <common.h>
27#include <command.h>
28#include <mpc106.h>
29#include <mk48t59.h>
30#include <74xx_7xx.h>
31#include <ns87308.h>
32#include <video_fb.h>
33
34/*---------------------------------------------------------------------------*/
35/*
36 * Get Bus clock frequency
37 */
38ulong bab7xx_get_bus_freq (void)
39{
wdenkbf9e3b32004-02-12 00:47:09 +000040 /*
41 * The GPIO Port 1 on BAB7xx reflects the bus speed.
42 */
43 volatile struct GPIO *gpio =
44 (struct GPIO *) (CFG_ISA_IO + CFG_NS87308_GPIO_BASE);
wdenk7ebf7442002-11-02 23:17:16 +000045
wdenkbf9e3b32004-02-12 00:47:09 +000046 unsigned char data = gpio->dta1;
wdenk7ebf7442002-11-02 23:17:16 +000047
wdenkbf9e3b32004-02-12 00:47:09 +000048 if (data & 0x02)
49 return 66666666;
wdenk7ebf7442002-11-02 23:17:16 +000050
wdenkbf9e3b32004-02-12 00:47:09 +000051 return 83333333;
wdenk7ebf7442002-11-02 23:17:16 +000052}
53
54/*---------------------------------------------------------------------------*/
55
56/*
57 * Measure CPU clock speed (core clock GCLK1) (Approx. GCLK frequency in Hz)
58 */
59ulong bab7xx_get_gclk_freq (void)
60{
wdenkbf9e3b32004-02-12 00:47:09 +000061 static const int pllratio_to_factor[] = {
62 00, 75, 70, 00, 20, 65, 100, 45, 30, 55, 40, 50, 80, 60, 35,
63 00,
64 };
wdenk7ebf7442002-11-02 23:17:16 +000065
wdenkbf9e3b32004-02-12 00:47:09 +000066 return pllratio_to_factor[get_hid1 () >> 28] *
67 (bab7xx_get_bus_freq () / 10);
wdenk7ebf7442002-11-02 23:17:16 +000068}
69
70/*----------------------------------------------------------------------------*/
71
72int checkcpu (void)
73{
wdenkbf9e3b32004-02-12 00:47:09 +000074 uint pvr = get_pvr ();
wdenk7ebf7442002-11-02 23:17:16 +000075
wdenkbf9e3b32004-02-12 00:47:09 +000076 printf ("MPC7xx V%d.%d", (pvr >> 8) & 0xFF, pvr & 0xFF);
77 printf (" at %ld / %ld MHz\n", bab7xx_get_gclk_freq () / 1000000,
78 bab7xx_get_bus_freq () / 1000000);
wdenk7ebf7442002-11-02 23:17:16 +000079
wdenkbf9e3b32004-02-12 00:47:09 +000080 return (0);
wdenk7ebf7442002-11-02 23:17:16 +000081}
82
83/* ------------------------------------------------------------------------- */
84
85int checkboard (void)
86{
87#ifdef CFG_ADDRESS_MAP_A
wdenkbf9e3b32004-02-12 00:47:09 +000088 puts ("Board: ELTEC BAB7xx PReP\n");
wdenk7ebf7442002-11-02 23:17:16 +000089#else
wdenkbf9e3b32004-02-12 00:47:09 +000090 puts ("Board: ELTEC BAB7xx CHRP\n");
wdenk7ebf7442002-11-02 23:17:16 +000091#endif
wdenkbf9e3b32004-02-12 00:47:09 +000092 return (0);
wdenk7ebf7442002-11-02 23:17:16 +000093}
94
95/* ------------------------------------------------------------------------- */
96
97int checkflash (void)
98{
wdenkbf9e3b32004-02-12 00:47:09 +000099 /* TODO: XXX XXX XXX */
100 printf ("2 MB ## Test not implemented yet ##\n");
101 return (0);
wdenk7ebf7442002-11-02 23:17:16 +0000102}
103
104/* ------------------------------------------------------------------------- */
105
106
107static unsigned int mpc106_read_cfg_dword (unsigned int reg)
108{
wdenkbf9e3b32004-02-12 00:47:09 +0000109 unsigned int reg_addr = MPC106_REG | (reg & 0xFFFFFFFC);
wdenk7ebf7442002-11-02 23:17:16 +0000110
wdenkbf9e3b32004-02-12 00:47:09 +0000111 out32r (MPC106_REG_ADDR, reg_addr);
wdenk7ebf7442002-11-02 23:17:16 +0000112
wdenkbf9e3b32004-02-12 00:47:09 +0000113 return (in32r (MPC106_REG_DATA | (reg & 0x3)));
wdenk7ebf7442002-11-02 23:17:16 +0000114}
115
116/* ------------------------------------------------------------------------- */
117
118long int dram_size (int board_type)
119{
wdenkbf9e3b32004-02-12 00:47:09 +0000120 /* No actual initialisation to do - done when setting up
121 * PICRs MCCRs ME/SARs etc in ram_init.S.
122 */
wdenk7ebf7442002-11-02 23:17:16 +0000123
wdenkbf9e3b32004-02-12 00:47:09 +0000124 register unsigned long i, msar1, mear1, memSize;
wdenk7ebf7442002-11-02 23:17:16 +0000125
126#if defined(CFG_MEMTEST)
wdenkbf9e3b32004-02-12 00:47:09 +0000127 register unsigned long reg;
wdenk7ebf7442002-11-02 23:17:16 +0000128
wdenkbf9e3b32004-02-12 00:47:09 +0000129 printf ("Testing DRAM\n");
wdenk7ebf7442002-11-02 23:17:16 +0000130
wdenkbf9e3b32004-02-12 00:47:09 +0000131 /* write each mem addr with it's address */
132 for (reg = CFG_MEMTEST_START; reg < CFG_MEMTEST_END; reg += 4)
133 *reg = reg;
wdenk7ebf7442002-11-02 23:17:16 +0000134
wdenkbf9e3b32004-02-12 00:47:09 +0000135 for (reg = CFG_MEMTEST_START; reg < CFG_MEMTEST_END; reg += 4) {
136 if (*reg != reg)
137 return -1;
138 }
wdenk7ebf7442002-11-02 23:17:16 +0000139#endif
140
wdenkbf9e3b32004-02-12 00:47:09 +0000141 /*
142 * Since MPC106 memory controller chip has already been set to
143 * control all memory, just read and interpret its memory boundery register.
144 */
145 memSize = 0;
146 msar1 = mpc106_read_cfg_dword (MPC106_MSAR1);
147 mear1 = mpc106_read_cfg_dword (MPC106_MEAR1);
148 i = mpc106_read_cfg_dword (MPC106_MBER) & 0xf;
wdenk7ebf7442002-11-02 23:17:16 +0000149
wdenkbf9e3b32004-02-12 00:47:09 +0000150 do {
151 if (i & 0x01) /* is bank enabled ? */
152 memSize += (mear1 & 0xff) - (msar1 & 0xff) + 1;
153 msar1 >>= 8;
154 mear1 >>= 8;
155 i >>= 1;
156 } while (i);
wdenk7ebf7442002-11-02 23:17:16 +0000157
wdenkbf9e3b32004-02-12 00:47:09 +0000158 return (memSize * 0x100000);
wdenk7ebf7442002-11-02 23:17:16 +0000159}
160
161/* ------------------------------------------------------------------------- */
162
wdenkbf9e3b32004-02-12 00:47:09 +0000163long int initdram (int board_type)
wdenk7ebf7442002-11-02 23:17:16 +0000164{
wdenkbf9e3b32004-02-12 00:47:09 +0000165 return dram_size (board_type);
wdenk7ebf7442002-11-02 23:17:16 +0000166}
167
168/* ------------------------------------------------------------------------- */
169
170void after_reloc (ulong dest_addr)
171{
wdenkbf9e3b32004-02-12 00:47:09 +0000172 DECLARE_GLOBAL_DATA_PTR;
wdenk7ebf7442002-11-02 23:17:16 +0000173
wdenkbf9e3b32004-02-12 00:47:09 +0000174 /*
175 * Jump to the main U-Boot board init code
176 */
177 board_init_r ((gd_t *) gd, dest_addr);
wdenk7ebf7442002-11-02 23:17:16 +0000178}
179
180/* ------------------------------------------------------------------------- */
181
182/*
183 * do_reset is done here because in this case it is board specific, since the
184 * 7xx CPUs can only be reset by external HW (the RTC in this case).
185 */
wdenkbf9e3b32004-02-12 00:47:09 +0000186void do_reset (cmd_tbl_t * cmdtp, bd_t * bd, int flag, int argc, char *argv[])
wdenk7ebf7442002-11-02 23:17:16 +0000187{
188#if defined(CONFIG_RTC_MK48T59)
wdenkbf9e3b32004-02-12 00:47:09 +0000189 /* trigger watchdog immediately */
190 rtc_set_watchdog (1, RTC_WD_RB_16TH);
wdenk7ebf7442002-11-02 23:17:16 +0000191#else
wdenkbf9e3b32004-02-12 00:47:09 +0000192#error "You must define the macro CONFIG_RTC_MK48T59."
wdenk7ebf7442002-11-02 23:17:16 +0000193#endif
194}
195
196/* ------------------------------------------------------------------------- */
197
198#if defined(CONFIG_WATCHDOG)
199/*
200 * Since the 7xx CPUs don't have an internal watchdog, this function is
201 * board specific. We use the RTC here.
202 */
wdenkbf9e3b32004-02-12 00:47:09 +0000203void watchdog_reset (void)
wdenk7ebf7442002-11-02 23:17:16 +0000204{
205#if defined(CONFIG_RTC_MK48T59)
wdenkbf9e3b32004-02-12 00:47:09 +0000206 /* we use a 32 sec watchdog timer */
207 rtc_set_watchdog (8, RTC_WD_RB_4);
wdenk7ebf7442002-11-02 23:17:16 +0000208#else
wdenkbf9e3b32004-02-12 00:47:09 +0000209#error "You must define the macro CONFIG_RTC_MK48T59."
wdenk7ebf7442002-11-02 23:17:16 +0000210#endif
211}
wdenkbf9e3b32004-02-12 00:47:09 +0000212#endif /* CONFIG_WATCHDOG */
wdenk7ebf7442002-11-02 23:17:16 +0000213
214/* ------------------------------------------------------------------------- */
215
216#ifdef CONFIG_CONSOLE_EXTRA_INFO
217extern GraphicDevice smi;
218
219void video_get_info_str (int line_number, char *info)
220{
wdenkbf9e3b32004-02-12 00:47:09 +0000221 /* init video info strings for graphic console */
222 switch (line_number) {
223 case 1:
224 sprintf (info, " MPC7xx V%d.%d at %ld / %ld MHz",
225 (get_pvr () >> 8) & 0xFF,
226 get_pvr () & 0xFF,
227 bab7xx_get_gclk_freq () / 1000000,
228 bab7xx_get_bus_freq () / 1000000);
229 return;
230 case 2:
231 sprintf (info,
232 " ELTEC BAB7xx with %ld MB DRAM and %ld MB FLASH",
233 dram_size (0) / 0x100000, flash_init () / 0x100000);
234 return;
235 case 3:
236 sprintf (info, " %s", smi.modeIdent);
237 return;
238 }
wdenk7ebf7442002-11-02 23:17:16 +0000239
wdenkbf9e3b32004-02-12 00:47:09 +0000240 /* no more info lines */
241 *info = 0;
242 return;
wdenk7ebf7442002-11-02 23:17:16 +0000243}
244#endif
245
246/*---------------------------------------------------------------------------*/