blob: 7017fff5de7c3acf4b4d203e21c3f0bb786ea89d [file] [log] [blame]
wdenke2211742002-11-02 23:30:20 +00001/*
2 * (C) Copyright 2001
3 * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_405GP 1 /* This is a PPC405GP CPU */
37#define CONFIG_4xx 1 /* ...member of PPC405 family */
38#define CONFIG_W7O 1 /* ...on a Wave 7 Optics board */
39#define CONFIG_W7OLMC 1 /* ...specifically an LMC */
40
wdenkc837dcb2004-01-20 23:12:12 +000041#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
42#define CONFIG_MISC_INIT_F 1 /* and misc_init_f() */
wdenke2211742002-11-02 23:30:20 +000043
44#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
45
46#define CONFIG_BAUDRATE 9600
47#define CONFIG_BOOTDELAY 3 /* autoboot after 3 seconds */
48
49#if 1
50#define CONFIG_BOOTCOMMAND "bootvx" /* VxWorks boot command */
51#else
52#define CONFIG_BOOTCOMMAND "bootp" /* autoboot command */
53#endif
54
55#undef CONFIG_BOOTARGS
56
57#define CONFIG_LOADADDR F0080000
58
59#define CONFIG_ETHADDR 00:06:0D:00:00:00 /* Default, overridden at boot */
60#define CONFIG_OVERWRITE_ETHADDR_ONCE
61#define CONFIG_IPADDR 192.168.1.1
62#define CONFIG_NETMASK 255.255.255.0
63#define CONFIG_SERVERIP 192.168.1.2
64
65#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
66#undef CFG_LOADS_BAUD_CHANGE /* disallow baudrate change */
67
68#define CONFIG_MII 1 /* MII PHY management */
69#define CONFIG_PHY_ADDR 0 /* PHY address */
70
71#define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */
72
Jon Loeligera5562902007-07-08 15:31:57 -050073/*
Jon Loeligera1aa0bb2007-07-10 09:22:23 -050074 * BOOTP options
75 */
76#define CONFIG_BOOTP_BOOTFILESIZE
77#define CONFIG_BOOTP_BOOTPATH
78#define CONFIG_BOOTP_GATEWAY
79#define CONFIG_BOOTP_HOSTNAME
80
81
82/*
Jon Loeligera5562902007-07-08 15:31:57 -050083 * Command line configuration.
84 */
85#include <config_cmd_default.h>
wdenke2211742002-11-02 23:30:20 +000086
Jon Loeligera5562902007-07-08 15:31:57 -050087#define CONFIG_CMD_PCI
88#define CONFIG_CMD_IRQ
89#define CONFIG_CMD_ASKENV
90#define CONFIG_CMD_DHCP
91#define CONFIG_CMD_BEDBUG
92#define CONFIG_CMD_DATE
93#define CONFIG_CMD_I2C
94#define CONFIG_CMD_EEPROM
95#define CONFIG_CMD_ELF
96#define CONFIG_CMD_BSP
97#define CONFIG_CMD_REGINFO
wdenke2211742002-11-02 23:30:20 +000098
99#undef CONFIG_WATCHDOG /* watchdog disabled */
100#define CONFIG_HW_WATCHDOG /* HW Watchdog, board specific */
101
102#define CONFIG_SPD_EEPROM /* SPD EEPROM for SDRAM param. */
wdenkdb2f721f2003-03-06 00:58:30 +0000103#define CONFIG_SPDDRAM_SILENT /* No output if spd fails */
wdenke2211742002-11-02 23:30:20 +0000104/*
105 * Miscellaneous configurable options
106 */
107#define CFG_LONGHELP /* undef to save memory */
108#define CFG_PROMPT "Wave7Optics> " /* Monitor Command Prompt */
109#undef CFG_HUSH_PARSER /* No hush parse for U-Boot */
110#ifdef CFG_HUSH_PARSER
111#define CFG_PROMPT_HUSH_PS2 "> "
112#endif
Jon Loeligera5562902007-07-08 15:31:57 -0500113#if defined(CONFIG_CMD_KGDB)
wdenke2211742002-11-02 23:30:20 +0000114#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
115#else
116#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
117#endif
118#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
119#define CFG_MAXARGS 16 /* max number of command args */
120#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
121
122#define CFG_MEMTEST_START 0x0400000 /* memtest works on */
123#define CFG_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
124
125#undef CFG_EXT_SERIAL_CLOCK /* external serial clock */
126#define CFG_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
127#define CFG_BASE_BAUD 384000
128
129
130/* The following table includes the supported baudrates */
131#define CFG_BAUDRATE_TABLE {9600}
132
133#define CFG_CLKS_IN_HZ 1 /* everything, incl board info, in Hz */
134
135#define CFG_LOAD_ADDR 0x100000 /* default load address */
136#define CFG_EXTBDINFO 1 /* use extended board_info (bd_t) */
137
138#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
139
140/*-----------------------------------------------------------------------
141 * PCI stuff
142 *-----------------------------------------------------------------------
143 */
144#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */
145#define PCI_HOST_FORCE 1 /* configure as pci host */
146#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
147
148
149#define CONFIG_PCI /* include pci support */
150#define CONFIG_PCI_HOST PCI_HOST_AUTO /* select pci host function */
151#define CONFIG_PCI_PNP /* pci plug-and-play */
152/* resource configuration */
153#define CFG_PCI_SUBSYS_VENDORID 0x1014 /* PCI Vendor ID: IBM */
154#define CFG_PCI_SUBSYS_DEVICEID 0x0156 /* PCI Device ID: 405GP */
155#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */
156#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
157#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
158#define CFG_PCI_PTM2LA 0x00000000 /* disabled */
159#define CFG_PCI_PTM2MS 0x00000000 /* disabled */
160#define CFG_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */
161
162/*-----------------------------------------------------------------------
163 * Set up values for external bus controller
164 * used by cpu_init.c
165 *-----------------------------------------------------------------------
166 */
167 /* Don't use PerWE instead of PCI_INT ( these functions share a pin ) */
168#undef CONFIG_USE_PERWE
169
170/* use on chip memory ( OCM ) for temperary stack until sdram is tested */
171#define CFG_TEMP_STACK_OCM 1
172
173/* bank 0 is boot flash */
174/* BME=0,TWT=6,CSN=1,OEN=1,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */
175#define CFG_W7O_EBC_PB0AP 0x03050440
176/* BAS=0xFFE,BS=0x1(2MB),BU=0x3(R/W),BW=0x0(8 bits) */
177#define CFG_W7O_EBC_PB0CR 0xFFE38000
178
179/* bank 1 is main flash */
180/* BME=0,TWT=11,CSN=1,OEN=1,WBN=0,WBF=0,TH=1,RE=0,SOR=0,BEM=1,PEN=0 */
181#define CFG_EBC_PB1AP 0x05850240
182/* BAS=0xF00,BS=0x7(128MB),BU=0x3(R/W),BW=0x10(32 bits) */
183#define CFG_EBC_PB1CR 0xF00FC000
184
185/* bank 2 is RTC/NVRAM */
186/* BME=0,TWT=6,CSN=0,OEN=0,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */
187#define CFG_EBC_PB2AP 0x03000440
188/* BAS=0xFC0,BS=0x0(1MB),BU=0x3(R/W),BW=0x0(8 bits) */
189#define CFG_EBC_PB2CR 0xFC018000
190
191/* bank 3 is FPGA 0 */
192/* BME=0,TWT=4,CSN=0,OEN=0,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=0,PEN=0 */
193#define CFG_EBC_PB3AP 0x02000400
194/* BAS=0xFD0,BS=0x0(1MB),BU=0x3(R/W),BW=0x1(16 bits) */
195#define CFG_EBC_PB3CR 0xFD01A000
196
197/* bank 4 is FPGA 1 */
198/* BME=,TWT=,CSN=,OEN=,WBN=,WBF=,TH=,RE=,SOR=,BEM=,PEN= */
199#define CFG_EBC_PB4AP 0x02000400
200/* BAS=,BS=,BU=0x3(R/W),BW=0x0(8 bits) */
201#define CFG_EBC_PB4CR 0xFD11A000
202
203/* bank 5 is FPGA 2 */
204/* BME=,TWT=,CSN=,OEN=,WBN=,WBF=,TH=,RE=,SOR=,BEM=,PEN= */
205#define CFG_EBC_PB5AP 0x02000400
206/* BAS=,BS=,BU=0x3(R/W),BW=0x1(16 bits) */
207#define CFG_EBC_PB5CR 0xFD21A000
208
209/* bank 6 is unused */
210/* pb6ap = 0 */
211#define CFG_EBC_PB6AP 0x00000000
212/* pb6cr = 0 */
213#define CFG_EBC_PB6CR 0x00000000
214
215/* bank 7 is LED register */
216/* BME=0,TWT=6,CSN=1,OEN=1,WBN=0,WBF=0,TH=2,RE=0,SOR=0,BEM=1,PEN=0 */
217#define CFG_W7O_EBC_PB7AP 0x03050440
218/* BAS=0xFE0,BS=0x0(1MB),BU=0x3(R/W),BW=0x2(32 bits) */
219#define CFG_W7O_EBC_PB7CR 0xFE01C000
220
221/*-----------------------------------------------------------------------
222 * Start addresses for the final memory configuration
223 * (Set up by the startup code)
224 * Please note that CFG_SDRAM_BASE _must_ start at 0
225 */
226#define CFG_SDRAM_BASE 0x00000000
227#define CFG_FLASH_BASE 0xFFFC0000
228#define CFG_MONITOR_BASE CFG_FLASH_BASE
229#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */
230#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */
231
232/*
233 * For booting Linux, the board info and command line data
234 * have to be in the first 8 MB of memory, since this is
235 * the maximum mapped by the Linux kernel during initialization.
236 */
237#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
238/*-----------------------------------------------------------------------
239 * FLASH organization
240 */
241#define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */
242#define CFG_MAX_FLASH_SECT 256 /* max number of sec on 1 chip */
243
244#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout, Flash Erase, in ms */
245#define CFG_FLASH_WRITE_TOUT 500 /* Timeout, Flash Write, in ms */
246#define CFG_FLASH_PROTECTION 1 /* Use real Flash protection */
247
248#if 1 /* Use NVRAM for environment variables */
249/*-----------------------------------------------------------------------
250 * NVRAM organization
251 */
252#define CFG_ENV_IS_IN_NVRAM 1 /* use NVRAM for env vars */
253#define CFG_NVRAM_BASE_ADDR 0xfc000000 /* NVRAM base address */
254#define CFG_NVRAM_SIZE (32*1024) /* NVRAM size */
255#define CFG_ENV_SIZE 0x1000 /* Size of Environment vars */
256/*define CFG_ENV_ADDR \
257 (CFG_NVRAM_BASE_ADDR+CFG_NVRAM_SIZE-CFG_ENV_SIZE) Env */
258#define CFG_ENV_ADDR CFG_NVRAM_BASE_ADDR
259
260#else /* Use Boot Flash for environment variables */
261/*-----------------------------------------------------------------------
262 * Flash EEPROM for environment
263 */
264#define CFG_ENV_IS_IN_FLASH 1
265#define CFG_ENV_OFFSET 0x00040000 /* Offset of Environment Sector */
266#define CFG_ENV_SIZE 0x10000 /* Total Size of env. sector */
267
268#define CFG_ENV_SECT_SIZE 0x10000 /* see README - env sec tot sze */
269#endif
270
271/*-----------------------------------------------------------------------
272 * I2C EEPROM (CAT24WC08) for environment
273 */
274#define CONFIG_HARD_I2C /* I2c with hardware support */
275#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
276#define CFG_I2C_SLAVE 0x7F
277
278#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */
279#define CFG_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
280/* mask of address bits that overflow into the "EEPROM chip address" */
281#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x07
282#define CFG_EEPROM_PAGE_WRITE_ENABLE
283#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* The Catalyst CAT24WC08 has */
284 /* 16 byte page write mode using*/
285 /* last 4 bits of the address */
286#define CFG_I2C_MULTI_EEPROMS
287/*-----------------------------------------------------------------------
288 * Definitions for Serial Presence Detect EEPROM address
289 * (to get SDRAM settings)
290 */
291#define SPD_EEPROM_ADDRESS 0x50 /* XXX conflicting address!!! XXX */
292
wdenke2211742002-11-02 23:30:20 +0000293/*
294 * Init Memory Controller:
295 */
296#define FLASH_BASE0_PRELIM 0xFFE00000 /* FLASH bank #0 */
297#define FLASH_BASE1_PRELIM 0xF0000000 /* FLASH bank #1 */
298
299/* On Chip Memory location */
300#define CFG_OCM_DATA_ADDR 0xF8000000
301#define CFG_OCM_DATA_SIZE 0x1000
302
303/*-----------------------------------------------------------------------
304 * Definitions for initial stack pointer and data area (in RAM)
305 */
306#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of SDRAM */
307#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of used area in RAM */
308#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
309#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
310#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
311
312
313/*
314 * Internal Definitions
315 *
316 * Boot Flags
317 */
318#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
319#define BOOTFLAG_WARM 0x02 /* Software reboot */
320
Jon Loeligera5562902007-07-08 15:31:57 -0500321#if defined(CONFIG_CMD_KGDB)
wdenke2211742002-11-02 23:30:20 +0000322#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
323#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
324#endif
325
326/*
327 * FPGA(s) configuration
328 */
329#define CFG_FPGA_IMAGE_LEN 0x80000 /* 512KB FPGA image */
330#define CONFIG_NUM_FPGAS 3 /* Number of FPGAs on board */
331#define CONFIG_MAX_FPGAS 6 /* Maximum number of FPGAs */
332#define CONFIG_FPGAS_BASE 0xFD000000L /* Base address of FPGAs */
333#define CONFIG_FPGAS_BANK_SIZE 0x00100000L /* FPGAs' mmap bank size */
334
335#endif /* __CONFIG_H */