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Haavard Skinnemoen6b443942007-04-14 17:11:49 +02001/*
2 * Copyright (C) 2006 Atmel Corporation
3 *
4 * Configuration settings for the AVR32 Network Gateway
5 *
6 * See file CREDITS for list of people who contributed to this
7 * project.
8 *
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
22 * MA 02111-1307 USA
23 */
24#ifndef __CONFIG_H
25#define __CONFIG_H
26
27#define CONFIG_AVR32 1
28#define CONFIG_AT32AP 1
29#define CONFIG_AT32AP7000 1
30#define CONFIG_ATNGW100 1
31
32#define CFG_HZ 1000
33
34/*
35 * Set up the PLL to run at 140 MHz, the CPU to run at the PLL
36 * frequency, the HSB and PBB busses to run at 1/2 the PLL frequency
37 * and the PBA bus to run at 1/4 the PLL frequency.
38 */
39#define CONFIG_PLL 1
40#define CFG_POWER_MANAGER 1
41#define CFG_OSC0_HZ 20000000
42#define CFG_PLL0_DIV 1
43#define CFG_PLL0_MUL 7
44#define CFG_PLL0_SUPPRESS_CYCLES 16
45#define CFG_CLKDIV_CPU 0
46#define CFG_CLKDIV_HSB 1
47#define CFG_CLKDIV_PBA 2
48#define CFG_CLKDIV_PBB 1
49
50/*
51 * The PLLOPT register controls the PLL like this:
52 * icp = PLLOPT<2>
53 * ivco = PLLOPT<1:0>
54 *
55 * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz).
56 */
57#define CFG_PLL0_OPT 0x04
58
59#define CONFIG_USART1 1
60
61/* User serviceable stuff */
62#define CONFIG_DOS_PARTITION 1
63
64#define CONFIG_CMDLINE_TAG 1
65#define CONFIG_SETUP_MEMORY_TAGS 1
66#define CONFIG_INITRD_TAG 1
67
68#define CONFIG_STACKSIZE (2048)
69
70#define CONFIG_BAUDRATE 115200
71#define CONFIG_BOOTARGS \
72 "console=ttyS0 root=/dev/mtdblock1 rootfstype=jffs2"
73#define CONFIG_BOOTCOMMAND \
74 "fsload; bootm"
75
76/*
77 * Only interrupt autoboot if <space> is pressed. Otherwise, garbage
78 * data on the serial line may interrupt the boot sequence.
79 */
80#define CONFIG_BOOTDELAY 1
81#define CONFIG_AUTOBOOT 1
82#define CONFIG_AUTOBOOT_KEYED 1
83#define CONFIG_AUTOBOOT_PROMPT \
Wolfgang Denk33dac032008-01-23 14:41:37 +010084 "Press SPACE to abort autoboot in %d seconds\n"
Haavard Skinnemoen6b443942007-04-14 17:11:49 +020085#define CONFIG_AUTOBOOT_DELAY_STR "d"
86#define CONFIG_AUTOBOOT_STOP_STR " "
87
88/*
89 * After booting the board for the first time, new ethernet addresses
90 * should be generated and assigned to the environment variables
91 * "ethaddr" and "eth1addr". This is normally done during production.
92 */
93#define CONFIG_OVERWRITE_ETHADDR_ONCE 1
94#define CONFIG_NET_MULTI 1
95
96/*
97 * BOOTP/DHCP options
98 */
99#define CONFIG_BOOTP_SUBNETMASK
100#define CONFIG_BOOTP_GATEWAY
101
102#define CONFIG_DOS_PARTITION 1
103
104/*
105 * Command line configuration.
106 */
107#include <config_cmd_default.h>
108
109#define CONFIG_CMD_ASKENV
110#define CONFIG_CMD_DHCP
111#define CONFIG_CMD_EXT2
112#define CONFIG_CMD_FAT
113#define CONFIG_CMD_JFFS2
114#define CONFIG_CMD_MMC
115#undef CONFIG_CMD_FPGA
116#undef CONFIG_CMD_SETGETDCR
117
118#define CONFIG_ATMEL_USART 1
119#define CONFIG_MACB 1
120#define CONFIG_PIO2 1
121#define CFG_NR_PIOS 5
122#define CFG_HSDRAMC 1
123#define CONFIG_MMC 1
124
125#define CFG_DCACHE_LINESZ 32
126#define CFG_ICACHE_LINESZ 32
127
128#define CONFIG_NR_DRAM_BANKS 1
129
130#define CFG_FLASH_CFI 1
131#define CFG_FLASH_CFI_DRIVER 1
132
133#define CFG_FLASH_BASE 0x00000000
134#define CFG_FLASH_SIZE 0x800000
135#define CFG_MAX_FLASH_BANKS 1
136#define CFG_MAX_FLASH_SECT 135
137
138#define CFG_MONITOR_BASE CFG_FLASH_BASE
139
140#define CFG_INTRAM_BASE 0x24000000
141#define CFG_INTRAM_SIZE 0x8000
142
143#define CFG_SDRAM_BASE 0x10000000
144#define CFG_SDRAM_16BIT 1
145
146#define CFG_ENV_IS_IN_FLASH 1
147#define CFG_ENV_SIZE 65536
148#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_FLASH_SIZE - CFG_ENV_SIZE)
149
150#define CFG_INIT_SP_ADDR (CFG_INTRAM_BASE + CFG_INTRAM_SIZE)
151
152#define CFG_MALLOC_LEN (256*1024)
153#define CFG_MALLOC_END \
154 ({ \
155 DECLARE_GLOBAL_DATA_PTR; \
156 CFG_SDRAM_BASE + gd->sdram_size; \
157 })
158#define CFG_MALLOC_START (CFG_MALLOC_END - CFG_MALLOC_LEN)
159
160#define CFG_DMA_ALLOC_LEN (16384)
161
162/* Allow 4MB for the kernel run-time image */
163#define CFG_LOAD_ADDR (CFG_SDRAM_BASE + 0x00400000)
164#define CFG_BOOTPARAMS_LEN (16 * 1024)
165
166/* Other configuration settings that shouldn't have to change all that often */
167#define CFG_PROMPT "Uboot> "
168#define CFG_CBSIZE 256
169#define CFG_MAXARGS 16
170#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16)
171#define CFG_LONGHELP 1
172
Haavard Skinnemoen2bcacc22007-11-22 16:51:39 +0100173#define CFG_MEMTEST_START CFG_SDRAM_BASE
174#define CFG_MEMTEST_END (CFG_MEMTEST_START + 0x1f00000)
175
Haavard Skinnemoen6b443942007-04-14 17:11:49 +0200176#define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 }
177
178#endif /* __CONFIG_H */