| Vlad Lungu | 0764c16 | 2008-01-16 19:27:51 +0200 | [diff] [blame] | 1 | /* Memory sub-system initialization code */ |
| 2 | |
| 3 | #include <config.h> |
| Vlad Lungu | 0764c16 | 2008-01-16 19:27:51 +0200 | [diff] [blame] | 4 | #include <asm/regdef.h> |
| 5 | #include <asm/mipsregs.h> |
| 6 | |
| 7 | .text |
| 8 | .set noreorder |
| 9 | .set mips32 |
| 10 | |
| 11 | .globl lowlevel_init |
| 12 | lowlevel_init: |
| 13 | |
| 14 | /* |
| 15 | * Step 2) Establish Status Register |
| 16 | * (set BEV, clear ERL, clear EXL, clear IE) |
| 17 | */ |
| 18 | li t1, 0x00400000 |
| 19 | mtc0 t1, CP0_STATUS |
| 20 | |
| 21 | /* |
| 22 | * Step 3) Establish CP0 Config0 |
| 23 | * (set K0=3) |
| 24 | */ |
| 25 | li t1, 0x00000003 |
| 26 | mtc0 t1, CP0_CONFIG |
| 27 | |
| 28 | /* |
| 29 | * Step 7) Establish Cause |
| 30 | * (set IV bit) |
| 31 | */ |
| 32 | li t1, 0x00800000 |
| 33 | mtc0 t1, CP0_CAUSE |
| 34 | |
| 35 | /* Establish Wired (and Random) */ |
| 36 | mtc0 zero, CP0_WIRED |
| 37 | nop |
| 38 | |
| Shinya Kuribayashi | 43c5092 | 2008-04-17 23:35:13 +0900 | [diff] [blame] | 39 | jr ra |
| Vlad Lungu | 0764c16 | 2008-01-16 19:27:51 +0200 | [diff] [blame] | 40 | nop |