| Dario Binacchi | f4cf871 | 2023-01-28 16:55:31 +0100 | [diff] [blame] | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| 2 | /* |
| 3 | * Copyright (C) 2020 Dario Binacchi <dariobin@libero.it> |
| 4 | */ |
| 5 | |
| 6 | #ifndef _TILCDC_H |
| 7 | #define _TILCDC_H |
| 8 | |
| 9 | /** |
| 10 | * tilcdc_panel_info: Panel parameters |
| 11 | * |
| 12 | * @ac_bias: AC Bias Pin Frequency |
| 13 | * @ac_bias_intrpt: AC Bias Pin Transitions per Interrupt |
| 14 | * @dma_burst_sz: DMA burst size |
| 15 | * @bpp: Bits per pixel |
| 16 | * @fdd: FIFO DMA Request Delay |
| 17 | * @tft_alt_mode: TFT Alternative Signal Mapping (Only for active) |
| 18 | * @invert_pxl_clk: Invert pixel clock |
| 19 | * @sync_edge: Horizontal and Vertical Sync Edge: 0=rising 1=falling |
| 20 | * @sync_ctrl: Horizontal and Vertical Sync: Control: 0=ignore |
| 21 | * @raster_order: Raster Data Order Select: 1=Most-to-least 0=Least-to-most |
| 22 | * @fifo_th: DMA FIFO threshold |
| 23 | */ |
| 24 | struct tilcdc_panel_info { |
| 25 | u32 ac_bias; |
| 26 | u32 ac_bias_intrpt; |
| 27 | u32 dma_burst_sz; |
| 28 | u32 bpp; |
| 29 | u32 fdd; |
| 30 | bool tft_alt_mode; |
| 31 | bool invert_pxl_clk; |
| 32 | u32 sync_edge; |
| 33 | u32 sync_ctrl; |
| 34 | u32 raster_order; |
| 35 | u32 fifo_th; |
| 36 | }; |
| 37 | |
| 38 | #endif /* _TILCDC_H */ |