blob: 2119320da7f423d6395e4eef87dafa409790f7bc [file] [log] [blame]
Dave Liu5f820432006-11-03 19:33:44 -06001/*
2 * Copyright (C) 2006 Freescale Semiconductor, Inc.
Dave Liu5f820432006-11-03 19:33:44 -06003 * Dave Liu <daveliu@freescale.com>
Dave Liu5f820432006-11-03 19:33:44 -06004 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 */
13
14#include <common.h>
15#include <ioports.h>
16#include <mpc83xx.h>
17#include <i2c.h>
Dave Liu5f820432006-11-03 19:33:44 -060018#include <miiphy.h>
Dave Liu5f820432006-11-03 19:33:44 -060019#if defined(CONFIG_PCI)
20#include <pci.h>
21#endif
Dave Liu5f820432006-11-03 19:33:44 -060022#include <spd_sdram.h>
Dave Liu5f820432006-11-03 19:33:44 -060023#include <asm/mmu.h>
Kim Phillipsb3458d22007-12-20 15:57:28 -060024#if defined(CONFIG_OF_LIBFDT)
Gerald Van Baren213bf8c2007-03-31 12:23:51 -040025#include <libfdt.h>
Gerald Van Baren213bf8c2007-03-31 12:23:51 -040026#endif
Tony Li14778582007-08-17 10:35:59 +080027#if defined(CONFIG_PQ_MDS_PIB)
Kim Phillipse58fe952007-08-16 22:53:09 -050028#include "../common/pq-mds-pib.h"
Tony Li14778582007-08-17 10:35:59 +080029#endif
Dave Liu5f820432006-11-03 19:33:44 -060030
Dave Liu7737d5c2006-11-03 12:11:15 -060031const qe_iop_conf_t qe_iop_conf_tab[] = {
32 /* GETH1 */
33 {0, 3, 1, 0, 1}, /* TxD0 */
34 {0, 4, 1, 0, 1}, /* TxD1 */
35 {0, 5, 1, 0, 1}, /* TxD2 */
36 {0, 6, 1, 0, 1}, /* TxD3 */
37 {1, 6, 1, 0, 3}, /* TxD4 */
38 {1, 7, 1, 0, 1}, /* TxD5 */
39 {1, 9, 1, 0, 2}, /* TxD6 */
40 {1, 10, 1, 0, 2}, /* TxD7 */
41 {0, 9, 2, 0, 1}, /* RxD0 */
42 {0, 10, 2, 0, 1}, /* RxD1 */
43 {0, 11, 2, 0, 1}, /* RxD2 */
44 {0, 12, 2, 0, 1}, /* RxD3 */
45 {0, 13, 2, 0, 1}, /* RxD4 */
46 {1, 1, 2, 0, 2}, /* RxD5 */
47 {1, 0, 2, 0, 2}, /* RxD6 */
48 {1, 4, 2, 0, 2}, /* RxD7 */
49 {0, 7, 1, 0, 1}, /* TX_EN */
50 {0, 8, 1, 0, 1}, /* TX_ER */
51 {0, 15, 2, 0, 1}, /* RX_DV */
52 {0, 16, 2, 0, 1}, /* RX_ER */
53 {0, 0, 2, 0, 1}, /* RX_CLK */
54 {2, 9, 1, 0, 3}, /* GTX_CLK - CLK10 */
55 {2, 8, 2, 0, 1}, /* GTX125 - CLK9 */
56 /* GETH2 */
57 {0, 17, 1, 0, 1}, /* TxD0 */
58 {0, 18, 1, 0, 1}, /* TxD1 */
59 {0, 19, 1, 0, 1}, /* TxD2 */
60 {0, 20, 1, 0, 1}, /* TxD3 */
61 {1, 2, 1, 0, 1}, /* TxD4 */
62 {1, 3, 1, 0, 2}, /* TxD5 */
63 {1, 5, 1, 0, 3}, /* TxD6 */
64 {1, 8, 1, 0, 3}, /* TxD7 */
65 {0, 23, 2, 0, 1}, /* RxD0 */
66 {0, 24, 2, 0, 1}, /* RxD1 */
67 {0, 25, 2, 0, 1}, /* RxD2 */
68 {0, 26, 2, 0, 1}, /* RxD3 */
69 {0, 27, 2, 0, 1}, /* RxD4 */
70 {1, 12, 2, 0, 2}, /* RxD5 */
71 {1, 13, 2, 0, 3}, /* RxD6 */
72 {1, 11, 2, 0, 2}, /* RxD7 */
73 {0, 21, 1, 0, 1}, /* TX_EN */
74 {0, 22, 1, 0, 1}, /* TX_ER */
75 {0, 29, 2, 0, 1}, /* RX_DV */
76 {0, 30, 2, 0, 1}, /* RX_ER */
77 {0, 31, 2, 0, 1}, /* RX_CLK */
78 {2, 2, 1, 0, 2}, /* GTX_CLK = CLK10 */
79 {2, 3, 2, 0, 1}, /* GTX125 - CLK4 */
80
81 {0, 1, 3, 0, 2}, /* MDIO */
82 {0, 2, 1, 0, 1}, /* MDC */
83
Anton Vorontsov651d96f2007-11-14 18:54:53 +030084 {5, 0, 1, 0, 2}, /* UART2_SOUT */
85 {5, 1, 2, 0, 3}, /* UART2_CTS */
86 {5, 2, 1, 0, 1}, /* UART2_RTS */
87 {5, 3, 2, 0, 2}, /* UART2_SIN */
88
Dave Liu7737d5c2006-11-03 12:11:15 -060089 {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */
90};
91
Dave Liu5f820432006-11-03 19:33:44 -060092int board_early_init_f(void)
93{
Kim Phillips3fc0bd12007-02-14 19:50:53 -060094
95 u8 *bcsr = (u8 *)CFG_BCSR;
96 const immap_t *immr = (immap_t *)CFG_IMMR;
Dave Liu5f820432006-11-03 19:33:44 -060097
98 /* Enable flash write */
99 bcsr[0xa] &= ~0x04;
100
Kim Phillipse5c4ade2008-03-28 10:19:07 -0500101 /* Disable G1TXCLK, G2TXCLK h/w buffers (rev.2.x h/w bug workaround) */
102 if (REVID_MAJOR(immr->sysconf.spridr) == 2)
Kim Phillips3fc0bd12007-02-14 19:50:53 -0600103 bcsr[0xe] = 0x30;
104
Anton Vorontsov651d96f2007-11-14 18:54:53 +0300105 /* Enable second UART */
106 bcsr[0x9] &= ~0x01;
107
Dave Liu5f820432006-11-03 19:33:44 -0600108 return 0;
109}
110
Tony Li14778582007-08-17 10:35:59 +0800111int board_early_init_r(void)
112{
113#ifdef CONFIG_PQ_MDS_PIB
114 pib_init();
115#endif
116 return 0;
117}
118
Dave Liu5f820432006-11-03 19:33:44 -0600119#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
120extern void ddr_enable_ecc(unsigned int dram_size);
121#endif
122int fixed_sdram(void);
123void sdram_init(void);
124
125long int initdram(int board_type)
126{
Timur Tabid239d742006-11-03 12:00:28 -0600127 volatile immap_t *im = (immap_t *) CFG_IMMR;
Dave Liu5f820432006-11-03 19:33:44 -0600128 u32 msize = 0;
129
130 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
131 return -1;
132
133 /* DDR SDRAM - Main SODIMM */
134 im->sysconf.ddrlaw[0].bar = CFG_DDR_BASE & LAWBAR_BAR;
135#if defined(CONFIG_SPD_EEPROM)
136 msize = spd_sdram();
137#else
138 msize = fixed_sdram();
139#endif
140
141#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
142 /*
143 * Initialize DDR ECC byte
144 */
145 ddr_enable_ecc(msize * 1024 * 1024);
146#endif
147 /*
148 * Initialize SDRAM if it is on local bus.
149 */
150 sdram_init();
Kim Phillipsbbea46f2007-08-16 22:52:48 -0500151
Dave Liu5f820432006-11-03 19:33:44 -0600152 /* return total bus SDRAM size(bytes) -- DDR */
153 return (msize * 1024 * 1024);
154}
155
156#if !defined(CONFIG_SPD_EEPROM)
157/*************************************************************************
158 * fixed sdram init -- doesn't use serial presence detect.
159 ************************************************************************/
160int fixed_sdram(void)
161{
Timur Tabid239d742006-11-03 12:00:28 -0600162 volatile immap_t *im = (immap_t *) CFG_IMMR;
Dave Liu5f820432006-11-03 19:33:44 -0600163 u32 msize = 0;
164 u32 ddr_size;
165 u32 ddr_size_log2;
166
167 msize = CFG_DDR_SIZE;
168 for (ddr_size = msize << 20, ddr_size_log2 = 0;
169 (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) {
170 if (ddr_size & 1) {
171 return -1;
172 }
173 }
174 im->sysconf.ddrlaw[0].ar =
175 LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
176#if (CFG_DDR_SIZE != 256)
177#warning Currenly any ddr size other than 256 is not supported
178#endif
Xie Xiaobod61853c2007-02-14 18:27:17 +0800179#ifdef CONFIG_DDR_II
180 im->ddr.csbnds[0].csbnds = CFG_DDR_CS0_BNDS;
181 im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG;
182 im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0;
183 im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
184 im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
185 im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3;
186 im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG;
187 im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2;
188 im->ddr.sdram_mode = CFG_DDR_MODE;
189 im->ddr.sdram_mode2 = CFG_DDR_MODE2;
190 im->ddr.sdram_interval = CFG_DDR_INTERVAL;
191 im->ddr.sdram_clk_cntl = CFG_DDR_CLK_CNTL;
192#else
Dave Liu5f820432006-11-03 19:33:44 -0600193 im->ddr.csbnds[0].csbnds = 0x00000007;
194 im->ddr.csbnds[1].csbnds = 0x0008000f;
195
196 im->ddr.cs_config[0] = CFG_DDR_CONFIG;
197 im->ddr.cs_config[1] = CFG_DDR_CONFIG;
198
199 im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
200 im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
201 im->ddr.sdram_cfg = CFG_DDR_CONTROL;
202
203 im->ddr.sdram_mode = CFG_DDR_MODE;
204 im->ddr.sdram_interval = CFG_DDR_INTERVAL;
Xie Xiaobod61853c2007-02-14 18:27:17 +0800205#endif
Dave Liu5f820432006-11-03 19:33:44 -0600206 udelay(200);
207 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
208
209 return msize;
210}
211#endif /*!CFG_SPD_EEPROM */
212
213int checkboard(void)
214{
215 puts("Board: Freescale MPC8360EMDS\n");
216 return 0;
217}
218
219/*
220 * if MPC8360EMDS is soldered with SDRAM
221 */
222#if defined(CFG_BR2_PRELIM) \
223 && defined(CFG_OR2_PRELIM) \
224 && defined(CFG_LBLAWBAR2_PRELIM) \
225 && defined(CFG_LBLAWAR2_PRELIM)
226/*
227 * Initialize SDRAM memory on the Local Bus.
228 */
229
230void sdram_init(void)
231{
Timur Tabid239d742006-11-03 12:00:28 -0600232 volatile immap_t *immap = (immap_t *) CFG_IMMR;
Dave Liu5f820432006-11-03 19:33:44 -0600233 volatile lbus83xx_t *lbc = &immap->lbus;
234 uint *sdram_addr = (uint *) CFG_LBC_SDRAM_BASE;
235
Dave Liu5f820432006-11-03 19:33:44 -0600236 /*
237 * Setup SDRAM Base and Option Registers, already done in cpu_init.c
238 */
239 /*setup mtrpt, lsrt and lbcr for LB bus */
240 lbc->lbcr = CFG_LBC_LBCR;
241 lbc->mrtpr = CFG_LBC_MRTPR;
242 lbc->lsrt = CFG_LBC_LSRT;
243 asm("sync");
244
245 /*
246 * Configure the SDRAM controller Machine Mode Register.
247 */
248 lbc->lsdmr = CFG_LBC_LSDMR_5; /* Normal Operation */
249 lbc->lsdmr = CFG_LBC_LSDMR_1; /* Precharge All Banks */
250 asm("sync");
251 *sdram_addr = 0xff;
252 udelay(100);
253
254 /*
255 * We need do 8 times auto refresh operation.
256 */
257 lbc->lsdmr = CFG_LBC_LSDMR_2;
258 asm("sync");
259 *sdram_addr = 0xff; /* 1 times */
260 udelay(100);
261 *sdram_addr = 0xff; /* 2 times */
262 udelay(100);
263 *sdram_addr = 0xff; /* 3 times */
264 udelay(100);
265 *sdram_addr = 0xff; /* 4 times */
266 udelay(100);
267 *sdram_addr = 0xff; /* 5 times */
268 udelay(100);
269 *sdram_addr = 0xff; /* 6 times */
270 udelay(100);
271 *sdram_addr = 0xff; /* 7 times */
272 udelay(100);
273 *sdram_addr = 0xff; /* 8 times */
274 udelay(100);
275
276 /* Mode register write operation */
277 lbc->lsdmr = CFG_LBC_LSDMR_4;
278 asm("sync");
279 *(sdram_addr + 0xcc) = 0xff;
280 udelay(100);
281
282 /* Normal operation */
283 lbc->lsdmr = CFG_LBC_LSDMR_5 | 0x40000000;
284 asm("sync");
285 *sdram_addr = 0xff;
286 udelay(100);
287}
288#else
289void sdram_init(void)
290{
Dave Liu5f820432006-11-03 19:33:44 -0600291}
292#endif
293
Kim Phillips3fde9e82007-08-15 22:30:33 -0500294#if defined(CONFIG_OF_BOARD_SETUP)
295void ft_board_setup(void *blob, bd_t *bd)
Kim Phillipsbf0b5422006-11-01 00:10:40 -0600296{
Kim Phillips24f86842007-11-09 14:28:08 -0600297 const immap_t *immr = (immap_t *)CFG_IMMR;
Kim Phillipsbf0b5422006-11-01 00:10:40 -0600298
Kim Phillips3fde9e82007-08-15 22:30:33 -0500299 ft_cpu_setup(blob, bd);
Gerald Van Baren213bf8c2007-03-31 12:23:51 -0400300#ifdef CONFIG_PCI
301 ft_pci_setup(blob, bd);
302#endif
Kim Phillips24f86842007-11-09 14:28:08 -0600303 /*
304 * mpc8360ea pb mds errata 2: RGMII timing
305 * if on mpc8360ea rev. 2.1,
306 * change both ucc phy-connection-types from rgmii-id to rgmii-rxid
307 */
Kim Phillipse5c4ade2008-03-28 10:19:07 -0500308 if ((REVID_MAJOR(immr->sysconf.spridr) == 2) &&
309 (REVID_MINOR(immr->sysconf.spridr) == 1)) {
Kim Phillips24f86842007-11-09 14:28:08 -0600310 int nodeoffset;
Kim Phillipsf6020822007-12-10 14:16:22 -0600311 const char *prop;
Kim Phillips363eea92008-01-15 09:51:12 -0600312 int path;
Kim Phillips24f86842007-11-09 14:28:08 -0600313
Kim Phillipsf09880e2008-01-14 16:14:46 -0600314 nodeoffset = fdt_path_offset(blob, "/aliases");
Kim Phillips24f86842007-11-09 14:28:08 -0600315 if (nodeoffset >= 0) {
Kim Phillips5b8bc602007-12-20 14:09:22 -0600316#if defined(CONFIG_HAS_ETH0)
317 /* fixup UCC 1 if using rgmii-id mode */
Kim Phillips363eea92008-01-15 09:51:12 -0600318 prop = fdt_getprop(blob, nodeoffset, "ethernet0", NULL);
319 if (prop) {
320 path = fdt_path_offset(blob, prop);
Kim Phillipsf09880e2008-01-14 16:14:46 -0600321 prop = fdt_getprop(blob, path,
322 "phy-connection-type", 0);
Kim Phillips5b8bc602007-12-20 14:09:22 -0600323 if (prop && (strcmp(prop, "rgmii-id") == 0))
Kim Phillipsf09880e2008-01-14 16:14:46 -0600324 fdt_setprop(blob, path,
325 "phy-connection-type",
326 "rgmii-rxid",
327 sizeof("rgmii-rxid"));
Kim Phillips5b8bc602007-12-20 14:09:22 -0600328 }
329#endif
330#if defined(CONFIG_HAS_ETH1)
331 /* fixup UCC 2 if using rgmii-id mode */
Kim Phillips363eea92008-01-15 09:51:12 -0600332 prop = fdt_getprop(blob, nodeoffset, "ethernet1", NULL);
333 if (prop) {
334 path = fdt_path_offset(blob, prop);
Kim Phillipsf09880e2008-01-14 16:14:46 -0600335 prop = fdt_getprop(blob, path,
336 "phy-connection-type", 0);
Kim Phillips5b8bc602007-12-20 14:09:22 -0600337 if (prop && (strcmp(prop, "rgmii-id") == 0))
Kim Phillipsf09880e2008-01-14 16:14:46 -0600338 fdt_setprop(blob, path,
339 "phy-connection-type",
340 "rgmii-rxid",
341 sizeof("rgmii-rxid"));
Kim Phillips5b8bc602007-12-20 14:09:22 -0600342 }
343#endif
Kim Phillips24f86842007-11-09 14:28:08 -0600344 }
345 }
Kim Phillipsbf0b5422006-11-01 00:10:40 -0600346}
Kim Phillips3fde9e82007-08-15 22:30:33 -0500347#endif