blob: 87f02bfaf3f7c8eff521f9778249d479c12573c8 [file] [log] [blame]
Songjun Wu8800e0f2016-06-20 13:22:38 +08001#ifndef _AT91_I2C_H
2#define _AT91_I2C_H
3
4#define TWI_CR_START BIT(0) /* Send a Start Condition */
5#define TWI_CR_MSEN BIT(2) /* Master Transfer Enable */
6#define TWI_CR_STOP BIT(1) /* Send a Stop Condition */
7#define TWI_CR_SVDIS BIT(5) /* Slave Transfer Disable */
8#define TWI_CR_SWRST BIT(7) /* Software Reset */
9#define TWI_CR_ACMEN BIT(16) /* Alternative Command Mode Enable */
10#define TWI_CR_ACMDIS BIT(17) /* Alternative Command Mode Disable */
11#define TWI_CR_LOCKCLR BIT(26) /* Lock Clear */
12
13#define TWI_MMR_MREAD BIT(12) /* Master Read Direction */
14#define TWI_MMR_IADRSZ_1 BIT(8) /* Internal Device Address Size */
15
16#define TWI_SR_TXCOMP BIT(0) /* Transmission Complete */
17#define TWI_SR_RXRDY BIT(1) /* Receive Holding Register Ready */
18#define TWI_SR_TXRDY BIT(2) /* Transmit Holding Register Ready */
19#define TWI_SR_OVRE BIT(6) /* Overrun Error */
20#define TWI_SR_UNRE BIT(7) /* Underrun Error */
21#define TWI_SR_NACK BIT(8) /* Not Acknowledged */
22#define TWI_SR_LOCK BIT(23) /* TWI Lock due to Frame Errors */
23
24#define TWI_ACR_DATAL(len) ((len) & 0xff)
25#define TWI_ACR_DIR_READ BIT(8)
26
27#define TWI_CWGR_HOLD_MAX 0x1f
28#define TWI_CWGR_HOLD(x) (((x) & TWI_CWGR_HOLD_MAX) << 24)
29
30struct at91_i2c_regs {
31 u32 cr;
32 u32 mmr;
33 u32 smr;
34 u32 iadr;
35 u32 cwgr;
36 u32 rev_0[3];
37 u32 sr;
38 u32 ier;
39 u32 idr;
40 u32 imr;
41 u32 rhr;
42 u32 thr;
43 u32 smbtr;
44 u32 rev_1;
45 u32 acr;
46 u32 filtr;
47 u32 rev_2;
48 u32 swmr;
49 u32 fmr;
50 u32 flr;
51 u32 rev_3;
52 u32 fsr;
53 u32 fier;
54 u32 fidr;
55 u32 fimr;
56 u32 rev_4[29];
57 u32 wpmr;
58 u32 wpsr;
59 u32 rev_5[6];
60};
61
62struct at91_i2c_pdata {
63 unsigned clk_max_div;
64 unsigned clk_offset;
65};
66
67struct at91_i2c_bus {
68 struct at91_i2c_regs *regs;
69 u32 status;
70 ulong bus_clk_rate;
71 u32 clock_frequency;
72 u32 speed;
73 u32 cwgr_val;
74 const struct at91_i2c_pdata *pdata;
75};
76
77#endif