| wdenk | bf9e3b3 | 2004-02-12 00:47:09 +0000 | [diff] [blame] | 1 | /* |
| 2 | * mcf5272.h -- Definitions for Motorola Coldfire 5272 |
| 3 | * |
| 4 | * Based on mcf5272sim.h of uCLinux distribution: |
| 5 | * (C) Copyright 1999, Greg Ungerer (gerg@snapgear.com) |
| 6 | * (C) Copyright 2000, Lineo Inc. (www.lineo.com) |
| 7 | * |
| 8 | * See file CREDITS for list of people who contributed to this |
| 9 | * project. |
| 10 | * |
| 11 | * This program is free software; you can redistribute it and/or |
| 12 | * modify it under the terms of the GNU General Public License as |
| 13 | * published by the Free Software Foundation; either version 2 of |
| 14 | * the License, or (at your option) any later version. |
| 15 | * |
| 16 | * This program is distributed in the hope that it will be useful, |
| 17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 19 | * GNU General Public License for more details. |
| 20 | * |
| 21 | * You should have received a copy of the GNU General Public License |
| 22 | * along with this program; if not, write to the Free Software |
| 23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 24 | * MA 02111-1307 USA |
| 25 | */ |
| 26 | |
| 27 | |
| 28 | #ifndef mcf5272_h |
| 29 | #define mcf5272_h |
| 30 | /****************************************************************************/ |
| 31 | |
| 32 | /* |
| 33 | * Size of internal RAM |
| 34 | */ |
| 35 | |
| 36 | #define INT_RAM_SIZE 4096 |
| 37 | |
| 38 | |
| 39 | /* |
| 40 | * Define the 5272 SIM register set addresses. |
| 41 | */ |
| 42 | #define MCFSIM_SCR 0x04 /* SIM Config reg (r/w) */ |
| 43 | #define MCFSIM_SPR 0x06 /* System Protection reg (r/w)*/ |
| 44 | #define MCFSIM_PMR 0x08 /* Power Management reg (r/w) */ |
| 45 | #define MCFSIM_APMR 0x0e /* Active Low Power reg (r/w) */ |
| 46 | #define MCFSIM_DIR 0x10 /* Device Identity reg (r/w) */ |
| 47 | |
| 48 | #define MCFSIM_ICR1 0x20 /* Intr Ctrl reg 1 (r/w) */ |
| 49 | #define MCFSIM_ICR2 0x24 /* Intr Ctrl reg 2 (r/w) */ |
| 50 | #define MCFSIM_ICR3 0x28 /* Intr Ctrl reg 3 (r/w) */ |
| 51 | #define MCFSIM_ICR4 0x2c /* Intr Ctrl reg 4 (r/w) */ |
| 52 | |
| 53 | #define MCFSIM_ISR 0x30 /* Interrupt Source reg (r/w) */ |
| 54 | #define MCFSIM_PITR 0x34 /* Interrupt Transition (r/w) */ |
| 55 | #define MCFSIM_PIWR 0x38 /* Interrupt Wakeup reg (r/w) */ |
| 56 | #define MCFSIM_PIVR 0x3f /* Interrupt Vector reg (r/w( */ |
| 57 | |
| 58 | #define MCFSIM_WRRR 0x280 /* Watchdog reference (r/w) */ |
| 59 | #define MCFSIM_WIRR 0x284 /* Watchdog interrupt (r/w) */ |
| 60 | #define MCFSIM_WCR 0x288 /* Watchdog counter (r/w) */ |
| 61 | #define MCFSIM_WER 0x28c /* Watchdog event (r/w) */ |
| 62 | |
| 63 | #define MCFSIM_CSBR0 0x40 /* CS0 Base Address (r/w) */ |
| 64 | #define MCFSIM_CSOR0 0x44 /* CS0 Option (r/w) */ |
| 65 | #define MCFSIM_CSBR1 0x48 /* CS1 Base Address (r/w) */ |
| 66 | #define MCFSIM_CSOR1 0x4c /* CS1 Option (r/w) */ |
| 67 | #define MCFSIM_CSBR2 0x50 /* CS2 Base Address (r/w) */ |
| 68 | #define MCFSIM_CSOR2 0x54 /* CS2 Option (r/w) */ |
| 69 | #define MCFSIM_CSBR3 0x58 /* CS3 Base Address (r/w) */ |
| 70 | #define MCFSIM_CSOR3 0x5c /* CS3 Option (r/w) */ |
| 71 | #define MCFSIM_CSBR4 0x60 /* CS4 Base Address (r/w) */ |
| 72 | #define MCFSIM_CSOR4 0x64 /* CS4 Option (r/w) */ |
| 73 | #define MCFSIM_CSBR5 0x68 /* CS5 Base Address (r/w) */ |
| 74 | #define MCFSIM_CSOR5 0x6c /* CS5 Option (r/w) */ |
| 75 | #define MCFSIM_CSBR6 0x70 /* CS6 Base Address (r/w) */ |
| 76 | #define MCFSIM_CSOR6 0x74 /* CS6 Option (r/w) */ |
| 77 | #define MCFSIM_CSBR7 0x78 /* CS7 Base Address (r/w) */ |
| 78 | #define MCFSIM_CSOR7 0x7c /* CS7 Option (r/w) */ |
| 79 | |
| 80 | #define MCFSIM_SDCR 0x180 /* SDRAM Configuration (r/w) */ |
| 81 | #define MCFSIM_SDTR 0x184 /* SDRAM Timing (r/w) */ |
| 82 | #define MCFSIM_DCAR0 0x4c /* DRAM 0 Address reg(r/w) */ |
| 83 | #define MCFSIM_DCMR0 0x50 /* DRAM 0 Mask reg (r/w) */ |
| 84 | #define MCFSIM_DCCR0 0x57 /* DRAM 0 Control reg (r/w) */ |
| 85 | #define MCFSIM_DCAR1 0x58 /* DRAM 1 Address reg (r/w) */ |
| 86 | #define MCFSIM_DCMR1 0x5c /* DRAM 1 Mask reg (r/w) */ |
| 87 | #define MCFSIM_DCCR1 0x63 /* DRAM 1 Control reg (r/w) */ |
| 88 | |
| 89 | #define MCFSIM_PACNT 0x80 /* Port A Control (r/w) */ |
| 90 | #define MCFSIM_PADDR 0x84 /* Port A Direction (r/w) */ |
| 91 | #define MCFSIM_PADAT 0x86 /* Port A Data (r/w) */ |
| 92 | #define MCFSIM_PBCNT 0x88 /* Port B Control (r/w) */ |
| 93 | #define MCFSIM_PBDDR 0x8c /* Port B Direction (r/w) */ |
| 94 | #define MCFSIM_PBDAT 0x8e /* Port B Data (r/w) */ |
| 95 | #define MCFSIM_PCDDR 0x94 /* Port C Direction (r/w) */ |
| 96 | #define MCFSIM_PCDAT 0x96 /* Port C Data (r/w) */ |
| 97 | #define MCFSIM_PDCNT 0x98 /* Port D Control (r/w) */ |
| 98 | |
| 99 | #endif /* mcf5272_h */ |