blob: 524a3e0690c1ff6c9fdfdb1d9f76d9e79ed941d6 [file] [log] [blame]
wdenkc6097192002-11-03 00:24:07 +00001/*
wdenk414eec32005-04-02 22:37:54 +00002 * (C) Copyright 2001-2005
wdenkc6097192002-11-03 00:24:07 +00003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/* ------------------------------------------------------------------------- */
25
26/*
27 * board/config.h - configuration options, board specific
28 */
29
30#ifndef __CONFIG_H
31#define __CONFIG_H
32
33/*
34 * High Level Configuration Options
35 * (easy to change)
36 */
37
38#define CONFIG_MPC824X 1
39#define CONFIG_MPC8240 1
40#define CONFIG_SANDPOINT 1
41
Wolfgang Denk2ae18242010-10-06 09:05:45 +020042#define CONFIG_SYS_TEXT_BASE 0xFFF00000
Wolfgang Denkde550d62010-11-23 23:48:56 +010043#define CONFIG_SYS_LDSCRIPT "board/sandpoint/u-boot.lds"
Wolfgang Denk2ae18242010-10-06 09:05:45 +020044
wdenkc6097192002-11-03 00:24:07 +000045#if 0
46#define USE_DINK32 1
47#else
48#undef USE_DINK32
49#endif
50
51#define CONFIG_CONS_INDEX 1
wdenk149dded2003-09-10 18:20:28 +000052#define CONFIG_BAUDRATE 9600
53
54#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
55
56#define CONFIG_TIMESTAMP /* Print image info with timestamp */
57
58#define CONFIG_PREBOOT "echo;" \
59 "echo Type \"run net_nfs\" to mount root filesystem over NFS;" \
60 "echo"
61
62#undef CONFIG_BOOTARGS
63
64#define CONFIG_EXTRA_ENV_SETTINGS \
65 "netdev=eth0\0" \
66 "nfsargs=setenv bootargs root=/dev/nfs rw " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010067 "nfsroot=${serverip}:${rootpath}\0" \
wdenk149dded2003-09-10 18:20:28 +000068 "ramargs=setenv bootargs root=/dev/ram rw\0" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010069 "addip=setenv bootargs ${bootargs} " \
70 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
71 ":${hostname}:${netdev}:off panic=1\0" \
72 "net_self=tftp ${kernel_addr} ${bootfile};" \
73 "tftp ${ramdisk_addr} ${ramdisk};" \
wdenk149dded2003-09-10 18:20:28 +000074 "run ramargs addip;" \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010075 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
76 "net_nfs=tftp ${kernel_addr} ${bootfile};" \
wdenk149dded2003-09-10 18:20:28 +000077 "run nfsargs addip;bootm\0" \
78 "rootpath=/opt/eldk/ppc_82xx\0" \
79 "bootfile=/tftpboot/SP8240/uImage\0" \
80 "ramdisk=/tftpboot/SP8240/uRamdisk\0" \
81 "kernel_addr=200000\0" \
82 "ramdisk_addr=400000\0" \
83 ""
84#define CONFIG_BOOTCOMMAND "run flash_self"
wdenkc6097192002-11-03 00:24:07 +000085
wdenkc6097192002-11-03 00:24:07 +000086
Jon Loeligerfe7f7822007-07-08 15:02:44 -050087/*
Jon Loeligera1aa0bb2007-07-10 09:22:23 -050088 * BOOTP options
89 */
90#define CONFIG_BOOTP_BOOTFILESIZE
91#define CONFIG_BOOTP_BOOTPATH
92#define CONFIG_BOOTP_GATEWAY
93#define CONFIG_BOOTP_HOSTNAME
94
95
96/*
Jon Loeligerfe7f7822007-07-08 15:02:44 -050097 * Command line configuration.
98 */
99#include <config_cmd_default.h>
100
101#define CONFIG_CMD_DHCP
102#define CONFIG_CMD_ELF
103#define CONFIG_CMD_I2C
104#define CONFIG_CMD_SDRAM
105#define CONFIG_CMD_EEPROM
106#define CONFIG_CMD_NFS
107#define CONFIG_CMD_PCI
108#define CONFIG_CMD_SNTP
109
wdenkc6097192002-11-03 00:24:07 +0000110
wdenk149dded2003-09-10 18:20:28 +0000111#define CONFIG_DRAM_SPEED 100 /* MHz */
wdenkc6097192002-11-03 00:24:07 +0000112
113/*
114 * Miscellaneous configurable options
115 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200116#define CONFIG_SYS_LONGHELP 1 /* undef to save memory */
117#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
118#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
119#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
120#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
121#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
122#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
123#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenkc6097192002-11-03 00:24:07 +0000124
125/*-----------------------------------------------------------------------
126 * PCI stuff
127 *-----------------------------------------------------------------------
128 */
129#define CONFIG_PCI /* include pci support */
130#undef CONFIG_PCI_PNP
131
132#define CONFIG_NET_MULTI /* Multi ethernet cards support */
133
134#define CONFIG_EEPRO100
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200135#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
wdenkc6097192002-11-03 00:24:07 +0000136
137#define PCI_ENET0_IOADDR 0x80000000
138#define PCI_ENET0_MEMADDR 0x80000000
139#define PCI_ENET1_IOADDR 0x81000000
140#define PCI_ENET1_MEMADDR 0x81000000
141
142
143/*-----------------------------------------------------------------------
144 * Start addresses for the final memory configuration
145 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200146 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenkc6097192002-11-03 00:24:07 +0000147 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200148#define CONFIG_SYS_SDRAM_BASE 0x00000000
149#define CONFIG_SYS_MAX_RAM_SIZE 0x10000000
wdenkc6097192002-11-03 00:24:07 +0000150
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200151#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
wdenkc6097192002-11-03 00:24:07 +0000152
153#if defined (USE_DINK32)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200154#define CONFIG_SYS_MONITOR_LEN 0x00030000
155#define CONFIG_SYS_MONITOR_BASE 0x00090000
156#define CONFIG_SYS_RAMBOOT 1
157#define CONFIG_SYS_INIT_RAM_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
Wolfgang Denk553f0982010-10-26 13:32:32 +0200158#define CONFIG_SYS_INIT_RAM_SIZE 0x10000
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200159#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200160#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenkc6097192002-11-03 00:24:07 +0000161#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200162#undef CONFIG_SYS_RAMBOOT
163#define CONFIG_SYS_MONITOR_LEN 0x00030000
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200164#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
wdenkc6097192002-11-03 00:24:07 +0000165
wdenkc6097192002-11-03 00:24:07 +0000166
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200167#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
Wolfgang Denk553f0982010-10-26 13:32:32 +0200168#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200169#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
wdenkc6097192002-11-03 00:24:07 +0000170
171#endif
172
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173#define CONFIG_SYS_FLASH_BASE 0xFFF00000
wdenkc6097192002-11-03 00:24:07 +0000174#if 0
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200175#define CONFIG_SYS_FLASH_SIZE (512 * 1024) /* sandpoint has tiny eeprom */
wdenkc6097192002-11-03 00:24:07 +0000176#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200177#define CONFIG_SYS_FLASH_SIZE (1024 * 1024) /* Unity has onboard 1MByte flash */
wdenkc6097192002-11-03 00:24:07 +0000178#endif
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200179#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200180#define CONFIG_ENV_OFFSET 0x00004000 /* Offset of Environment Sector */
181#define CONFIG_ENV_SIZE 0x00002000 /* Total Size of Environment Sector */
wdenkc6097192002-11-03 00:24:07 +0000182
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200183#define CONFIG_SYS_MALLOC_LEN (512 << 10) /* Reserve 512 kB for malloc() */
wdenkc6097192002-11-03 00:24:07 +0000184
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200185#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
186#define CONFIG_SYS_MEMTEST_END 0x04000000 /* 0 ... 32 MB in DRAM */
wdenkc6097192002-11-03 00:24:07 +0000187
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200188#define CONFIG_SYS_EUMB_ADDR 0xFC000000
wdenkc6097192002-11-03 00:24:07 +0000189
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200190#define CONFIG_SYS_ISA_MEM 0xFD000000
191#define CONFIG_SYS_ISA_IO 0xFE000000
wdenkc6097192002-11-03 00:24:07 +0000192
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200193#define CONFIG_SYS_FLASH_RANGE_BASE 0xFF000000 /* flash memory address range */
194#define CONFIG_SYS_FLASH_RANGE_SIZE 0x01000000
wdenkc6097192002-11-03 00:24:07 +0000195#define FLASH_BASE0_PRELIM 0xFFF00000 /* sandpoint flash */
196#define FLASH_BASE1_PRELIM 0xFF000000 /* PMC onboard flash */
197
198/*
199 * select i2c support configuration
200 *
201 * Supported configurations are {none, software, hardware} drivers.
202 * If the software driver is chosen, there are some additional
203 * configuration items that the driver uses to drive the port pins.
204 */
205#define CONFIG_HARD_I2C 1 /* To enable I2C support */
206#undef CONFIG_SOFT_I2C /* I2C bit-banged */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200207#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
208#define CONFIG_SYS_I2C_SLAVE 0x7F
wdenkc6097192002-11-03 00:24:07 +0000209
210#ifdef CONFIG_SOFT_I2C
211#error "Soft I2C is not configured properly. Please review!"
212#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
213#define I2C_ACTIVE (iop->pdir |= 0x00010000)
214#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
215#define I2C_READ ((iop->pdat & 0x00010000) != 0)
216#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
217 else iop->pdat &= ~0x00010000
218#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
219 else iop->pdat &= ~0x00020000
220#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
221#endif /* CONFIG_SOFT_I2C */
222
223
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200224#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57 /* EEPROM IS24C02 */
225#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
226#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 /* write page size */
227#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* takes up to 10 msec */
wdenkc6097192002-11-03 00:24:07 +0000228
229
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200230#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
231#define CONFIG_SYS_FLASH_BANKS { FLASH_BASE0_PRELIM , FLASH_BASE1_PRELIM }
wdenkc6097192002-11-03 00:24:07 +0000232
233/*-----------------------------------------------------------------------
234 * Definitions for initial stack pointer and data area (in DPRAM)
235 */
236
237
Wolfgang Denk57d6c582010-11-23 23:17:18 +0100238/* #define CONFIG_WINBOND_83C553 1 / *has a winbond bridge */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200239#define CONFIG_SYS_USE_WINBOND_IDE 0 /*use winbond 83c553 internal IDE ctrlr */
240#define CONFIG_SYS_WINBOND_ISA_CFG_ADDR 0x80005800 /*pci-isa bridge config addr */
241#define CONFIG_SYS_WINBOND_IDE_CFG_ADDR 0x80005900 /*ide config addr */
wdenkc6097192002-11-03 00:24:07 +0000242
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200243#define CONFIG_SYS_IDE_MAXBUS 2 /* max. 2 IDE busses */
244#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
wdenkc6097192002-11-03 00:24:07 +0000245
246/*
247 * NS87308 Configuration
248 */
Jean-Christophe PLAGNIOL-VILLARD55d6d2d2008-08-13 01:40:40 +0200249#define CONFIG_NS87308 /* Nat Semi super-io controller on ISA bus */
wdenkc6097192002-11-03 00:24:07 +0000250
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200251#define CONFIG_SYS_NS87308_BADDR_10 1
wdenkc6097192002-11-03 00:24:07 +0000252
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200253#define CONFIG_SYS_NS87308_DEVS ( CONFIG_SYS_NS87308_UART1 | \
254 CONFIG_SYS_NS87308_UART2 | \
255 CONFIG_SYS_NS87308_POWRMAN | \
256 CONFIG_SYS_NS87308_RTC_APC )
wdenkc6097192002-11-03 00:24:07 +0000257
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200258#undef CONFIG_SYS_NS87308_PS2MOD
wdenkc6097192002-11-03 00:24:07 +0000259
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200260#define CONFIG_SYS_NS87308_CS0_BASE 0x0076
261#define CONFIG_SYS_NS87308_CS0_CONF 0x30
262#define CONFIG_SYS_NS87308_CS1_BASE 0x0075
263#define CONFIG_SYS_NS87308_CS1_CONF 0x30
264#define CONFIG_SYS_NS87308_CS2_BASE 0x0074
265#define CONFIG_SYS_NS87308_CS2_CONF 0x30
wdenkc6097192002-11-03 00:24:07 +0000266
267/*
268 * NS16550 Configuration
269 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200270#define CONFIG_SYS_NS16550
271#define CONFIG_SYS_NS16550_SERIAL
wdenkc6097192002-11-03 00:24:07 +0000272
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200273#define CONFIG_SYS_NS16550_REG_SIZE 1
wdenkc6097192002-11-03 00:24:07 +0000274
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200275#define CONFIG_SYS_NS16550_CLK 1843200
wdenkc6097192002-11-03 00:24:07 +0000276
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200277#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_ISA_IO + CONFIG_SYS_NS87308_UART1_BASE)
278#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_ISA_IO + CONFIG_SYS_NS87308_UART2_BASE)
wdenkc6097192002-11-03 00:24:07 +0000279
280/*
281 * Low Level Configuration Settings
282 * (address mappings, register initial values, etc.)
283 * You should know what you are doing if you make changes here.
284 */
285
286#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
wdenk7cb22f92003-12-27 19:24:54 +0000287#define CONFIG_PLL_PCI_TO_MEM_MULTIPLIER 1
wdenkc6097192002-11-03 00:24:07 +0000288
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200289#define CONFIG_SYS_ROMNAL 7 /*rom/flash next access time */
290#define CONFIG_SYS_ROMFAL 11 /*rom/flash access time */
wdenkc6097192002-11-03 00:24:07 +0000291
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200292#define CONFIG_SYS_REFINT 430 /* no of clock cycles between CBR refresh cycles */
wdenkc6097192002-11-03 00:24:07 +0000293
294/* the following are for SDRAM only*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200295#define CONFIG_SYS_BSTOPRE 121 /* Burst To Precharge, sets open page interval */
296#define CONFIG_SYS_REFREC 8 /* Refresh to activate interval */
297#define CONFIG_SYS_RDLAT 4 /* data latency from read command */
298#define CONFIG_SYS_PRETOACT 3 /* Precharge to activate interval */
299#define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval */
300#define CONFIG_SYS_ACTORW 3 /* Activate to R/W */
301#define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latency */
302#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */
303#define CONFIG_SYS_SDMODE_BURSTLEN 2 /* SDMODE Burst length 2=4, 3=8 */
wdenkc6097192002-11-03 00:24:07 +0000304
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200305#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
wdenkc6097192002-11-03 00:24:07 +0000306
307/* memory bank settings*/
308/*
309 * only bits 20-29 are actually used from these vales to set the
310 * start/end address the upper two bits will be 0, and the lower 20
311 * bits will be set to 0x00000 for a start address, or 0xfffff for an
312 * end address
313 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200314#define CONFIG_SYS_BANK0_START 0x00000000
315#define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1)
316#define CONFIG_SYS_BANK0_ENABLE 1
317#define CONFIG_SYS_BANK1_START 0x3ff00000
318#define CONFIG_SYS_BANK1_END 0x3fffffff
319#define CONFIG_SYS_BANK1_ENABLE 0
320#define CONFIG_SYS_BANK2_START 0x3ff00000
321#define CONFIG_SYS_BANK2_END 0x3fffffff
322#define CONFIG_SYS_BANK2_ENABLE 0
323#define CONFIG_SYS_BANK3_START 0x3ff00000
324#define CONFIG_SYS_BANK3_END 0x3fffffff
325#define CONFIG_SYS_BANK3_ENABLE 0
326#define CONFIG_SYS_BANK4_START 0x00000000
327#define CONFIG_SYS_BANK4_END 0x00000000
328#define CONFIG_SYS_BANK4_ENABLE 0
329#define CONFIG_SYS_BANK5_START 0x00000000
330#define CONFIG_SYS_BANK5_END 0x00000000
331#define CONFIG_SYS_BANK5_ENABLE 0
332#define CONFIG_SYS_BANK6_START 0x00000000
333#define CONFIG_SYS_BANK6_END 0x00000000
334#define CONFIG_SYS_BANK6_ENABLE 0
335#define CONFIG_SYS_BANK7_START 0x00000000
336#define CONFIG_SYS_BANK7_END 0x00000000
337#define CONFIG_SYS_BANK7_ENABLE 0
wdenkc6097192002-11-03 00:24:07 +0000338/*
339 * Memory bank enable bitmask, specifying which of the banks defined above
340 are actually present. MSB is for bank #7, LSB is for bank #0.
341 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200342#define CONFIG_SYS_BANK_ENABLE 0x01
wdenkc6097192002-11-03 00:24:07 +0000343
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200344#define CONFIG_SYS_ODCR 0xff /* configures line driver impedances, */
wdenkc6097192002-11-03 00:24:07 +0000345 /* see 8240 book for bit definitions */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200346#define CONFIG_SYS_PGMAX 0x32 /* how long the 8240 retains the */
wdenkc6097192002-11-03 00:24:07 +0000347 /* currently accessed page in memory */
348 /* see 8240 book for details */
349
350/* SDRAM 0 - 256MB */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200351#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
352#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
wdenkc6097192002-11-03 00:24:07 +0000353
354/* stack in DCACHE @ 1GB (no backing mem) */
355#if defined(USE_DINK32)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200356#define CONFIG_SYS_IBAT1L (0x40000000 | BATL_PP_00 )
357#define CONFIG_SYS_IBAT1U (0x40000000 | BATU_BL_128K )
wdenkc6097192002-11-03 00:24:07 +0000358#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200359#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
360#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
wdenkc6097192002-11-03 00:24:07 +0000361#endif
362
363/* PCI memory */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200364#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
365#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
wdenkc6097192002-11-03 00:24:07 +0000366
367/* Flash, config addrs, etc */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200368#define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
369#define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
wdenkc6097192002-11-03 00:24:07 +0000370
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200371#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
372#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
373#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
374#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
375#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
376#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
377#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
378#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
wdenkc6097192002-11-03 00:24:07 +0000379
380/*
381 * For booting Linux, the board info and command line data
382 * have to be in the first 8 MB of memory, since this is
383 * the maximum mapped by the Linux kernel during initialization.
384 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200385#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenkc6097192002-11-03 00:24:07 +0000386/*-----------------------------------------------------------------------
387 * FLASH organization
388 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200389#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
390#define CONFIG_SYS_MAX_FLASH_SECT 20 /* max number of sectors on one chip */
wdenkc6097192002-11-03 00:24:07 +0000391
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200392#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
393#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
wdenkc6097192002-11-03 00:24:07 +0000394
395/*-----------------------------------------------------------------------
396 * Cache Configuration
397 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200398#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8240 CPU */
Jon Loeligerfe7f7822007-07-08 15:02:44 -0500399#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200400# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
wdenkc6097192002-11-03 00:24:07 +0000401#endif
402
wdenkc6097192002-11-03 00:24:07 +0000403/* values according to the manual */
404
405#define CONFIG_DRAM_50MHZ 1
406#define CONFIG_SDRAM_50MHZ
407
408#undef NR_8259_INTS
409#define NR_8259_INTS 1
410
411
412#define CONFIG_DISK_SPINUP_TIME 1000000
413
414
415#endif /* __CONFIG_H */