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Zachary P. Landau3a108ed2006-01-26 17:37:59 -05001/*
2 * mcf5271.h -- Definitions for Motorola Coldfire 5271
3 *
4 * (C) Copyright 2006, Lab X Technologies <zachary.landau@labxtechnologies.com>
5 * Based on mcf5272sim.h of uCLinux distribution:
6 * (C) Copyright 1999, Greg Ungerer (gerg@snapgear.com)
7 * (C) Copyright 2000, Lineo Inc. (www.lineo.com)
8 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02009 * SPDX-License-Identifier: GPL-2.0+
Zachary P. Landau3a108ed2006-01-26 17:37:59 -050010 */
11
Zachary P. Landau3a108ed2006-01-26 17:37:59 -050012#ifndef _MCF5271_H_
13#define _MCF5271_H_
14
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020015#define mbar_readLong(x) *((volatile unsigned long *) (CONFIG_SYS_MBAR + x))
16#define mbar_readShort(x) *((volatile unsigned short *) (CONFIG_SYS_MBAR + x))
17#define mbar_readByte(x) *((volatile unsigned char *) (CONFIG_SYS_MBAR + x))
18#define mbar_writeLong(x,y) *((volatile unsigned long *) (CONFIG_SYS_MBAR + x)) = y
19#define mbar_writeShort(x,y) *((volatile unsigned short *) (CONFIG_SYS_MBAR + x)) = y
20#define mbar_writeByte(x,y) *((volatile unsigned char *) (CONFIG_SYS_MBAR + x)) = y
Zachary P. Landau3a108ed2006-01-26 17:37:59 -050021
22#define MCF_FMPLL_SYNCR 0x120000
23#define MCF_FMPLL_SYNSR 0x120004
Richard Retanubune0db3442009-01-29 14:36:06 -050024
Zachary P. Landau3a108ed2006-01-26 17:37:59 -050025#define MCF_FMPLL_SYNCR_MFD(x) ((x&0x7)<<24)
Richard Retanubune0db3442009-01-29 14:36:06 -050026#define MCF_SYNCR_MFD_4X 0x00000000
27#define MCF_SYNCR_MFD_6X 0x01000000
28#define MCF_SYNCR_MFD_8X 0x02000000
29#define MCF_SYNCR_MFD_10X 0x03000000
30#define MCF_SYNCR_MFD_12X 0x04000000
31#define MCF_SYNCR_MFD_14X 0x05000000
32#define MCF_SYNCR_MFD_16X 0x06000000
33#define MCF_SYNCR_MFD_18X 0x07000000
34
Zachary P. Landau3a108ed2006-01-26 17:37:59 -050035#define MCF_FMPLL_SYNCR_RFD(x) ((x&0x7)<<19)
Richard Retanubune0db3442009-01-29 14:36:06 -050036#define MCF_SYNCR_RFD_DIV1 0x00000000
37#define MCF_SYNCR_RFD_DIV2 0x00080000
38#define MCF_SYNCR_RFD_DIV4 0x00100000
39#define MCF_SYNCR_RFD_DIV8 0x00180000
40#define MCF_SYNCR_RFD_DIV16 0x00200000
41#define MCF_SYNCR_RFD_DIV32 0x00280000
42#define MCF_SYNCR_RFD_DIV64 0x00300000
43#define MCF_SYNCR_RFD_DIV128 0x00380000
44
Zachary P. Landau3a108ed2006-01-26 17:37:59 -050045#define MCF_FMPLL_SYNSR_LOCK 0x8
46
47#define MCF_WTM_WCR 0x140000
48#define MCF_WTM_WCNTR 0x140004
49#define MCF_WTM_WSR 0x140006
50#define MCF_WTM_WCR_EN 0x0001
51
52#define MCF_RCM_RCR 0x110000
53#define MCF_RCM_RCR_FRCRSTOUT 0x40
54#define MCF_RCM_RCR_SOFTRST 0x80
55
Richard Retanubune0db3442009-01-29 14:36:06 -050056#define MCF_GPIO_PODR_ADDR 0x100000
57#define MCF_GPIO_PODR_DATAH 0x100001
58#define MCF_GPIO_PODR_DATAL 0x100002
59#define MCF_GPIO_PODR_BUSCTL 0x100003
60#define MCF_GPIO_PODR_BS 0x100004
61#define MCF_GPIO_PODR_CS 0x100005
62#define MCF_GPIO_PODR_SDRAM 0x100006
63#define MCF_GPIO_PODR_FECI2C 0x100007
64#define MCF_GPIO_PODR_UARTH 0x100008
65#define MCF_GPIO_PODR_UARTL 0x100009
66#define MCF_GPIO_PODR_QSPI 0x10000A
67#define MCF_GPIO_PODR_TIMER 0x10000B
68
69#define MCF_GPIO_PDDR_ADDR 0x100010
70#define MCF_GPIO_PDDR_DATAH 0x100011
71#define MCF_GPIO_PDDR_DATAL 0x100012
72#define MCF_GPIO_PDDR_BUSCTL 0x100013
73#define MCF_GPIO_PDDR_BS 0x100014
74#define MCF_GPIO_PDDR_CS 0x100015
75#define MCF_GPIO_PDDR_SDRAM 0x100016
76#define MCF_GPIO_PDDR_FECI2C 0x100017
77#define MCF_GPIO_PDDR_UARTH 0x100018
78#define MCF_GPIO_PDDR_UARTL 0x100019
79#define MCF_GPIO_PDDR_QSPI 0x10001A
80#define MCF_GPIO_PDDR_TIMER 0x10001B
81
Richard Retanubun6989e4f2009-02-05 09:33:50 -050082#define MCF_GPIO_PPDSDR_ADDR 0x100020
83#define MCF_GPIO_PPDSDR_DATAH 0x100021
84#define MCF_GPIO_PPDSDR_DATAL 0x100022
85#define MCF_GPIO_PPDSDR_BUSCTL 0x100023
86#define MCF_GPIO_PPDSDR_BS 0x100024
87#define MCF_GPIO_PPDSDR_CS 0x100025
88#define MCF_GPIO_PPDSDR_SDRAM 0x100026
89#define MCF_GPIO_PPDSDR_FECI2C 0x100027
90#define MCF_GPIO_PPDSDR_UARTH 0x100028
91#define MCF_GPIO_PPDSDR_UARTL 0x100029
92#define MCF_GPIO_PPDSDR_QSPI 0x10002A
93#define MCF_GPIO_PPDSDR_TIMER 0x10002B
94
95#define MCF_GPIO_PCLRR_ADDR 0x100030
96#define MCF_GPIO_PCLRR_DATAH 0x100031
97#define MCF_GPIO_PCLRR_DATAL 0x100032
98#define MCF_GPIO_PCLRR_BUSCTL 0x100033
99#define MCF_GPIO_PCLRR_BS 0x100034
100#define MCF_GPIO_PCLRR_CS 0x100035
101#define MCF_GPIO_PCLRR_SDRAM 0x100036
102#define MCF_GPIO_PCLRR_FECI2C 0x100037
103#define MCF_GPIO_PCLRR_UARTH 0x100038
104#define MCF_GPIO_PCLRR_UARTL 0x100039
105#define MCF_GPIO_PCLRR_QSPI 0x10003A
106#define MCF_GPIO_PCLRR_TIMER 0x10003B
107
Marian Balakowiczb4853b72006-05-09 11:43:59 +0200108#define MCF_GPIO_PAR_AD 0x100040
Richard Retanubune0db3442009-01-29 14:36:06 -0500109#define MCF_GPIO_PAR_BUSCTL 0x100042
110#define MCF_GPIO_PAR_BS 0x100044
Zachary P. Landau3a108ed2006-01-26 17:37:59 -0500111#define MCF_GPIO_PAR_CS 0x100045
112#define MCF_GPIO_PAR_SDRAM 0x100046
113#define MCF_GPIO_PAR_FECI2C 0x100047
114#define MCF_GPIO_PAR_UART 0x100048
Richard Retanubune0db3442009-01-29 14:36:06 -0500115#define MCF_GPIO_PAR_QSPI 0x10004A
116#define MCF_GPIO_PAR_TIMER 0x10004C
Zachary P. Landau3a108ed2006-01-26 17:37:59 -0500117
Richard Retanubun6989e4f2009-02-05 09:33:50 -0500118#define MCF_DSCR_EIM 0x100050
119#define MCF_DCSR_FEC12C 0x100052
120#define MCF_DCSR_UART 0x100053
121#define MCF_DCSR_QSPI 0x100054
122#define MCF_DCSR_TIMER 0x100055
123
Bartlomiej Sieka363d1d82007-01-23 13:25:22 +0100124#define MCF_CCM_CIR 0x11000A
125#define MCF_CCM_CIR_PRN_MASK 0x3F
126#define MCF_CCM_CIR_PIN_LEN 6
Richard Retanubune0db3442009-01-29 14:36:06 -0500127#define MCF_CCM_CIR_PIN_MCF5270 0x002e
128#define MCF_CCM_CIR_PIN_MCF5271 0x0032
Bartlomiej Sieka363d1d82007-01-23 13:25:22 +0100129
Marian Balakowiczb4853b72006-05-09 11:43:59 +0200130#define MCF_GPIO_AD_ADDR23 0x80
131#define MCF_GPIO_AD_ADDR22 0x40
132#define MCF_GPIO_AD_ADDR21 0x20
133#define MCF_GPIO_AD_DATAL 0x01
134#define MCF_GPIO_AD_MASK 0xe1
Zachary P. Landau3a108ed2006-01-26 17:37:59 -0500135
Marian Balakowiczb4853b72006-05-09 11:43:59 +0200136#define MCF_GPIO_PAR_CS_PAR_CS2 0x04
137
138#define MCF_GPIO_SDRAM_CSSDCS_00 0x00 /* CS[3:2] pins: CS3, CS2 */
139#define MCF_GPIO_SDRAM_CSSDCS_01 0x40 /* CS[3:2] pins: CS3, SD_CS0 */
140#define MCF_GPIO_SDRAM_CSSDCS_10 0x80 /* CS[3:2] pins: SD_CS1, SC2 */
141#define MCF_GPIO_SDRAM_CSSDCS_11 0xc0 /* CS[3:2] pins: SD_CS1, SD_CS0 */
142#define MCF_GPIO_SDRAM_SDWE 0x20 /* WE pin */
143#define MCF_GPIO_SDRAM_SCAS 0x10 /* CAS pin */
144#define MCF_GPIO_SDRAM_SRAS 0x08 /* RAS pin */
145#define MCF_GPIO_SDRAM_SCKE 0x04 /* CKE pin */
146#define MCF_GPIO_SDRAM_SDCS_00 0x00 /* SD_CS[0:1] pins: GPIO, GPIO */
147#define MCF_GPIO_SDRAM_SDCS_01 0x01 /* SD_CS[0:1] pins: GPIO, SD_CS0 */
148#define MCF_GPIO_SDRAM_SDCS_10 0x02 /* SD_CS[0:1] pins: SD_CS1, GPIO */
149#define MCF_GPIO_SDRAM_SDCS_11 0x03 /* SD_CS[0:1] pins: SD_CS1, SD_CS0 */
150
151#define MCF_GPIO_PAR_UART_U0RTS 0x0001
152#define MCF_GPIO_PAR_UART_U0CTS 0x0002
153#define MCF_GPIO_PAR_UART_U0TXD 0x0004
154#define MCF_GPIO_PAR_UART_U0RXD 0x0008
155#define MCF_GPIO_PAR_UART_U1RXD_UART1 0x0C00
156#define MCF_GPIO_PAR_UART_U1TXD_UART1 0x0300
Zachary P. Landau3a108ed2006-01-26 17:37:59 -0500157
Richard Retanubun59d06122011-03-24 08:58:11 +0000158/* Bit definitions and macros for PAR_QSPI */
159#define MCF_GPIO_PAR_QSPI_PCS1_UNMASK 0x3F
160#define MCF_GPIO_PAR_QSPI_PCS1_PCS1 0xC0
161#define MCF_GPIO_PAR_QSPI_PCS1_SDRAM_SCKE 0x80
162#define MCF_GPIO_PAR_QSPI_PCS1_GPIO 0x00
163#define MCF_GPIO_PAR_QSPI_PCS0_UNMASK 0xDF
164#define MCF_GPIO_PAR_QSPI_PCS0_PCS0 0x20
165#define MCF_GPIO_PAR_QSPI_PCS0_GPIO 0x00
166#define MCF_GPIO_PAR_QSPI_SIN_UNMASK 0xE7
167#define MCF_GPIO_PAR_QSPI_SIN_SIN 0x18
168#define MCF_GPIO_PAR_QSPI_SIN_I2C_SDA 0x10
169#define MCF_GPIO_PAR_QSPI_SIN_GPIO 0x00
170#define MCF_GPIO_PAR_QSPI_SOUT_UNMASK 0xFB
171#define MCF_GPIO_PAR_QSPI_SOUT_SOUT 0x04
172#define MCF_GPIO_PAR_QSPI_SOUT_GPIO 0x00
173#define MCF_GPIO_PAR_QSPI_SCK_UNMASK 0xFC
174#define MCF_GPIO_PAR_QSPI_SCK_SCK 0x03
175#define MCF_GPIO_PAR_QSPI_SCK_I2C_SCL 0x02
176#define MCF_GPIO_PAR_QSPI_SCK_GPIO 0x00
177
178/* Bit definitions and macros for PAR_TIMER for QSPI */
179#define MCF_GPIO_PAR_TIMER_T3IN_UNMASK 0x3FFF
180#define MCF_GPIO_PAR_TIMER_T3IN_QSPI_PCS2 0x4000
181#define MCF_GPIO_PAR_TIMER_T3OUT_UNMASK 0xFF3F
182#define MCF_GPIO_PAR_TIMER_T3OUT_QSPI_PCS3 0x0040
183
TsiChungLiew56115662007-08-15 19:38:15 -0500184#define MCF_GPIO_PAR_SDRAM_PAR_CSSDCS(x) (((x)&0x03)<<6)
Zachary P. Landau3a108ed2006-01-26 17:37:59 -0500185
186#define MCF_SDRAMC_DCR 0x000040
187#define MCF_SDRAMC_DACR0 0x000048
188#define MCF_SDRAMC_DMR0 0x00004C
189
190#define MCF_SDRAMC_DCR_RC(x) (((x)&0x01FF)<<0)
191#define MCF_SDRAMC_DCR_RTIM(x) (((x)&0x0003)<<9)
Marian Balakowiczb4853b72006-05-09 11:43:59 +0200192#define MCF_SDRAMC_DCR_IS 0x0800
193#define MCF_SDRAMC_DCR_COC 0x1000
194#define MCF_SDRAMC_DCR_NAM 0x2000
Zachary P. Landau3a108ed2006-01-26 17:37:59 -0500195
Marian Balakowiczb4853b72006-05-09 11:43:59 +0200196#define MCF_SDRAMC_DACRn_IP 0x00000008
Zachary P. Landau3a108ed2006-01-26 17:37:59 -0500197#define MCF_SDRAMC_DACRn_PS(x) (((x)&0x00000003)<<4)
Marian Balakowiczb4853b72006-05-09 11:43:59 +0200198#define MCF_SDRAMC_DACRn_MRS 0x00000040
Zachary P. Landau3a108ed2006-01-26 17:37:59 -0500199#define MCF_SDRAMC_DACRn_CBM(x) (((x)&0x00000007)<<8)
200#define MCF_SDRAMC_DACRn_CASL(x) (((x)&0x00000003)<<12)
Marian Balakowiczb4853b72006-05-09 11:43:59 +0200201#define MCF_SDRAMC_DACRn_RE 0x00008000
Zachary P. Landau3a108ed2006-01-26 17:37:59 -0500202#define MCF_SDRAMC_DACRn_BA(x) (((x)&0x00003FFF)<<18)
203
Marian Balakowiczb4853b72006-05-09 11:43:59 +0200204#define MCF_SDRAMC_DMRn_BAM_8M 0x007C0000
205#define MCF_SDRAMC_DMRn_BAM_16M 0x00FC0000
206#define MCF_SDRAMC_DMRn_V 0x00000001
Zachary P. Landau3a108ed2006-01-26 17:37:59 -0500207
Marian Balakowiczb4853b72006-05-09 11:43:59 +0200208#define MCFSIM_ICR1 0x000C41
Zachary P. Landau3a108ed2006-01-26 17:37:59 -0500209
TsiChung Liew012522f2008-10-21 10:03:07 +0000210/* Interrupt Controller (INTC) */
TsiChungLiew56115662007-08-15 19:38:15 -0500211#define INT0_LO_RSVD0 (0)
212#define INT0_LO_EPORT1 (1)
213#define INT0_LO_EPORT2 (2)
214#define INT0_LO_EPORT3 (3)
215#define INT0_LO_EPORT4 (4)
216#define INT0_LO_EPORT5 (5)
217#define INT0_LO_EPORT6 (6)
218#define INT0_LO_EPORT7 (7)
219#define INT0_LO_SCM (8)
220#define INT0_LO_DMA0 (9)
221#define INT0_LO_DMA1 (10)
222#define INT0_LO_DMA2 (11)
223#define INT0_LO_DMA3 (12)
224#define INT0_LO_UART0 (13)
225#define INT0_LO_UART1 (14)
226#define INT0_LO_UART2 (15)
227#define INT0_LO_RSVD1 (16)
228#define INT0_LO_I2C (17)
229#define INT0_LO_QSPI (18)
230#define INT0_LO_DTMR0 (19)
231#define INT0_LO_DTMR1 (20)
232#define INT0_LO_DTMR2 (21)
233#define INT0_LO_DTMR3 (22)
234#define INT0_LO_FEC_TXF (23)
235#define INT0_LO_FEC_TXB (24)
236#define INT0_LO_FEC_UN (25)
237#define INT0_LO_FEC_RL (26)
238#define INT0_LO_FEC_RXF (27)
239#define INT0_LO_FEC_RXB (28)
240#define INT0_LO_FEC_MII (29)
241#define INT0_LO_FEC_LC (30)
242#define INT0_LO_FEC_HBERR (31)
243#define INT0_HI_FEC_GRA (32)
244#define INT0_HI_FEC_EBERR (33)
245#define INT0_HI_FEC_BABT (34)
246#define INT0_HI_FEC_BABR (35)
247#define INT0_HI_PIT0 (36)
248#define INT0_HI_PIT1 (37)
249#define INT0_HI_PIT2 (38)
250#define INT0_HI_PIT3 (39)
251#define INT0_HI_RNG (40)
252#define INT0_HI_SKHA (41)
253#define INT0_HI_MDHA (42)
254#define INT0_HI_CAN1_BUF0I (43)
255#define INT0_HI_CAN1_BUF1I (44)
256#define INT0_HI_CAN1_BUF2I (45)
257#define INT0_HI_CAN1_BUF3I (46)
258#define INT0_HI_CAN1_BUF4I (47)
259#define INT0_HI_CAN1_BUF5I (48)
260#define INT0_HI_CAN1_BUF6I (49)
261#define INT0_HI_CAN1_BUF7I (50)
262#define INT0_HI_CAN1_BUF8I (51)
263#define INT0_HI_CAN1_BUF9I (52)
264#define INT0_HI_CAN1_BUF10I (53)
265#define INT0_HI_CAN1_BUF11I (54)
266#define INT0_HI_CAN1_BUF12I (55)
267#define INT0_HI_CAN1_BUF13I (56)
268#define INT0_HI_CAN1_BUF14I (57)
269#define INT0_HI_CAN1_BUF15I (58)
270#define INT0_HI_CAN1_ERRINT (59)
271#define INT0_HI_CAN1_BOFFINT (60)
272/* 60-63 Reserved */
273
TsiChungLiew56115662007-08-15 19:38:15 -0500274#endif /* _MCF5271_H_ */