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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / e7ae4cf27a6d5837cb5e868712cdaa61d3ceb5e0 / . / drivers / pinctrl / rockchip / pinctrl-rk3128.c
blob: 43a6c173a0fa4b0b9fe36a662a069a363d56e4ae [file] [log] [blame]
David Wue7ae4cf2019-01-02 21:00:55 +0800[diff] [blame^]1// SPDX-License-Identifier: GPL-2.0+
2/*
3 * (C) Copyright 2019 Rockchip Electronics Co., Ltd
4 */
5
6#include <common.h>
7#include <dm.h>
8#include <dm/pinctrl.h>
9#include <regmap.h>
10#include <syscon.h>
11
12#include "pinctrl-rockchip.h"
13
14static struct rockchip_mux_recalced_data rk3128_mux_recalced_data[] = {
15 {
16 .num = 2,
17 .pin = 20,
18 .reg = 0xe8,
19 .bit = 0,
20 .mask = 0x7
21 }, {
22 .num = 2,
23 .pin = 21,
24 .reg = 0xe8,
25 .bit = 4,
26 .mask = 0x7
27 }, {
28 .num = 2,
29 .pin = 22,
30 .reg = 0xe8,
31 .bit = 8,
32 .mask = 0x7
33 }, {
34 .num = 2,
35 .pin = 23,
36 .reg = 0xe8,
37 .bit = 12,
38 .mask = 0x7
39 }, {
40 .num = 2,
41 .pin = 24,
42 .reg = 0xd4,
43 .bit = 12,
44 .mask = 0x7
45 },
46};
47
48static struct rockchip_mux_route_data rk3128_mux_route_data[] = {
49 {
50 /* spi-0 */
51 .bank_num = 1,
52 .pin = 10,
53 .func = 1,
54 .route_offset = 0x144,
55 .route_val = BIT(16 + 3) | BIT(16 + 4),
56 }, {
57 /* spi-1 */
58 .bank_num = 1,
59 .pin = 27,
60 .func = 3,
61 .route_offset = 0x144,
62 .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(3),
63 }, {
64 /* spi-2 */
65 .bank_num = 0,
66 .pin = 13,
67 .func = 2,
68 .route_offset = 0x144,
69 .route_val = BIT(16 + 3) | BIT(16 + 4) | BIT(4),
70 }, {
71 /* i2s-0 */
72 .bank_num = 1,
73 .pin = 5,
74 .func = 1,
75 .route_offset = 0x144,
76 .route_val = BIT(16 + 5),
77 }, {
78 /* i2s-1 */
79 .bank_num = 0,
80 .pin = 14,
81 .func = 1,
82 .route_offset = 0x144,
83 .route_val = BIT(16 + 5) | BIT(5),
84 }, {
85 /* emmc-0 */
86 .bank_num = 1,
87 .pin = 22,
88 .func = 2,
89 .route_offset = 0x144,
90 .route_val = BIT(16 + 6),
91 }, {
92 /* emmc-1 */
93 .bank_num = 2,
94 .pin = 4,
95 .func = 2,
96 .route_offset = 0x144,
97 .route_val = BIT(16 + 6) | BIT(6),
98 },
99};
100
101#define RK3128_PULL_OFFSET 0x118
102#define RK3128_PULL_PINS_PER_REG 16
103#define RK3128_PULL_BANK_STRIDE 8
104
105static void rk3128_calc_pull_reg_and_bit(struct rockchip_pin_bank *bank,
106 int pin_num, struct regmap **regmap,
107 int *reg, u8 *bit)
108{
109 struct rockchip_pinctrl_priv *priv = bank->priv;
110
111 *regmap = priv->regmap_base;
112 *reg = RK3128_PULL_OFFSET;
113 *reg += bank->bank_num * RK3128_PULL_BANK_STRIDE;
114 *reg += ((pin_num / RK3128_PULL_PINS_PER_REG) * 4);
115
116 *bit = pin_num % RK3128_PULL_PINS_PER_REG;
117}
118
119static struct rockchip_pin_bank rk3128_pin_banks[] = {
120 PIN_BANK(0, 32, "gpio0"),
121 PIN_BANK(1, 32, "gpio1"),
122 PIN_BANK(2, 32, "gpio2"),
123 PIN_BANK(3, 32, "gpio3"),
124};
125
126static struct rockchip_pin_ctrl rk3128_pin_ctrl = {
127 .pin_banks = rk3128_pin_banks,
128 .nr_banks = ARRAY_SIZE(rk3128_pin_banks),
129 .label = "RK3128-GPIO",
130 .type = RK3128,
131 .grf_mux_offset = 0xa8,
132 .iomux_recalced = rk3128_mux_recalced_data,
133 .niomux_recalced = ARRAY_SIZE(rk3128_mux_recalced_data),
134 .iomux_routes = rk3128_mux_route_data,
135 .niomux_routes = ARRAY_SIZE(rk3128_mux_route_data),
136 .pull_calc_reg = rk3128_calc_pull_reg_and_bit,
137};
138
139static const struct udevice_id rk3128_pinctrl_ids[] = {
140 { .compatible = "rockchip,rk3128-pinctrl",
141 .data = (ulong)&rk3128_pin_ctrl },
142 { }
143};
144
145U_BOOT_DRIVER(pinctrl_rk3128) = {
146 .name = "pinctrl_rk3128",
147 .id = UCLASS_PINCTRL,
148 .of_match = rk3128_pinctrl_ids,
149 .priv_auto_alloc_size = sizeof(struct rockchip_pinctrl_priv),
150 .ops = &rockchip_pinctrl_ops,
151#if !CONFIG_IS_ENABLED(OF_PLATDATA)
152 .bind = dm_scan_fdt_dev,
153#endif
154 .probe = rockchip_pinctrl_probe,
155};