Robert Beckett | d494aec | 2019-11-12 19:15:19 +0000 | [diff] [blame] | 1 | // SPDX-License-Identifier: GPL-2.0+ OR X11 |
| 2 | /* |
| 3 | * Copyright 2019 Collabora Ltd |
| 4 | * Copyright 2019 General Electric Company |
| 5 | */ |
| 6 | |
| 7 | / { |
Robert Beckett | 41613a7 | 2020-01-31 15:07:55 +0200 | [diff] [blame] | 8 | bootcount { |
| 9 | compatible = "u-boot,bootcount-i2c-eeprom"; |
| 10 | i2c-eeprom = <&bootcount>; |
| 11 | }; |
| 12 | |
Robert Beckett | d494aec | 2019-11-12 19:15:19 +0000 | [diff] [blame] | 13 | wdt-reboot { |
| 14 | compatible = "wdt-reboot"; |
| 15 | wdt = <&wdog1>; |
| 16 | }; |
Ian Ray | bd58b1a | 2020-01-31 15:07:58 +0200 | [diff] [blame] | 17 | |
| 18 | panel-lvds0 { |
| 19 | compatible = "simple-panel"; |
| 20 | }; |
Robert Beckett | d494aec | 2019-11-12 19:15:19 +0000 | [diff] [blame] | 21 | }; |
Robert Beckett | b64088c | 2020-01-31 15:07:53 +0200 | [diff] [blame] | 22 | |
| 23 | &eeprom { |
| 24 | partitions { |
| 25 | compatible = "fixed-partitions"; |
Michal Simek | f692b47 | 2020-05-28 11:48:55 +0200 | [diff] [blame] | 26 | #address-cells = <1>; |
| 27 | #size-cells = <1>; |
Robert Beckett | b64088c | 2020-01-31 15:07:53 +0200 | [diff] [blame] | 28 | |
Michal Simek | f692b47 | 2020-05-28 11:48:55 +0200 | [diff] [blame] | 29 | vpd@0 { |
Ian Ray | 559aaa2 | 2020-11-04 17:18:42 +0100 | [diff] [blame] | 30 | reg = <0 800>; |
Robert Beckett | b64088c | 2020-01-31 15:07:53 +0200 | [diff] [blame] | 31 | }; |
| 32 | |
Robert Beckett | 41613a7 | 2020-01-31 15:07:55 +0200 | [diff] [blame] | 33 | bootcount: bootcount { |
Michal Simek | f692b47 | 2020-05-28 11:48:55 +0200 | [diff] [blame] | 34 | reg = <1022 2>; |
Robert Beckett | b64088c | 2020-01-31 15:07:53 +0200 | [diff] [blame] | 35 | }; |
| 36 | }; |
| 37 | }; |
Sebastian Reichel | 4ac026a | 2021-04-23 16:15:08 +0200 | [diff] [blame] | 38 | |
| 39 | /* |
| 40 | * This is not done in imx6q-ba16.dtsi, since that file is shared |
| 41 | * with the kernel and the kernel should not reset the PHY, since |
| 42 | * it lacks support for configuring the reserved registeres to |
| 43 | * avoid a board specific voltage peak issue. |
| 44 | */ |
| 45 | &fec { |
| 46 | phy-reset-gpios = <&gpio1 28 GPIO_ACTIVE_LOW>; |
| 47 | phy-reset-duration = <1>; |
| 48 | phy-reset-post-delay = <0>; |
| 49 | }; |