| Kuo-Jung Su | e82a316 | 2013-05-15 15:29:23 +0800 | [diff] [blame^] | 1 | /* |
| 2 | * Faraday USB 2.0 EHCI Controller |
| 3 | * |
| 4 | * (C) Copyright 2010 Faraday Technology |
| 5 | * Dante Su <dantesu@faraday-tech.com> |
| 6 | * |
| 7 | * This file is released under the terms of GPL v2 and any later version. |
| 8 | * See the file COPYING in the root directory of the source tree for details. |
| 9 | */ |
| 10 | |
| 11 | #ifndef _FUSBH200_H |
| 12 | #define _FUSBH200_H |
| 13 | |
| 14 | struct fusbh200_regs { |
| 15 | struct { |
| 16 | uint32_t data[4]; |
| 17 | } hccr; /* 0x00 - 0x0f: hccr */ |
| 18 | struct { |
| 19 | uint32_t data[9]; |
| 20 | } hcor; /* 0x10 - 0x33: hcor */ |
| 21 | uint32_t easstr;/* 0x34: EOF&Async. Sched. Sleep Timer Register */ |
| 22 | uint32_t rsvd[2]; |
| 23 | uint32_t bmcsr; /* 0x40: Bus Monitor Control Status Register */ |
| 24 | uint32_t bmisr; /* 0x44: Bus Monitor Interrupt Status Register */ |
| 25 | uint32_t bmier; /* 0x48: Bus Monitor Interrupt Enable Register */ |
| 26 | }; |
| 27 | |
| 28 | /* EOF & Async. Schedule Sleep Timer Register */ |
| 29 | #define EASSTR_RUNNING (1 << 6) /* Put transceiver in running/resume mode */ |
| 30 | #define EASSTR_SUSPEND (0 << 6) /* Put transceiver in suspend mode */ |
| 31 | #define EASSTR_EOF2(x) (((x) & 0x3) << 4) /* EOF 2 Timing */ |
| 32 | #define EASSTR_EOF1(x) (((x) & 0x3) << 2) /* EOF 1 Timing */ |
| 33 | #define EASSTR_ASST(x) (((x) & 0x3) << 0) /* Async. Sched. Sleep Timer */ |
| 34 | |
| 35 | /* Bus Monitor Control Status Register */ |
| 36 | #define BMCSR_SPD_HIGH (2 << 9) /* Speed of the attached device */ |
| 37 | #define BMCSR_SPD_LOW (1 << 9) |
| 38 | #define BMCSR_SPD_FULL (0 << 9) |
| 39 | #define BMCSR_SPD_MASK (3 << 9) |
| 40 | #define BMCSR_SPD_SHIFT 9 |
| 41 | #define BMCSR_SPD(x) ((x >> 9) & 0x03) |
| 42 | #define BMCSR_VBUS (1 << 8) /* VBUS Valid */ |
| 43 | #define BMCSR_VBUS_OFF (1 << 4) /* VBUS Off */ |
| 44 | #define BMCSR_VBUS_ON (0 << 4) /* VBUS On */ |
| 45 | #define BMCSR_IRQLH (1 << 3) /* IRQ triggered at level-high */ |
| 46 | #define BMCSR_IRQLL (0 << 3) /* IRQ triggered at level-low */ |
| 47 | #define BMCSR_HALFSPD (1 << 2) /* Half speed mode for FPGA test */ |
| 48 | #define BMCSR_HFT_LONG (1 << 1) /* HDISCON noise filter = 270 us*/ |
| 49 | #define BMCSR_HFT (0 << 1) /* HDISCON noise filter = 135 us*/ |
| 50 | #define BMCSR_VFT_LONG (1 << 1) /* VBUS noise filter = 472 us*/ |
| 51 | #define BMCSR_VFT (0 << 1) /* VBUS noise filter = 135 us*/ |
| 52 | |
| 53 | /* Bus Monitor Interrupt Status Register */ |
| 54 | /* Bus Monitor Interrupt Enable Register */ |
| 55 | #define BMISR_DMAERR (1 << 4) /* DMA error */ |
| 56 | #define BMISR_DMA (1 << 3) /* DMA complete */ |
| 57 | #define BMISR_DEVRM (1 << 2) /* device removed */ |
| 58 | #define BMISR_OVD (1 << 1) /* over-current detected */ |
| 59 | #define BMISR_VBUSERR (1 << 0) /* VBUS error */ |
| 60 | |
| 61 | #endif |