| Andy Fleming | 6743105 | 2007-04-23 02:54:25 -0500 | [diff] [blame] | 1 | /* |
| 2 | * Copyright 2007 Freescale Semiconductor. |
| 3 | * |
| 4 | * See file CREDITS for list of people who contributed to this |
| 5 | * project. |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or |
| 8 | * modify it under the terms of the GNU General Public License as |
| 9 | * published by the Free Software Foundation; either version 2 of |
| 10 | * the License, or (at your option) any later version. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
| 16 | * |
| 17 | * You should have received a copy of the GNU General Public License |
| 18 | * along with this program; if not, write to the Free Software |
| 19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, |
| 20 | * MA 02111-1307 USA |
| 21 | */ |
| 22 | |
| 23 | #ifndef __BCSR_H_ |
| 24 | #define __BCSR_H_ |
| 25 | |
| 26 | #include <common.h> |
| 27 | |
| 28 | /* BCSR Bit definitions |
| 29 | * BCSR 0 * |
| 30 | 0:3 ccb sys pll |
| 31 | 4:6 cfg core pll |
| 32 | 7 cfg boot seq |
| 33 | |
| 34 | * BCSR 1 * |
| 35 | 0:2 cfg rom lock |
| 36 | 3:5 cfg host agent |
| 37 | 6 PCI IO |
| 38 | 7 cfg RIO size |
| 39 | |
| 40 | * BCSR 2 * |
| 41 | 0:4 QE PLL |
| 42 | 5 QE clock |
| 43 | 6 cfg PCI arbiter |
| 44 | |
| 45 | * BCSR 3 * |
| 46 | 0 TSEC1 reduce |
| 47 | 1 TSEC2 reduce |
| 48 | 2:3 TSEC1 protocol |
| 49 | 4:5 TSEC2 protocol |
| 50 | 6 PHY1 slave |
| 51 | 7 PHY2 slave |
| 52 | |
| 53 | * BCSR 4 * |
| 54 | 4 clock enable |
| 55 | 5 boot EPROM |
| 56 | 6 GETH transactive reset |
| 57 | 7 BRD write potect |
| 58 | |
| 59 | * BCSR 5 * |
| 60 | 1:3 Leds 1-3 |
| 61 | 4 UPC1 enable |
| 62 | 5 UPC2 enable |
| 63 | 6 UPC2 pos |
| 64 | 7 RS232 enable |
| 65 | |
| 66 | * BCSR 6 * |
| 67 | 0 CFG ver 0 |
| 68 | 1 CFG ver 1 |
| 69 | 6 Register config led |
| 70 | 7 Power on reset |
| 71 | |
| 72 | * BCSR 7 * |
| 73 | 2 board host mode indication |
| 74 | 5 enable TSEC1 PHY |
| 75 | 6 enable TSEC2 PHY |
| 76 | |
| 77 | * BCSR 8 * |
| 78 | 0 UCC GETH1 enable |
| 79 | 1 UCC GMII enable |
| 80 | 3 UCC TBI enable |
| 81 | 5 UCC MII enable |
| 82 | 7 Real time clock reset |
| 83 | |
| 84 | * BCSR 9 * |
| 85 | 0 UCC2 GETH enable |
| 86 | 1 UCC2 GMII enable |
| 87 | 3 UCC2 TBI enable |
| 88 | 5 UCC2 MII enable |
| 89 | 6 Ready only - indicate flash ready after burning |
| 90 | 7 Flash write protect |
| 91 | */ |
| 92 | |
| 93 | /*BCSR Utils functions*/ |
| 94 | |
| 95 | void enable_8568mds_duart(void); |
| 96 | void enable_8568mds_flash_write(void); |
| 97 | void disable_8568mds_flash_write(void); |
| 98 | |
| 99 | #endif /* __BCSR_H_ */ |