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TsiChungLiew4a442d32007-08-16 19:23:50 -05001/*
2 *
Alison Wangc6d88632012-03-26 21:49:06 +00003 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
TsiChungLiew4a442d32007-08-16 19:23:50 -05004 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
5 *
Wolfgang Denk1a459662013-07-08 09:37:19 +02006 * SPDX-License-Identifier: GPL-2.0+
TsiChungLiew4a442d32007-08-16 19:23:50 -05007 */
8
9/* CPU specific interrupt routine */
10#include <common.h>
11#include <asm/immap.h>
Alison Wangc6d88632012-03-26 21:49:06 +000012#include <asm/io.h>
TsiChungLiew4a442d32007-08-16 19:23:50 -050013
14int interrupt_init(void)
15{
Alison Wangc6d88632012-03-26 21:49:06 +000016 int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
TsiChungLiew4a442d32007-08-16 19:23:50 -050017
18 /* Make sure all interrupts are disabled */
Alison Wangc6d88632012-03-26 21:49:06 +000019 setbits_be32(&intp->imrl0, 0x1);
TsiChungLiew4a442d32007-08-16 19:23:50 -050020
21 enable_interrupts();
22 return 0;
23}
24
25#if defined(CONFIG_MCFTMR)
26void dtimer_intr_setup(void)
27{
Alison Wangc6d88632012-03-26 21:49:06 +000028 int0_t *intp = (int0_t *) (CONFIG_SYS_INTR_BASE);
TsiChungLiew4a442d32007-08-16 19:23:50 -050029
Alison Wangc6d88632012-03-26 21:49:06 +000030 out_8(&intp->icr0[CONFIG_SYS_TMRINTR_NO], CONFIG_SYS_TMRINTR_PRI);
31 clrbits_be32(&intp->imrl0, INTC_IPRL_INT0);
32 clrbits_be32(&intp->imrl0, CONFIG_SYS_TMRINTR_MASK);
TsiChungLiew4a442d32007-08-16 19:23:50 -050033}
34#endif