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gerrit.devboardsforandroid.linaro.org / platform / external / u-boot / e84b8f6ce0e7daf4e9781172c4ffd74d7d525dbb / . / board / csb472 / init.S
blob: 1ebc9ead3ae5b762f99ae3aa6603862cd465733e [file] [log] [blame]
Wolfgang Denk46263f22013-07-28 22:12:45 +0200[diff] [blame]1/*
Wolfgang Denk1b387ef2013-09-17 11:24:06 +0200[diff] [blame]2 * SPDX-License-Identifier: GPL-2.0 IBM-pibs
Wolfgang Denk46263f22013-07-28 22:12:45 +0200[diff] [blame]3 */
wdenkaa245092004-06-09 12:47:02 +0000[diff] [blame]4#include <config.h>
Stefan Roeseb36df562010-09-09 19:18:00 +0200[diff] [blame]5#include <asm/ppc4xx.h>
wdenkaa245092004-06-09 12:47:02 +0000[diff] [blame]6
7#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
8
9#include <ppc_asm.tmpl>
10#include <ppc_defs.h>
11
12#include <asm/cache.h>
13#include <asm/mmu.h>
14
15#define LI32(reg,val) \
16 addis reg,0,val@h;\
17 ori reg,reg,val@l
18
19#define WDCR_EBC(reg,val) \
20 addi r4,0,reg;\
Stefan Roesed1c3b272009-09-09 16:25:29 +0200[diff] [blame]21 mtdcr EBC0_CFGADDR,r4;\
wdenkaa245092004-06-09 12:47:02 +0000[diff] [blame]22 addis r4,0,val@h;\
23 ori r4,r4,val@l;\
Stefan Roesed1c3b272009-09-09 16:25:29 +0200[diff] [blame]24 mtdcr EBC0_CFGDATA,r4
wdenkaa245092004-06-09 12:47:02 +0000[diff] [blame]25
26#define WDCR_SDRAM(reg,val) \
27 addi r4,0,reg;\
Stefan Roesed1c3b272009-09-09 16:25:29 +0200[diff] [blame]28 mtdcr SDRAM0_CFGADDR,r4;\
wdenkaa245092004-06-09 12:47:02 +0000[diff] [blame]29 addis r4,0,val@h;\
30 ori r4,r4,val@l;\
Stefan Roesed1c3b272009-09-09 16:25:29 +0200[diff] [blame]31 mtdcr SDRAM0_CFGDATA,r4
wdenkaa245092004-06-09 12:47:02 +0000[diff] [blame]32
33/******************************************************************************
34 * Function: ext_bus_cntlr_init
35 *
36 * Description: Configures EBC Controller and a few basic chip selects.
37 *
38 * CS0 is setup to get the Boot Flash out of the addresss range
39 * so that we may setup a stack. CS7 is setup so that we can
40 * access and reset the hardware watchdog.
41 *
42 * IMPORTANT: For pass1 this code must run from
43 * cache since you can not reliably change a peripheral banks
44 * timing register (pbxap) while running code from that bank.
45 * For ex., since we are running from ROM on bank 0, we can NOT
46 * execute the code that modifies bank 0 timings from ROM, so
47 * we run it from cache.
48 *
49 * Notes: Does NOT use the stack.
50 *****************************************************************************/
51 .section ".text"
52 .align 2
53 .globl ext_bus_cntlr_init
54 .type ext_bus_cntlr_init, @function
55ext_bus_cntlr_init:
56 mflr r0
57 /********************************************************************
58 * Prefetch entire ext_bus_cntrl_init function into the icache.
59 * This is necessary because we are going to change the same CS we
60 * are executing from. Otherwise a CPU lockup may occur.
61 *******************************************************************/
62 bl ..getAddr
63..getAddr:
64 mflr r3 /* get address of ..getAddr */
65
66 /* Calculate number of cache lines for this function */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]67 addi r4, 0, (((.Lfe0 - ..getAddr) / CONFIG_SYS_CACHELINE_SIZE) + 2)
wdenkaa245092004-06-09 12:47:02 +0000[diff] [blame]68 mtctr r4
69..ebcloop:
70 icbt r0, r3 /* prefetch cache line for addr in r3*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200[diff] [blame]71 addi r3, r3, CONFIG_SYS_CACHELINE_SIZE /* move to next cache line */
wdenkaa245092004-06-09 12:47:02 +0000[diff] [blame]72 bdnz ..ebcloop /* continue for $CTR cache lines */
73
74 /********************************************************************
75 * Delay to ensure all accesses to ROM are complete before changing
76 * bank 0 timings. 200usec should be enough.
77 * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles.
78 *******************************************************************/
79 addis r3, 0, 0x0
80 ori r3, r3, 0xA000 /* wait 200us from reset */
81 mtctr r3
82..spinlp:
83 bdnz ..spinlp /* spin loop */
84
85 /********************************************************************
86 * SETUP CPC0_CR0
87 *******************************************************************/
88 LI32(r4, 0x00c01030)
Stefan Roesed1c3b272009-09-09 16:25:29 +0200[diff] [blame]89 mtdcr CPC0_CR0, r4
wdenkaa245092004-06-09 12:47:02 +0000[diff] [blame]90
91 /********************************************************************
92 * Setup CPC0_CR1: Change PCIINT signal to PerWE
93 *******************************************************************/
Stefan Roesed1c3b272009-09-09 16:25:29 +0200[diff] [blame]94 mfdcr r4, CPC0_CR1
wdenkaa245092004-06-09 12:47:02 +0000[diff] [blame]95 ori r4, r4, 0x4000
Stefan Roesed1c3b272009-09-09 16:25:29 +0200[diff] [blame]96 mtdcr CPC0_CR1, r4
wdenkaa245092004-06-09 12:47:02 +0000[diff] [blame]97
98 /********************************************************************
99 * Setup External Bus Controller (EBC).
100 *******************************************************************/
Stefan Roesed1c3b272009-09-09 16:25:29 +0200[diff] [blame]101 WDCR_EBC(EBC0_CFG, 0xd84c0000)
wdenkaa245092004-06-09 12:47:02 +0000[diff] [blame]102 /********************************************************************
103 * Memory Bank 0 (Intel 28F640J3 Flash) initialization
104 *******************************************************************/
Stefan Roesed1c3b272009-09-09 16:25:29 +0200[diff] [blame]105 /*WDCR_EBC(PB1AP, 0x03055200)*/
106 /*WDCR_EBC(PB1AP, 0x04055200)*/
107 WDCR_EBC(PB1AP, 0x08055200)
108 WDCR_EBC(PB0CR, 0xff87a000)
wdenkaa245092004-06-09 12:47:02 +0000[diff] [blame]109 /********************************************************************
110 * Memory Bank 3 (Xilinx XC95144 CPLD) initialization
111 *******************************************************************/
Stefan Roesed1c3b272009-09-09 16:25:29 +0200[diff] [blame]112 /*WDCR_EBC(PB3AP, 0x07869200)*/
113 WDCR_EBC(PB3AP, 0x04055200)
114 WDCR_EBC(PB3CR, 0xf081c000)
wdenkaa245092004-06-09 12:47:02 +0000[diff] [blame]115 /********************************************************************
116 * Memory Bank 1,2,4-7 (Unused) initialization
117 *******************************************************************/
Stefan Roesed1c3b272009-09-09 16:25:29 +0200[diff] [blame]118 WDCR_EBC(PB1AP, 0)
119 WDCR_EBC(PB1CR, 0)
120 WDCR_EBC(PB2AP, 0)
121 WDCR_EBC(PB2CR, 0)
122 WDCR_EBC(PB4AP, 0)
123 WDCR_EBC(PB4CR, 0)
124 WDCR_EBC(PB5AP, 0)
125 WDCR_EBC(PB5CR, 0)
126 WDCR_EBC(PB6AP, 0)
127 WDCR_EBC(PB6CR, 0)
128 WDCR_EBC(PB7AP, 0)
129 WDCR_EBC(PB7CR, 0)
wdenkaa245092004-06-09 12:47:02 +0000[diff] [blame]130
131 /* We are all done */
132 mtlr r0 /* Restore link register */
133 blr /* Return to calling function */
134.Lfe0: .size ext_bus_cntlr_init,.Lfe0-ext_bus_cntlr_init
135/* end ext_bus_cntlr_init() */
136
137/******************************************************************************
138 * Function: sdram_init
139 *
140 * Description: Configures SDRAM memory banks.
141 *
142 * Notes: Does NOT use the stack.
143 *****************************************************************************/
144 .section ".text"
145 .align 2
146 .globl sdram_init
147 .type sdram_init, @function
148sdram_init:
149
150 /*
151 * Disable memory controller to allow
152 * values to be changed.
153 */
Stefan Roese95b602b2009-09-24 13:59:57 +0200[diff] [blame]154 WDCR_SDRAM(SDRAM0_CFG, 0x00000000)
wdenkaa245092004-06-09 12:47:02 +0000[diff] [blame]155
156 /*
157 * Configure Memory Banks
158 */
Stefan Roese95b602b2009-09-24 13:59:57 +0200[diff] [blame]159 WDCR_SDRAM(SDRAM0_B0CR, 0x00062001)
160 WDCR_SDRAM(SDRAM0_B1CR, 0x00000000)
161 WDCR_SDRAM(SDRAM0_B2CR, 0x00000000)
162 WDCR_SDRAM(SDRAM0_B3CR, 0x00000000)
wdenkaa245092004-06-09 12:47:02 +0000[diff] [blame]163
164 /*
165 * Set up SDTR1 (SDRAM Timing Register)
166 */
Stefan Roese95b602b2009-09-24 13:59:57 +0200[diff] [blame]167 WDCR_SDRAM(SDRAM0_TR, 0x00854009)
wdenkaa245092004-06-09 12:47:02 +0000[diff] [blame]168
169 /*
170 * Set RTR (Refresh Timing Register)
171 */
Stefan Roese95b602b2009-09-24 13:59:57 +0200[diff] [blame]172 WDCR_SDRAM(SDRAM0_RTR, 0x10000000)
173 /* WDCR_SDRAM(SDRAM0_RTR, 0x05f00000) */
wdenkaa245092004-06-09 12:47:02 +0000[diff] [blame]174
175 /********************************************************************
176 * Delay to ensure 200usec have elapsed since reset. Assume worst
177 * case that the core is running 200Mhz:
178 * 200,000,000 (cycles/sec) X .000200 (sec) = 0x9C40 cycles
179 *******************************************************************/
180 addis r3, 0, 0x0000
181 ori r3, r3, 0xA000 /* Wait >200us from reset */
182 mtctr r3
183..spinlp2:
184 bdnz ..spinlp2 /* spin loop */
185
186 /********************************************************************
187 * Set memory controller options reg, MCOPT1.
188 *******************************************************************/
Stefan Roese95b602b2009-09-24 13:59:57 +0200[diff] [blame]189 WDCR_SDRAM(SDRAM0_CFG,0x80800000)
wdenkaa245092004-06-09 12:47:02 +0000[diff] [blame]190
191..sdri_done:
192 blr /* Return to calling function */
193.Lfe1: .size sdram_init,.Lfe1-sdram_init
194/* end sdram_init() */