blob: 6492ace0de6b3de57422f70ea72667f121aed7b8 [file] [log] [blame]
FUKAUMI Naoki85a8ef12022-10-04 01:30:30 +00001// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
2/*
3 * Copyright (c) 2021 Rockchip Electronics Co., Ltd.
4 */
5
6#include <dt-bindings/clock/rk3568-cru.h>
7#include <dt-bindings/interrupt-controller/arm-gic.h>
8#include <dt-bindings/interrupt-controller/irq.h>
9#include <dt-bindings/phy/phy.h>
10#include <dt-bindings/pinctrl/rockchip.h>
11#include <dt-bindings/power/rk3568-power.h>
12#include <dt-bindings/soc/rockchip,boot-mode.h>
13#include <dt-bindings/thermal/thermal.h>
14
15/ {
16 interrupt-parent = <&gic>;
17 #address-cells = <2>;
18 #size-cells = <2>;
19
20 aliases {
21 gpio0 = &gpio0;
22 gpio1 = &gpio1;
23 gpio2 = &gpio2;
24 gpio3 = &gpio3;
25 gpio4 = &gpio4;
26 i2c0 = &i2c0;
27 i2c1 = &i2c1;
28 i2c2 = &i2c2;
29 i2c3 = &i2c3;
30 i2c4 = &i2c4;
31 i2c5 = &i2c5;
32 serial0 = &uart0;
33 serial1 = &uart1;
34 serial2 = &uart2;
35 serial3 = &uart3;
36 serial4 = &uart4;
37 serial5 = &uart5;
38 serial6 = &uart6;
39 serial7 = &uart7;
40 serial8 = &uart8;
41 serial9 = &uart9;
42 spi0 = &spi0;
43 spi1 = &spi1;
44 spi2 = &spi2;
45 spi3 = &spi3;
46 };
47
48 cpus {
49 #address-cells = <2>;
50 #size-cells = <0>;
51
52 cpu0: cpu@0 {
53 device_type = "cpu";
54 compatible = "arm,cortex-a55";
55 reg = <0x0 0x0>;
56 clocks = <&scmi_clk 0>;
57 #cooling-cells = <2>;
58 enable-method = "psci";
59 operating-points-v2 = <&cpu0_opp_table>;
60 };
61
62 cpu1: cpu@100 {
63 device_type = "cpu";
64 compatible = "arm,cortex-a55";
65 reg = <0x0 0x100>;
66 #cooling-cells = <2>;
67 enable-method = "psci";
68 operating-points-v2 = <&cpu0_opp_table>;
69 };
70
71 cpu2: cpu@200 {
72 device_type = "cpu";
73 compatible = "arm,cortex-a55";
74 reg = <0x0 0x200>;
75 #cooling-cells = <2>;
76 enable-method = "psci";
77 operating-points-v2 = <&cpu0_opp_table>;
78 };
79
80 cpu3: cpu@300 {
81 device_type = "cpu";
82 compatible = "arm,cortex-a55";
83 reg = <0x0 0x300>;
84 #cooling-cells = <2>;
85 enable-method = "psci";
86 operating-points-v2 = <&cpu0_opp_table>;
87 };
88 };
89
90 cpu0_opp_table: opp-table-0 {
91 compatible = "operating-points-v2";
92 opp-shared;
93
94 opp-408000000 {
95 opp-hz = /bits/ 64 <408000000>;
96 opp-microvolt = <900000 900000 1150000>;
97 clock-latency-ns = <40000>;
98 };
99
100 opp-600000000 {
101 opp-hz = /bits/ 64 <600000000>;
102 opp-microvolt = <900000 900000 1150000>;
103 };
104
105 opp-816000000 {
106 opp-hz = /bits/ 64 <816000000>;
107 opp-microvolt = <900000 900000 1150000>;
108 opp-suspend;
109 };
110
111 opp-1104000000 {
112 opp-hz = /bits/ 64 <1104000000>;
113 opp-microvolt = <900000 900000 1150000>;
114 };
115
116 opp-1416000000 {
117 opp-hz = /bits/ 64 <1416000000>;
118 opp-microvolt = <900000 900000 1150000>;
119 };
120
121 opp-1608000000 {
122 opp-hz = /bits/ 64 <1608000000>;
123 opp-microvolt = <975000 975000 1150000>;
124 };
125
126 opp-1800000000 {
127 opp-hz = /bits/ 64 <1800000000>;
128 opp-microvolt = <1050000 1050000 1150000>;
129 };
130 };
131
132 display_subsystem: display-subsystem {
133 compatible = "rockchip,display-subsystem";
134 ports = <&vop_out>;
135 };
136
137 firmware {
138 scmi: scmi {
139 compatible = "arm,scmi-smc";
140 arm,smc-id = <0x82000010>;
141 shmem = <&scmi_shmem>;
142 #address-cells = <1>;
143 #size-cells = <0>;
144
145 scmi_clk: protocol@14 {
146 reg = <0x14>;
147 #clock-cells = <1>;
148 };
149 };
150 };
151
152 gpu_opp_table: opp-table-1 {
153 compatible = "operating-points-v2";
154
155 opp-200000000 {
156 opp-hz = /bits/ 64 <200000000>;
157 opp-microvolt = <825000>;
158 };
159
160 opp-300000000 {
161 opp-hz = /bits/ 64 <300000000>;
162 opp-microvolt = <825000>;
163 };
164
165 opp-400000000 {
166 opp-hz = /bits/ 64 <400000000>;
167 opp-microvolt = <825000>;
168 };
169
170 opp-600000000 {
171 opp-hz = /bits/ 64 <600000000>;
172 opp-microvolt = <825000>;
173 };
174
175 opp-700000000 {
176 opp-hz = /bits/ 64 <700000000>;
177 opp-microvolt = <900000>;
178 };
179
180 opp-800000000 {
181 opp-hz = /bits/ 64 <800000000>;
182 opp-microvolt = <1000000>;
183 };
184 };
185
186 hdmi_sound: hdmi-sound {
187 compatible = "simple-audio-card";
188 simple-audio-card,name = "HDMI";
189 simple-audio-card,format = "i2s";
190 simple-audio-card,mclk-fs = <256>;
191 status = "disabled";
192
193 simple-audio-card,codec {
194 sound-dai = <&hdmi>;
195 };
196
197 simple-audio-card,cpu {
198 sound-dai = <&i2s0_8ch>;
199 };
200 };
201
202 pmu {
203 compatible = "arm,cortex-a55-pmu";
204 interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>,
205 <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>,
206 <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>,
207 <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
208 interrupt-affinity = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>;
209 };
210
211 psci {
212 compatible = "arm,psci-1.0";
213 method = "smc";
214 };
215
216 timer {
217 compatible = "arm,armv8-timer";
218 interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH>,
219 <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH>,
220 <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>,
221 <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH>;
222 arm,no-tick-in-suspend;
223 };
224
225 xin24m: xin24m {
226 compatible = "fixed-clock";
227 clock-frequency = <24000000>;
228 clock-output-names = "xin24m";
229 #clock-cells = <0>;
230 };
231
232 xin32k: xin32k {
233 compatible = "fixed-clock";
234 clock-frequency = <32768>;
235 clock-output-names = "xin32k";
236 pinctrl-0 = <&clk32k_out0>;
237 pinctrl-names = "default";
238 #clock-cells = <0>;
239 };
240
241 sram@10f000 {
242 compatible = "mmio-sram";
243 reg = <0x0 0x0010f000 0x0 0x100>;
244 #address-cells = <1>;
245 #size-cells = <1>;
246 ranges = <0 0x0 0x0010f000 0x100>;
247
248 scmi_shmem: sram@0 {
249 compatible = "arm,scmi-shmem";
250 reg = <0x0 0x100>;
251 };
252 };
253
254 sata1: sata@fc400000 {
255 compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci";
256 reg = <0 0xfc400000 0 0x1000>;
257 clocks = <&cru ACLK_SATA1>, <&cru CLK_SATA1_PMALIVE>,
258 <&cru CLK_SATA1_RXOOB>;
259 clock-names = "sata", "pmalive", "rxoob";
260 interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>;
261 phys = <&combphy1 PHY_TYPE_SATA>;
262 phy-names = "sata-phy";
263 ports-implemented = <0x1>;
264 power-domains = <&power RK3568_PD_PIPE>;
265 status = "disabled";
266 };
267
268 sata2: sata@fc800000 {
269 compatible = "rockchip,rk3568-dwc-ahci", "snps,dwc-ahci";
270 reg = <0 0xfc800000 0 0x1000>;
271 clocks = <&cru ACLK_SATA2>, <&cru CLK_SATA2_PMALIVE>,
272 <&cru CLK_SATA2_RXOOB>;
273 clock-names = "sata", "pmalive", "rxoob";
274 interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
275 phys = <&combphy2 PHY_TYPE_SATA>;
276 phy-names = "sata-phy";
277 ports-implemented = <0x1>;
278 power-domains = <&power RK3568_PD_PIPE>;
279 status = "disabled";
280 };
281
282 usb_host0_xhci: usb@fcc00000 {
283 compatible = "rockchip,rk3568-dwc3", "snps,dwc3";
284 reg = <0x0 0xfcc00000 0x0 0x400000>;
285 interrupts = <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>;
286 clocks = <&cru CLK_USB3OTG0_REF>, <&cru CLK_USB3OTG0_SUSPEND>,
287 <&cru ACLK_USB3OTG0>;
288 clock-names = "ref_clk", "suspend_clk",
289 "bus_clk";
290 dr_mode = "otg";
291 phy_type = "utmi_wide";
292 power-domains = <&power RK3568_PD_PIPE>;
293 resets = <&cru SRST_USB3OTG0>;
294 snps,dis_u2_susphy_quirk;
295 status = "disabled";
296 };
297
298 usb_host1_xhci: usb@fd000000 {
299 compatible = "rockchip,rk3568-dwc3", "snps,dwc3";
300 reg = <0x0 0xfd000000 0x0 0x400000>;
301 interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>;
302 clocks = <&cru CLK_USB3OTG1_REF>, <&cru CLK_USB3OTG1_SUSPEND>,
303 <&cru ACLK_USB3OTG1>;
304 clock-names = "ref_clk", "suspend_clk",
305 "bus_clk";
306 dr_mode = "host";
307 phys = <&usb2phy0_host>, <&combphy1 PHY_TYPE_USB3>;
308 phy-names = "usb2-phy", "usb3-phy";
309 phy_type = "utmi_wide";
310 power-domains = <&power RK3568_PD_PIPE>;
311 resets = <&cru SRST_USB3OTG1>;
312 snps,dis_u2_susphy_quirk;
313 status = "disabled";
314 };
315
316 gic: interrupt-controller@fd400000 {
317 compatible = "arm,gic-v3";
318 reg = <0x0 0xfd400000 0 0x10000>, /* GICD */
319 <0x0 0xfd460000 0 0x80000>; /* GICR */
320 interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH>;
321 interrupt-controller;
322 #interrupt-cells = <3>;
323 mbi-alias = <0x0 0xfd410000>;
324 mbi-ranges = <296 24>;
325 msi-controller;
326 };
327
328 usb_host0_ehci: usb@fd800000 {
329 compatible = "generic-ehci";
330 reg = <0x0 0xfd800000 0x0 0x40000>;
331 interrupts = <GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>;
332 clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>,
333 <&cru PCLK_USB>;
334 phys = <&usb2phy1_otg>;
335 phy-names = "usb";
336 status = "disabled";
337 };
338
339 usb_host0_ohci: usb@fd840000 {
340 compatible = "generic-ohci";
341 reg = <0x0 0xfd840000 0x0 0x40000>;
342 interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>;
343 clocks = <&cru HCLK_USB2HOST0>, <&cru HCLK_USB2HOST0_ARB>,
344 <&cru PCLK_USB>;
345 phys = <&usb2phy1_otg>;
346 phy-names = "usb";
347 status = "disabled";
348 };
349
350 usb_host1_ehci: usb@fd880000 {
351 compatible = "generic-ehci";
352 reg = <0x0 0xfd880000 0x0 0x40000>;
353 interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
354 clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>,
355 <&cru PCLK_USB>;
356 phys = <&usb2phy1_host>;
357 phy-names = "usb";
358 status = "disabled";
359 };
360
361 usb_host1_ohci: usb@fd8c0000 {
362 compatible = "generic-ohci";
363 reg = <0x0 0xfd8c0000 0x0 0x40000>;
364 interrupts = <GIC_SPI 134 IRQ_TYPE_LEVEL_HIGH>;
365 clocks = <&cru HCLK_USB2HOST1>, <&cru HCLK_USB2HOST1_ARB>,
366 <&cru PCLK_USB>;
367 phys = <&usb2phy1_host>;
368 phy-names = "usb";
369 status = "disabled";
370 };
371
372 pmugrf: syscon@fdc20000 {
373 compatible = "rockchip,rk3568-pmugrf", "syscon", "simple-mfd";
374 reg = <0x0 0xfdc20000 0x0 0x10000>;
375
376 pmu_io_domains: io-domains {
377 compatible = "rockchip,rk3568-pmu-io-voltage-domain";
378 status = "disabled";
379 };
380 };
381
382 pipegrf: syscon@fdc50000 {
383 reg = <0x0 0xfdc50000 0x0 0x1000>;
384 };
385
386 grf: syscon@fdc60000 {
387 compatible = "rockchip,rk3568-grf", "syscon", "simple-mfd";
388 reg = <0x0 0xfdc60000 0x0 0x10000>;
389 };
390
391 pipe_phy_grf1: syscon@fdc80000 {
392 compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
393 reg = <0x0 0xfdc80000 0x0 0x1000>;
394 };
395
396 pipe_phy_grf2: syscon@fdc90000 {
397 compatible = "rockchip,rk3568-pipe-phy-grf", "syscon";
398 reg = <0x0 0xfdc90000 0x0 0x1000>;
399 };
400
401 usb2phy0_grf: syscon@fdca0000 {
402 compatible = "rockchip,rk3568-usb2phy-grf", "syscon";
403 reg = <0x0 0xfdca0000 0x0 0x8000>;
404 };
405
406 usb2phy1_grf: syscon@fdca8000 {
407 compatible = "rockchip,rk3568-usb2phy-grf", "syscon";
408 reg = <0x0 0xfdca8000 0x0 0x8000>;
409 };
410
411 pmucru: clock-controller@fdd00000 {
412 compatible = "rockchip,rk3568-pmucru";
413 reg = <0x0 0xfdd00000 0x0 0x1000>;
414 #clock-cells = <1>;
415 #reset-cells = <1>;
416 };
417
418 cru: clock-controller@fdd20000 {
419 compatible = "rockchip,rk3568-cru";
420 reg = <0x0 0xfdd20000 0x0 0x1000>;
421 clocks = <&xin24m>;
422 clock-names = "xin24m";
423 #clock-cells = <1>;
424 #reset-cells = <1>;
425 assigned-clocks = <&cru PLL_GPLL>, <&pmucru PLL_PPLL>;
426 assigned-clock-rates = <1200000000>, <200000000>;
427 rockchip,grf = <&grf>;
428 };
429
430 i2c0: i2c@fdd40000 {
431 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
432 reg = <0x0 0xfdd40000 0x0 0x1000>;
433 interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
434 clocks = <&pmucru CLK_I2C0>, <&pmucru PCLK_I2C0>;
435 clock-names = "i2c", "pclk";
436 pinctrl-0 = <&i2c0_xfer>;
437 pinctrl-names = "default";
438 #address-cells = <1>;
439 #size-cells = <0>;
440 status = "disabled";
441 };
442
443 uart0: serial@fdd50000 {
444 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
445 reg = <0x0 0xfdd50000 0x0 0x100>;
446 interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
447 clocks = <&pmucru SCLK_UART0>, <&pmucru PCLK_UART0>;
448 clock-names = "baudclk", "apb_pclk";
449 dmas = <&dmac0 0>, <&dmac0 1>;
450 pinctrl-0 = <&uart0_xfer>;
451 pinctrl-names = "default";
452 reg-io-width = <4>;
453 reg-shift = <2>;
454 status = "disabled";
455 };
456
457 pwm0: pwm@fdd70000 {
458 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
459 reg = <0x0 0xfdd70000 0x0 0x10>;
460 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
461 clock-names = "pwm", "pclk";
462 pinctrl-0 = <&pwm0m0_pins>;
463 pinctrl-names = "default";
464 #pwm-cells = <3>;
465 status = "disabled";
466 };
467
468 pwm1: pwm@fdd70010 {
469 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
470 reg = <0x0 0xfdd70010 0x0 0x10>;
471 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
472 clock-names = "pwm", "pclk";
473 pinctrl-0 = <&pwm1m0_pins>;
474 pinctrl-names = "default";
475 #pwm-cells = <3>;
476 status = "disabled";
477 };
478
479 pwm2: pwm@fdd70020 {
480 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
481 reg = <0x0 0xfdd70020 0x0 0x10>;
482 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
483 clock-names = "pwm", "pclk";
484 pinctrl-0 = <&pwm2m0_pins>;
485 pinctrl-names = "default";
486 #pwm-cells = <3>;
487 status = "disabled";
488 };
489
490 pwm3: pwm@fdd70030 {
491 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
492 reg = <0x0 0xfdd70030 0x0 0x10>;
493 clocks = <&pmucru CLK_PWM0>, <&pmucru PCLK_PWM0>;
494 clock-names = "pwm", "pclk";
495 pinctrl-0 = <&pwm3_pins>;
496 pinctrl-names = "default";
497 #pwm-cells = <3>;
498 status = "disabled";
499 };
500
501 pmu: power-management@fdd90000 {
502 compatible = "rockchip,rk3568-pmu", "syscon", "simple-mfd";
503 reg = <0x0 0xfdd90000 0x0 0x1000>;
504
505 power: power-controller {
506 compatible = "rockchip,rk3568-power-controller";
507 #power-domain-cells = <1>;
508 #address-cells = <1>;
509 #size-cells = <0>;
510
511 /* These power domains are grouped by VD_GPU */
512 power-domain@RK3568_PD_GPU {
513 reg = <RK3568_PD_GPU>;
514 clocks = <&cru ACLK_GPU_PRE>,
515 <&cru PCLK_GPU_PRE>;
516 pm_qos = <&qos_gpu>;
517 #power-domain-cells = <0>;
518 };
519
520 /* These power domains are grouped by VD_LOGIC */
521 power-domain@RK3568_PD_VI {
522 reg = <RK3568_PD_VI>;
523 clocks = <&cru HCLK_VI>,
524 <&cru PCLK_VI>;
525 pm_qos = <&qos_isp>,
526 <&qos_vicap0>,
527 <&qos_vicap1>;
528 #power-domain-cells = <0>;
529 };
530
531 power-domain@RK3568_PD_VO {
532 reg = <RK3568_PD_VO>;
533 clocks = <&cru HCLK_VO>,
534 <&cru PCLK_VO>,
535 <&cru ACLK_VOP_PRE>;
536 pm_qos = <&qos_hdcp>,
537 <&qos_vop_m0>,
538 <&qos_vop_m1>;
539 #power-domain-cells = <0>;
540 };
541
542 power-domain@RK3568_PD_RGA {
543 reg = <RK3568_PD_RGA>;
544 clocks = <&cru HCLK_RGA_PRE>,
545 <&cru PCLK_RGA_PRE>;
546 pm_qos = <&qos_ebc>,
547 <&qos_iep>,
548 <&qos_jpeg_dec>,
549 <&qos_jpeg_enc>,
550 <&qos_rga_rd>,
551 <&qos_rga_wr>;
552 #power-domain-cells = <0>;
553 };
554
555 power-domain@RK3568_PD_VPU {
556 reg = <RK3568_PD_VPU>;
557 clocks = <&cru HCLK_VPU_PRE>;
558 pm_qos = <&qos_vpu>;
559 #power-domain-cells = <0>;
560 };
561
562 power-domain@RK3568_PD_RKVDEC {
563 clocks = <&cru HCLK_RKVDEC_PRE>;
564 reg = <RK3568_PD_RKVDEC>;
565 pm_qos = <&qos_rkvdec>;
566 #power-domain-cells = <0>;
567 };
568
569 power-domain@RK3568_PD_RKVENC {
570 reg = <RK3568_PD_RKVENC>;
571 clocks = <&cru HCLK_RKVENC_PRE>;
572 pm_qos = <&qos_rkvenc_rd_m0>,
573 <&qos_rkvenc_rd_m1>,
574 <&qos_rkvenc_wr_m0>;
575 #power-domain-cells = <0>;
576 };
577 };
578 };
579
580 gpu: gpu@fde60000 {
581 compatible = "rockchip,rk3568-mali", "arm,mali-bifrost";
582 reg = <0x0 0xfde60000 0x0 0x4000>;
583 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
584 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>,
585 <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
586 interrupt-names = "job", "mmu", "gpu";
587 clocks = <&scmi_clk 1>, <&cru CLK_GPU>;
588 clock-names = "gpu", "bus";
589 #cooling-cells = <2>;
590 operating-points-v2 = <&gpu_opp_table>;
591 power-domains = <&power RK3568_PD_GPU>;
592 status = "disabled";
593 };
594
Chris Morgane2df30c2023-02-13 16:27:37 -0600595 vpu: video-codec@fdea0400 {
596 compatible = "rockchip,rk3568-vpu";
597 reg = <0x0 0xfdea0000 0x0 0x800>;
598 interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>;
599 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
600 clock-names = "aclk", "hclk";
601 iommus = <&vdpu_mmu>;
602 power-domains = <&power RK3568_PD_VPU>;
603 };
604
605 vdpu_mmu: iommu@fdea0800 {
606 compatible = "rockchip,rk3568-iommu";
607 reg = <0x0 0xfdea0800 0x0 0x40>;
608 interrupts = <GIC_SPI 138 IRQ_TYPE_LEVEL_HIGH>;
609 clock-names = "aclk", "iface";
610 clocks = <&cru ACLK_VPU>, <&cru HCLK_VPU>;
611 power-domains = <&power RK3568_PD_VPU>;
612 #iommu-cells = <0>;
613 };
614
615 vepu: video-codec@fdee0000 {
616 compatible = "rockchip,rk3568-vepu";
617 reg = <0x0 0xfdee0000 0x0 0x800>;
618 interrupts = <GIC_SPI 64 IRQ_TYPE_LEVEL_HIGH>;
619 clocks = <&cru ACLK_JENC>, <&cru HCLK_JENC>;
620 clock-names = "aclk", "hclk";
621 iommus = <&vepu_mmu>;
622 power-domains = <&power RK3568_PD_RGA>;
623 };
624
625 vepu_mmu: iommu@fdee0800 {
626 compatible = "rockchip,rk3568-iommu";
627 reg = <0x0 0xfdee0800 0x0 0x40>;
628 interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>;
629 clocks = <&cru ACLK_JENC>, <&cru HCLK_JENC>;
630 clock-names = "aclk", "iface";
631 power-domains = <&power RK3568_PD_RGA>;
632 #iommu-cells = <0>;
633 };
634
FUKAUMI Naoki85a8ef12022-10-04 01:30:30 +0000635 sdmmc2: mmc@fe000000 {
636 compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
637 reg = <0x0 0xfe000000 0x0 0x4000>;
638 interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
639 clocks = <&cru HCLK_SDMMC2>, <&cru CLK_SDMMC2>,
640 <&cru SCLK_SDMMC2_DRV>, <&cru SCLK_SDMMC2_SAMPLE>;
641 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
642 fifo-depth = <0x100>;
643 max-frequency = <150000000>;
644 resets = <&cru SRST_SDMMC2>;
645 reset-names = "reset";
646 status = "disabled";
647 };
648
649 gmac1: ethernet@fe010000 {
650 compatible = "rockchip,rk3568-gmac", "snps,dwmac-4.20a";
651 reg = <0x0 0xfe010000 0x0 0x10000>;
652 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
653 <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
654 interrupt-names = "macirq", "eth_wake_irq";
655 clocks = <&cru SCLK_GMAC1>, <&cru SCLK_GMAC1_RX_TX>,
656 <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_MAC1_REFOUT>,
657 <&cru ACLK_GMAC1>, <&cru PCLK_GMAC1>,
658 <&cru SCLK_GMAC1_RX_TX>, <&cru CLK_GMAC1_PTP_REF>;
659 clock-names = "stmmaceth", "mac_clk_rx",
660 "mac_clk_tx", "clk_mac_refout",
661 "aclk_mac", "pclk_mac",
662 "clk_mac_speed", "ptp_ref";
663 resets = <&cru SRST_A_GMAC1>;
664 reset-names = "stmmaceth";
665 rockchip,grf = <&grf>;
666 snps,axi-config = <&gmac1_stmmac_axi_setup>;
667 snps,mixed-burst;
668 snps,mtl-rx-config = <&gmac1_mtl_rx_setup>;
669 snps,mtl-tx-config = <&gmac1_mtl_tx_setup>;
670 snps,tso;
671 status = "disabled";
672
673 mdio1: mdio {
674 compatible = "snps,dwmac-mdio";
675 #address-cells = <0x1>;
676 #size-cells = <0x0>;
677 };
678
679 gmac1_stmmac_axi_setup: stmmac-axi-config {
680 snps,blen = <0 0 0 0 16 8 4>;
681 snps,rd_osr_lmt = <8>;
682 snps,wr_osr_lmt = <4>;
683 };
684
685 gmac1_mtl_rx_setup: rx-queues-config {
686 snps,rx-queues-to-use = <1>;
687 queue0 {};
688 };
689
690 gmac1_mtl_tx_setup: tx-queues-config {
691 snps,tx-queues-to-use = <1>;
692 queue0 {};
693 };
694 };
695
696 vop: vop@fe040000 {
697 reg = <0x0 0xfe040000 0x0 0x3000>, <0x0 0xfe044000 0x0 0x1000>;
698 reg-names = "vop", "gamma-lut";
699 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
700 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>, <&cru DCLK_VOP0>,
701 <&cru DCLK_VOP1>, <&cru DCLK_VOP2>;
702 clock-names = "aclk", "hclk", "dclk_vp0", "dclk_vp1", "dclk_vp2";
703 iommus = <&vop_mmu>;
704 power-domains = <&power RK3568_PD_VO>;
705 rockchip,grf = <&grf>;
706 status = "disabled";
707
708 vop_out: ports {
709 #address-cells = <1>;
710 #size-cells = <0>;
711
712 vp0: port@0 {
713 reg = <0>;
714 #address-cells = <1>;
715 #size-cells = <0>;
716 };
717
718 vp1: port@1 {
719 reg = <1>;
720 #address-cells = <1>;
721 #size-cells = <0>;
722 };
723
724 vp2: port@2 {
725 reg = <2>;
726 #address-cells = <1>;
727 #size-cells = <0>;
728 };
729 };
730 };
731
732 vop_mmu: iommu@fe043e00 {
733 compatible = "rockchip,rk3568-iommu";
734 reg = <0x0 0xfe043e00 0x0 0x100>, <0x0 0xfe043f00 0x0 0x100>;
735 interrupts = <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>;
736 clocks = <&cru ACLK_VOP>, <&cru HCLK_VOP>;
737 clock-names = "aclk", "iface";
738 #iommu-cells = <0>;
739 status = "disabled";
740 };
741
Chris Morgane2df30c2023-02-13 16:27:37 -0600742 dsi0: dsi@fe060000 {
743 compatible = "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi";
744 reg = <0x00 0xfe060000 0x00 0x10000>;
745 interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>;
746 clock-names = "pclk", "hclk";
747 clocks = <&cru PCLK_DSITX_0>, <&cru HCLK_VO>;
748 phy-names = "dphy";
749 phys = <&dsi_dphy0>;
750 power-domains = <&power RK3568_PD_VO>;
751 reset-names = "apb";
752 resets = <&cru SRST_P_DSITX_0>;
753 rockchip,grf = <&grf>;
754 status = "disabled";
755
756 ports {
757 #address-cells = <1>;
758 #size-cells = <0>;
759
760 dsi0_in: port@0 {
761 reg = <0>;
762 };
763
764 dsi0_out: port@1 {
765 reg = <1>;
766 };
767 };
768 };
769
770 dsi1: dsi@fe070000 {
771 compatible = "rockchip,rk3568-mipi-dsi", "snps,dw-mipi-dsi";
772 reg = <0x0 0xfe070000 0x0 0x10000>;
773 interrupts = <GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
774 clock-names = "pclk", "hclk";
775 clocks = <&cru PCLK_DSITX_1>, <&cru HCLK_VO>;
776 phy-names = "dphy";
777 phys = <&dsi_dphy1>;
778 power-domains = <&power RK3568_PD_VO>;
779 reset-names = "apb";
780 resets = <&cru SRST_P_DSITX_1>;
781 rockchip,grf = <&grf>;
782 status = "disabled";
783
784 ports {
785 #address-cells = <1>;
786 #size-cells = <0>;
787
788 dsi1_in: port@0 {
789 reg = <0>;
790 };
791
792 dsi1_out: port@1 {
793 reg = <1>;
794 };
795 };
796 };
797
FUKAUMI Naoki85a8ef12022-10-04 01:30:30 +0000798 hdmi: hdmi@fe0a0000 {
799 compatible = "rockchip,rk3568-dw-hdmi";
800 reg = <0x0 0xfe0a0000 0x0 0x20000>;
801 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
802 clocks = <&cru PCLK_HDMI_HOST>,
803 <&cru CLK_HDMI_SFR>,
804 <&cru CLK_HDMI_CEC>,
805 <&pmucru CLK_HDMI_REF>,
806 <&cru HCLK_VO>;
807 clock-names = "iahb", "isfr", "cec", "ref";
808 pinctrl-names = "default";
809 pinctrl-0 = <&hdmitx_scl &hdmitx_sda &hdmitxm0_cec>;
810 power-domains = <&power RK3568_PD_VO>;
811 reg-io-width = <4>;
812 rockchip,grf = <&grf>;
813 #sound-dai-cells = <0>;
814 status = "disabled";
815
816 ports {
817 #address-cells = <1>;
818 #size-cells = <0>;
819
820 hdmi_in: port@0 {
821 reg = <0>;
822 };
823
824 hdmi_out: port@1 {
825 reg = <1>;
826 };
827 };
828 };
829
830 qos_gpu: qos@fe128000 {
831 compatible = "rockchip,rk3568-qos", "syscon";
832 reg = <0x0 0xfe128000 0x0 0x20>;
833 };
834
835 qos_rkvenc_rd_m0: qos@fe138080 {
836 compatible = "rockchip,rk3568-qos", "syscon";
837 reg = <0x0 0xfe138080 0x0 0x20>;
838 };
839
840 qos_rkvenc_rd_m1: qos@fe138100 {
841 compatible = "rockchip,rk3568-qos", "syscon";
842 reg = <0x0 0xfe138100 0x0 0x20>;
843 };
844
845 qos_rkvenc_wr_m0: qos@fe138180 {
846 compatible = "rockchip,rk3568-qos", "syscon";
847 reg = <0x0 0xfe138180 0x0 0x20>;
848 };
849
850 qos_isp: qos@fe148000 {
851 compatible = "rockchip,rk3568-qos", "syscon";
852 reg = <0x0 0xfe148000 0x0 0x20>;
853 };
854
855 qos_vicap0: qos@fe148080 {
856 compatible = "rockchip,rk3568-qos", "syscon";
857 reg = <0x0 0xfe148080 0x0 0x20>;
858 };
859
860 qos_vicap1: qos@fe148100 {
861 compatible = "rockchip,rk3568-qos", "syscon";
862 reg = <0x0 0xfe148100 0x0 0x20>;
863 };
864
865 qos_vpu: qos@fe150000 {
866 compatible = "rockchip,rk3568-qos", "syscon";
867 reg = <0x0 0xfe150000 0x0 0x20>;
868 };
869
870 qos_ebc: qos@fe158000 {
871 compatible = "rockchip,rk3568-qos", "syscon";
872 reg = <0x0 0xfe158000 0x0 0x20>;
873 };
874
875 qos_iep: qos@fe158100 {
876 compatible = "rockchip,rk3568-qos", "syscon";
877 reg = <0x0 0xfe158100 0x0 0x20>;
878 };
879
880 qos_jpeg_dec: qos@fe158180 {
881 compatible = "rockchip,rk3568-qos", "syscon";
882 reg = <0x0 0xfe158180 0x0 0x20>;
883 };
884
885 qos_jpeg_enc: qos@fe158200 {
886 compatible = "rockchip,rk3568-qos", "syscon";
887 reg = <0x0 0xfe158200 0x0 0x20>;
888 };
889
890 qos_rga_rd: qos@fe158280 {
891 compatible = "rockchip,rk3568-qos", "syscon";
892 reg = <0x0 0xfe158280 0x0 0x20>;
893 };
894
895 qos_rga_wr: qos@fe158300 {
896 compatible = "rockchip,rk3568-qos", "syscon";
897 reg = <0x0 0xfe158300 0x0 0x20>;
898 };
899
900 qos_npu: qos@fe180000 {
901 compatible = "rockchip,rk3568-qos", "syscon";
902 reg = <0x0 0xfe180000 0x0 0x20>;
903 };
904
905 qos_pcie2x1: qos@fe190000 {
906 compatible = "rockchip,rk3568-qos", "syscon";
907 reg = <0x0 0xfe190000 0x0 0x20>;
908 };
909
910 qos_sata1: qos@fe190280 {
911 compatible = "rockchip,rk3568-qos", "syscon";
912 reg = <0x0 0xfe190280 0x0 0x20>;
913 };
914
915 qos_sata2: qos@fe190300 {
916 compatible = "rockchip,rk3568-qos", "syscon";
917 reg = <0x0 0xfe190300 0x0 0x20>;
918 };
919
920 qos_usb3_0: qos@fe190380 {
921 compatible = "rockchip,rk3568-qos", "syscon";
922 reg = <0x0 0xfe190380 0x0 0x20>;
923 };
924
925 qos_usb3_1: qos@fe190400 {
926 compatible = "rockchip,rk3568-qos", "syscon";
927 reg = <0x0 0xfe190400 0x0 0x20>;
928 };
929
930 qos_rkvdec: qos@fe198000 {
931 compatible = "rockchip,rk3568-qos", "syscon";
932 reg = <0x0 0xfe198000 0x0 0x20>;
933 };
934
935 qos_hdcp: qos@fe1a8000 {
936 compatible = "rockchip,rk3568-qos", "syscon";
937 reg = <0x0 0xfe1a8000 0x0 0x20>;
938 };
939
940 qos_vop_m0: qos@fe1a8080 {
941 compatible = "rockchip,rk3568-qos", "syscon";
942 reg = <0x0 0xfe1a8080 0x0 0x20>;
943 };
944
945 qos_vop_m1: qos@fe1a8100 {
946 compatible = "rockchip,rk3568-qos", "syscon";
947 reg = <0x0 0xfe1a8100 0x0 0x20>;
948 };
949
950 pcie2x1: pcie@fe260000 {
951 compatible = "rockchip,rk3568-pcie";
952 reg = <0x3 0xc0000000 0x0 0x00400000>,
953 <0x0 0xfe260000 0x0 0x00010000>,
954 <0x3 0x3f000000 0x0 0x01000000>;
955 reg-names = "dbi", "apb", "config";
956 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>,
957 <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
958 <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>,
959 <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
960 <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
961 interrupt-names = "sys", "pmc", "msi", "legacy", "err";
962 bus-range = <0x0 0xf>;
963 clocks = <&cru ACLK_PCIE20_MST>, <&cru ACLK_PCIE20_SLV>,
964 <&cru ACLK_PCIE20_DBI>, <&cru PCLK_PCIE20>,
965 <&cru CLK_PCIE20_AUX_NDFT>;
966 clock-names = "aclk_mst", "aclk_slv",
967 "aclk_dbi", "pclk", "aux";
968 device_type = "pci";
969 interrupt-map-mask = <0 0 0 7>;
970 interrupt-map = <0 0 0 1 &pcie_intc 0>,
971 <0 0 0 2 &pcie_intc 1>,
972 <0 0 0 3 &pcie_intc 2>,
973 <0 0 0 4 &pcie_intc 3>;
974 linux,pci-domain = <0>;
975 num-ib-windows = <6>;
976 num-ob-windows = <2>;
977 max-link-speed = <2>;
978 msi-map = <0x0 &gic 0x0 0x1000>;
979 num-lanes = <1>;
980 phys = <&combphy2 PHY_TYPE_PCIE>;
981 phy-names = "pcie-phy";
982 power-domains = <&power RK3568_PD_PIPE>;
983 ranges = <0x01000000 0x0 0x3ef00000 0x3 0x3ef00000 0x0 0x00100000
984 0x02000000 0x0 0x00000000 0x3 0x00000000 0x0 0x3ef00000>;
985 resets = <&cru SRST_PCIE20_POWERUP>;
986 reset-names = "pipe";
987 #address-cells = <3>;
988 #size-cells = <2>;
989 status = "disabled";
990
991 pcie_intc: legacy-interrupt-controller {
992 #address-cells = <0>;
993 #interrupt-cells = <1>;
994 interrupt-controller;
995 interrupt-parent = <&gic>;
996 interrupts = <GIC_SPI 72 IRQ_TYPE_EDGE_RISING>;
997 };
998 };
999
1000 sdmmc0: mmc@fe2b0000 {
1001 compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
1002 reg = <0x0 0xfe2b0000 0x0 0x4000>;
1003 interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
1004 clocks = <&cru HCLK_SDMMC0>, <&cru CLK_SDMMC0>,
1005 <&cru SCLK_SDMMC0_DRV>, <&cru SCLK_SDMMC0_SAMPLE>;
1006 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1007 fifo-depth = <0x100>;
1008 max-frequency = <150000000>;
1009 resets = <&cru SRST_SDMMC0>;
1010 reset-names = "reset";
1011 status = "disabled";
1012 };
1013
1014 sdmmc1: mmc@fe2c0000 {
1015 compatible = "rockchip,rk3568-dw-mshc", "rockchip,rk3288-dw-mshc";
1016 reg = <0x0 0xfe2c0000 0x0 0x4000>;
1017 interrupts = <GIC_SPI 99 IRQ_TYPE_LEVEL_HIGH>;
1018 clocks = <&cru HCLK_SDMMC1>, <&cru CLK_SDMMC1>,
1019 <&cru SCLK_SDMMC1_DRV>, <&cru SCLK_SDMMC1_SAMPLE>;
1020 clock-names = "biu", "ciu", "ciu-drive", "ciu-sample";
1021 fifo-depth = <0x100>;
1022 max-frequency = <150000000>;
1023 resets = <&cru SRST_SDMMC1>;
1024 reset-names = "reset";
1025 status = "disabled";
1026 };
1027
1028 sfc: spi@fe300000 {
1029 compatible = "rockchip,sfc";
1030 reg = <0x0 0xfe300000 0x0 0x4000>;
1031 interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
1032 clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
1033 clock-names = "clk_sfc", "hclk_sfc";
1034 pinctrl-0 = <&fspi_pins>;
1035 pinctrl-names = "default";
1036 status = "disabled";
1037 };
1038
1039 sdhci: mmc@fe310000 {
1040 compatible = "rockchip,rk3568-dwcmshc";
1041 reg = <0x0 0xfe310000 0x0 0x10000>;
1042 interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
1043 assigned-clocks = <&cru BCLK_EMMC>, <&cru TCLK_EMMC>;
1044 assigned-clock-rates = <200000000>, <24000000>;
1045 clocks = <&cru CCLK_EMMC>, <&cru HCLK_EMMC>,
1046 <&cru ACLK_EMMC>, <&cru BCLK_EMMC>,
1047 <&cru TCLK_EMMC>;
1048 clock-names = "core", "bus", "axi", "block", "timer";
1049 status = "disabled";
1050 };
1051
FUKAUMI Naoki85a8ef12022-10-04 01:30:30 +00001052 i2s0_8ch: i2s@fe400000 {
1053 compatible = "rockchip,rk3568-i2s-tdm";
1054 reg = <0x0 0xfe400000 0x0 0x1000>;
1055 interrupts = <GIC_SPI 52 IRQ_TYPE_LEVEL_HIGH>;
1056 assigned-clocks = <&cru CLK_I2S0_8CH_TX_SRC>, <&cru CLK_I2S0_8CH_RX_SRC>;
1057 assigned-clock-rates = <1188000000>, <1188000000>;
1058 clocks = <&cru MCLK_I2S0_8CH_TX>, <&cru MCLK_I2S0_8CH_RX>, <&cru HCLK_I2S0_8CH>;
1059 clock-names = "mclk_tx", "mclk_rx", "hclk";
1060 dmas = <&dmac1 0>;
1061 dma-names = "tx";
1062 resets = <&cru SRST_M_I2S0_8CH_TX>, <&cru SRST_M_I2S0_8CH_RX>;
1063 reset-names = "tx-m", "rx-m";
1064 rockchip,grf = <&grf>;
1065 #sound-dai-cells = <0>;
1066 status = "disabled";
1067 };
1068
1069 i2s1_8ch: i2s@fe410000 {
1070 compatible = "rockchip,rk3568-i2s-tdm";
1071 reg = <0x0 0xfe410000 0x0 0x1000>;
1072 interrupts = <GIC_SPI 53 IRQ_TYPE_LEVEL_HIGH>;
1073 assigned-clocks = <&cru CLK_I2S1_8CH_TX_SRC>, <&cru CLK_I2S1_8CH_RX_SRC>;
1074 assigned-clock-rates = <1188000000>, <1188000000>;
1075 clocks = <&cru MCLK_I2S1_8CH_TX>, <&cru MCLK_I2S1_8CH_RX>,
1076 <&cru HCLK_I2S1_8CH>;
1077 clock-names = "mclk_tx", "mclk_rx", "hclk";
1078 dmas = <&dmac1 3>, <&dmac1 2>;
1079 dma-names = "rx", "tx";
1080 resets = <&cru SRST_M_I2S1_8CH_TX>, <&cru SRST_M_I2S1_8CH_RX>;
1081 reset-names = "tx-m", "rx-m";
1082 rockchip,grf = <&grf>;
1083 pinctrl-names = "default";
1084 pinctrl-0 = <&i2s1m0_sclktx &i2s1m0_sclkrx
1085 &i2s1m0_lrcktx &i2s1m0_lrckrx
1086 &i2s1m0_sdi0 &i2s1m0_sdi1
1087 &i2s1m0_sdi2 &i2s1m0_sdi3
1088 &i2s1m0_sdo0 &i2s1m0_sdo1
1089 &i2s1m0_sdo2 &i2s1m0_sdo3>;
1090 #sound-dai-cells = <0>;
1091 status = "disabled";
1092 };
1093
Chris Morgane2df30c2023-02-13 16:27:37 -06001094 i2s2_2ch: i2s@fe420000 {
1095 compatible = "rockchip,rk3568-i2s-tdm";
1096 reg = <0x0 0xfe420000 0x0 0x1000>;
1097 interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
1098 assigned-clocks = <&cru CLK_I2S2_2CH_SRC>;
1099 assigned-clock-rates = <1188000000>;
1100 clocks = <&cru MCLK_I2S2_2CH>, <&cru MCLK_I2S2_2CH>, <&cru HCLK_I2S2_2CH>;
1101 clock-names = "mclk_tx", "mclk_rx", "hclk";
1102 dmas = <&dmac1 4>, <&dmac1 5>;
1103 dma-names = "tx", "rx";
1104 resets = <&cru SRST_M_I2S2_2CH>;
1105 reset-names = "m";
1106 rockchip,grf = <&grf>;
1107 pinctrl-names = "default";
1108 pinctrl-0 = <&i2s2m0_sclktx
1109 &i2s2m0_lrcktx
1110 &i2s2m0_sdi
1111 &i2s2m0_sdo>;
1112 #sound-dai-cells = <0>;
1113 status = "disabled";
1114 };
1115
FUKAUMI Naoki85a8ef12022-10-04 01:30:30 +00001116 i2s3_2ch: i2s@fe430000 {
1117 compatible = "rockchip,rk3568-i2s-tdm";
1118 reg = <0x0 0xfe430000 0x0 0x1000>;
1119 interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
1120 clocks = <&cru MCLK_I2S3_2CH_TX>, <&cru MCLK_I2S3_2CH_RX>,
1121 <&cru HCLK_I2S3_2CH>;
1122 clock-names = "mclk_tx", "mclk_rx", "hclk";
1123 dmas = <&dmac1 6>, <&dmac1 7>;
1124 dma-names = "tx", "rx";
1125 resets = <&cru SRST_M_I2S3_2CH_TX>, <&cru SRST_M_I2S3_2CH_RX>;
1126 reset-names = "tx-m", "rx-m";
1127 rockchip,grf = <&grf>;
1128 #sound-dai-cells = <0>;
1129 status = "disabled";
1130 };
1131
1132 pdm: pdm@fe440000 {
1133 compatible = "rockchip,rk3568-pdm";
1134 reg = <0x0 0xfe440000 0x0 0x1000>;
1135 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
1136 clocks = <&cru MCLK_PDM>, <&cru HCLK_PDM>;
1137 clock-names = "pdm_clk", "pdm_hclk";
1138 dmas = <&dmac1 9>;
1139 dma-names = "rx";
1140 pinctrl-0 = <&pdmm0_clk
1141 &pdmm0_clk1
1142 &pdmm0_sdi0
1143 &pdmm0_sdi1
1144 &pdmm0_sdi2
1145 &pdmm0_sdi3>;
1146 pinctrl-names = "default";
1147 resets = <&cru SRST_M_PDM>;
1148 reset-names = "pdm-m";
1149 #sound-dai-cells = <0>;
1150 status = "disabled";
1151 };
1152
Chris Morgane2df30c2023-02-13 16:27:37 -06001153 spdif: spdif@fe460000 {
1154 compatible = "rockchip,rk3568-spdif";
1155 reg = <0x0 0xfe460000 0x0 0x1000>;
1156 interrupts = <GIC_SPI 102 IRQ_TYPE_LEVEL_HIGH>;
1157 clock-names = "mclk", "hclk";
1158 clocks = <&cru MCLK_SPDIF_8CH>, <&cru HCLK_SPDIF_8CH>;
1159 dmas = <&dmac1 1>;
1160 dma-names = "tx";
1161 pinctrl-names = "default";
1162 pinctrl-0 = <&spdifm0_tx>;
1163 #sound-dai-cells = <0>;
1164 status = "disabled";
1165 };
1166
FUKAUMI Naoki85a8ef12022-10-04 01:30:30 +00001167 dmac0: dma-controller@fe530000 {
1168 compatible = "arm,pl330", "arm,primecell";
1169 reg = <0x0 0xfe530000 0x0 0x4000>;
1170 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>,
1171 <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
1172 arm,pl330-periph-burst;
1173 clocks = <&cru ACLK_BUS>;
1174 clock-names = "apb_pclk";
1175 #dma-cells = <1>;
1176 };
1177
1178 dmac1: dma-controller@fe550000 {
1179 compatible = "arm,pl330", "arm,primecell";
1180 reg = <0x0 0xfe550000 0x0 0x4000>;
1181 interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>,
1182 <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
1183 arm,pl330-periph-burst;
1184 clocks = <&cru ACLK_BUS>;
1185 clock-names = "apb_pclk";
1186 #dma-cells = <1>;
1187 };
1188
1189 i2c1: i2c@fe5a0000 {
1190 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
1191 reg = <0x0 0xfe5a0000 0x0 0x1000>;
1192 interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>;
1193 clocks = <&cru CLK_I2C1>, <&cru PCLK_I2C1>;
1194 clock-names = "i2c", "pclk";
1195 pinctrl-0 = <&i2c1_xfer>;
1196 pinctrl-names = "default";
1197 #address-cells = <1>;
1198 #size-cells = <0>;
1199 status = "disabled";
1200 };
1201
1202 i2c2: i2c@fe5b0000 {
1203 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
1204 reg = <0x0 0xfe5b0000 0x0 0x1000>;
1205 interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
1206 clocks = <&cru CLK_I2C2>, <&cru PCLK_I2C2>;
1207 clock-names = "i2c", "pclk";
1208 pinctrl-0 = <&i2c2m0_xfer>;
1209 pinctrl-names = "default";
1210 #address-cells = <1>;
1211 #size-cells = <0>;
1212 status = "disabled";
1213 };
1214
1215 i2c3: i2c@fe5c0000 {
1216 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
1217 reg = <0x0 0xfe5c0000 0x0 0x1000>;
1218 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
1219 clocks = <&cru CLK_I2C3>, <&cru PCLK_I2C3>;
1220 clock-names = "i2c", "pclk";
1221 pinctrl-0 = <&i2c3m0_xfer>;
1222 pinctrl-names = "default";
1223 #address-cells = <1>;
1224 #size-cells = <0>;
1225 status = "disabled";
1226 };
1227
1228 i2c4: i2c@fe5d0000 {
1229 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
1230 reg = <0x0 0xfe5d0000 0x0 0x1000>;
1231 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
1232 clocks = <&cru CLK_I2C4>, <&cru PCLK_I2C4>;
1233 clock-names = "i2c", "pclk";
1234 pinctrl-0 = <&i2c4m0_xfer>;
1235 pinctrl-names = "default";
1236 #address-cells = <1>;
1237 #size-cells = <0>;
1238 status = "disabled";
1239 };
1240
1241 i2c5: i2c@fe5e0000 {
1242 compatible = "rockchip,rk3568-i2c", "rockchip,rk3399-i2c";
1243 reg = <0x0 0xfe5e0000 0x0 0x1000>;
1244 interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>;
1245 clocks = <&cru CLK_I2C5>, <&cru PCLK_I2C5>;
1246 clock-names = "i2c", "pclk";
1247 pinctrl-0 = <&i2c5m0_xfer>;
1248 pinctrl-names = "default";
1249 #address-cells = <1>;
1250 #size-cells = <0>;
1251 status = "disabled";
1252 };
1253
1254 wdt: watchdog@fe600000 {
1255 compatible = "rockchip,rk3568-wdt", "snps,dw-wdt";
1256 reg = <0x0 0xfe600000 0x0 0x100>;
1257 interrupts = <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>;
1258 clocks = <&cru TCLK_WDT_NS>, <&cru PCLK_WDT_NS>;
1259 clock-names = "tclk", "pclk";
1260 };
1261
1262 spi0: spi@fe610000 {
1263 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
1264 reg = <0x0 0xfe610000 0x0 0x1000>;
1265 interrupts = <GIC_SPI 103 IRQ_TYPE_LEVEL_HIGH>;
1266 clocks = <&cru CLK_SPI0>, <&cru PCLK_SPI0>;
1267 clock-names = "spiclk", "apb_pclk";
1268 dmas = <&dmac0 20>, <&dmac0 21>;
1269 dma-names = "tx", "rx";
1270 pinctrl-names = "default";
1271 pinctrl-0 = <&spi0m0_cs0 &spi0m0_cs1 &spi0m0_pins>;
1272 #address-cells = <1>;
1273 #size-cells = <0>;
1274 status = "disabled";
1275 };
1276
1277 spi1: spi@fe620000 {
1278 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
1279 reg = <0x0 0xfe620000 0x0 0x1000>;
1280 interrupts = <GIC_SPI 104 IRQ_TYPE_LEVEL_HIGH>;
1281 clocks = <&cru CLK_SPI1>, <&cru PCLK_SPI1>;
1282 clock-names = "spiclk", "apb_pclk";
1283 dmas = <&dmac0 22>, <&dmac0 23>;
1284 dma-names = "tx", "rx";
1285 pinctrl-names = "default";
1286 pinctrl-0 = <&spi1m0_cs0 &spi1m0_cs1 &spi1m0_pins>;
1287 #address-cells = <1>;
1288 #size-cells = <0>;
1289 status = "disabled";
1290 };
1291
1292 spi2: spi@fe630000 {
1293 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
1294 reg = <0x0 0xfe630000 0x0 0x1000>;
1295 interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
1296 clocks = <&cru CLK_SPI2>, <&cru PCLK_SPI2>;
1297 clock-names = "spiclk", "apb_pclk";
1298 dmas = <&dmac0 24>, <&dmac0 25>;
1299 dma-names = "tx", "rx";
1300 pinctrl-names = "default";
1301 pinctrl-0 = <&spi2m0_cs0 &spi2m0_cs1 &spi2m0_pins>;
1302 #address-cells = <1>;
1303 #size-cells = <0>;
1304 status = "disabled";
1305 };
1306
1307 spi3: spi@fe640000 {
1308 compatible = "rockchip,rk3568-spi", "rockchip,rk3066-spi";
1309 reg = <0x0 0xfe640000 0x0 0x1000>;
1310 interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
1311 clocks = <&cru CLK_SPI3>, <&cru PCLK_SPI3>;
1312 clock-names = "spiclk", "apb_pclk";
1313 dmas = <&dmac0 26>, <&dmac0 27>;
1314 dma-names = "tx", "rx";
1315 pinctrl-names = "default";
1316 pinctrl-0 = <&spi3m0_cs0 &spi3m0_cs1 &spi3m0_pins>;
1317 #address-cells = <1>;
1318 #size-cells = <0>;
1319 status = "disabled";
1320 };
1321
1322 uart1: serial@fe650000 {
1323 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1324 reg = <0x0 0xfe650000 0x0 0x100>;
1325 interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
1326 clocks = <&cru SCLK_UART1>, <&cru PCLK_UART1>;
1327 clock-names = "baudclk", "apb_pclk";
1328 dmas = <&dmac0 2>, <&dmac0 3>;
1329 pinctrl-0 = <&uart1m0_xfer>;
1330 pinctrl-names = "default";
1331 reg-io-width = <4>;
1332 reg-shift = <2>;
1333 status = "disabled";
1334 };
1335
1336 uart2: serial@fe660000 {
1337 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1338 reg = <0x0 0xfe660000 0x0 0x100>;
1339 interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>;
1340 clocks = <&cru SCLK_UART2>, <&cru PCLK_UART2>;
1341 clock-names = "baudclk", "apb_pclk";
1342 dmas = <&dmac0 4>, <&dmac0 5>;
1343 pinctrl-0 = <&uart2m0_xfer>;
1344 pinctrl-names = "default";
1345 reg-io-width = <4>;
1346 reg-shift = <2>;
1347 status = "disabled";
1348 };
1349
1350 uart3: serial@fe670000 {
1351 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1352 reg = <0x0 0xfe670000 0x0 0x100>;
1353 interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
1354 clocks = <&cru SCLK_UART3>, <&cru PCLK_UART3>;
1355 clock-names = "baudclk", "apb_pclk";
1356 dmas = <&dmac0 6>, <&dmac0 7>;
1357 pinctrl-0 = <&uart3m0_xfer>;
1358 pinctrl-names = "default";
1359 reg-io-width = <4>;
1360 reg-shift = <2>;
1361 status = "disabled";
1362 };
1363
1364 uart4: serial@fe680000 {
1365 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1366 reg = <0x0 0xfe680000 0x0 0x100>;
1367 interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>;
1368 clocks = <&cru SCLK_UART4>, <&cru PCLK_UART4>;
1369 clock-names = "baudclk", "apb_pclk";
1370 dmas = <&dmac0 8>, <&dmac0 9>;
1371 pinctrl-0 = <&uart4m0_xfer>;
1372 pinctrl-names = "default";
1373 reg-io-width = <4>;
1374 reg-shift = <2>;
1375 status = "disabled";
1376 };
1377
1378 uart5: serial@fe690000 {
1379 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1380 reg = <0x0 0xfe690000 0x0 0x100>;
1381 interrupts = <GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
1382 clocks = <&cru SCLK_UART5>, <&cru PCLK_UART5>;
1383 clock-names = "baudclk", "apb_pclk";
1384 dmas = <&dmac0 10>, <&dmac0 11>;
1385 pinctrl-0 = <&uart5m0_xfer>;
1386 pinctrl-names = "default";
1387 reg-io-width = <4>;
1388 reg-shift = <2>;
1389 status = "disabled";
1390 };
1391
1392 uart6: serial@fe6a0000 {
1393 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1394 reg = <0x0 0xfe6a0000 0x0 0x100>;
1395 interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>;
1396 clocks = <&cru SCLK_UART6>, <&cru PCLK_UART6>;
1397 clock-names = "baudclk", "apb_pclk";
1398 dmas = <&dmac0 12>, <&dmac0 13>;
1399 pinctrl-0 = <&uart6m0_xfer>;
1400 pinctrl-names = "default";
1401 reg-io-width = <4>;
1402 reg-shift = <2>;
1403 status = "disabled";
1404 };
1405
1406 uart7: serial@fe6b0000 {
1407 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1408 reg = <0x0 0xfe6b0000 0x0 0x100>;
1409 interrupts = <GIC_SPI 123 IRQ_TYPE_LEVEL_HIGH>;
1410 clocks = <&cru SCLK_UART7>, <&cru PCLK_UART7>;
1411 clock-names = "baudclk", "apb_pclk";
1412 dmas = <&dmac0 14>, <&dmac0 15>;
1413 pinctrl-0 = <&uart7m0_xfer>;
1414 pinctrl-names = "default";
1415 reg-io-width = <4>;
1416 reg-shift = <2>;
1417 status = "disabled";
1418 };
1419
1420 uart8: serial@fe6c0000 {
1421 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1422 reg = <0x0 0xfe6c0000 0x0 0x100>;
1423 interrupts = <GIC_SPI 124 IRQ_TYPE_LEVEL_HIGH>;
1424 clocks = <&cru SCLK_UART8>, <&cru PCLK_UART8>;
1425 clock-names = "baudclk", "apb_pclk";
1426 dmas = <&dmac0 16>, <&dmac0 17>;
1427 pinctrl-0 = <&uart8m0_xfer>;
1428 pinctrl-names = "default";
1429 reg-io-width = <4>;
1430 reg-shift = <2>;
1431 status = "disabled";
1432 };
1433
1434 uart9: serial@fe6d0000 {
1435 compatible = "rockchip,rk3568-uart", "snps,dw-apb-uart";
1436 reg = <0x0 0xfe6d0000 0x0 0x100>;
1437 interrupts = <GIC_SPI 125 IRQ_TYPE_LEVEL_HIGH>;
1438 clocks = <&cru SCLK_UART9>, <&cru PCLK_UART9>;
1439 clock-names = "baudclk", "apb_pclk";
1440 dmas = <&dmac0 18>, <&dmac0 19>;
1441 pinctrl-0 = <&uart9m0_xfer>;
1442 pinctrl-names = "default";
1443 reg-io-width = <4>;
1444 reg-shift = <2>;
1445 status = "disabled";
1446 };
1447
1448 thermal_zones: thermal-zones {
1449 cpu_thermal: cpu-thermal {
1450 polling-delay-passive = <100>;
1451 polling-delay = <1000>;
1452
1453 thermal-sensors = <&tsadc 0>;
1454
1455 trips {
1456 cpu_alert0: cpu_alert0 {
1457 temperature = <70000>;
1458 hysteresis = <2000>;
1459 type = "passive";
1460 };
1461 cpu_alert1: cpu_alert1 {
1462 temperature = <75000>;
1463 hysteresis = <2000>;
1464 type = "passive";
1465 };
1466 cpu_crit: cpu_crit {
1467 temperature = <95000>;
1468 hysteresis = <2000>;
1469 type = "critical";
1470 };
1471 };
1472
1473 cooling-maps {
1474 map0 {
1475 trip = <&cpu_alert0>;
1476 cooling-device =
1477 <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1478 <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1479 <&cpu2 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>,
1480 <&cpu3 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1481 };
1482 };
1483 };
1484
1485 gpu_thermal: gpu-thermal {
1486 polling-delay-passive = <20>; /* milliseconds */
1487 polling-delay = <1000>; /* milliseconds */
1488
1489 thermal-sensors = <&tsadc 1>;
1490
1491 trips {
1492 gpu_threshold: gpu-threshold {
1493 temperature = <70000>;
1494 hysteresis = <2000>;
1495 type = "passive";
1496 };
1497 gpu_target: gpu-target {
1498 temperature = <75000>;
1499 hysteresis = <2000>;
1500 type = "passive";
1501 };
1502 gpu_crit: gpu-crit {
1503 temperature = <95000>;
1504 hysteresis = <2000>;
1505 type = "critical";
1506 };
1507 };
1508
1509 cooling-maps {
1510 map0 {
1511 trip = <&gpu_target>;
1512 cooling-device =
1513 <&gpu THERMAL_NO_LIMIT THERMAL_NO_LIMIT>;
1514 };
1515 };
1516 };
1517 };
1518
1519 tsadc: tsadc@fe710000 {
1520 compatible = "rockchip,rk3568-tsadc";
1521 reg = <0x0 0xfe710000 0x0 0x100>;
1522 interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
1523 assigned-clocks = <&cru CLK_TSADC_TSEN>, <&cru CLK_TSADC>;
1524 assigned-clock-rates = <17000000>, <700000>;
1525 clocks = <&cru CLK_TSADC>, <&cru PCLK_TSADC>;
1526 clock-names = "tsadc", "apb_pclk";
1527 resets = <&cru SRST_P_TSADC>, <&cru SRST_TSADC>,
1528 <&cru SRST_TSADCPHY>;
1529 rockchip,grf = <&grf>;
1530 rockchip,hw-tshut-temp = <95000>;
1531 pinctrl-names = "init", "default", "sleep";
1532 pinctrl-0 = <&tsadc_pin>;
1533 pinctrl-1 = <&tsadc_shutorg>;
1534 pinctrl-2 = <&tsadc_pin>;
1535 #thermal-sensor-cells = <1>;
1536 status = "disabled";
1537 };
1538
1539 saradc: saradc@fe720000 {
1540 compatible = "rockchip,rk3568-saradc", "rockchip,rk3399-saradc";
1541 reg = <0x0 0xfe720000 0x0 0x100>;
1542 interrupts = <GIC_SPI 93 IRQ_TYPE_LEVEL_HIGH>;
1543 clocks = <&cru CLK_SARADC>, <&cru PCLK_SARADC>;
1544 clock-names = "saradc", "apb_pclk";
1545 resets = <&cru SRST_P_SARADC>;
1546 reset-names = "saradc-apb";
1547 #io-channel-cells = <1>;
1548 status = "disabled";
1549 };
1550
1551 pwm4: pwm@fe6e0000 {
1552 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1553 reg = <0x0 0xfe6e0000 0x0 0x10>;
1554 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
1555 clock-names = "pwm", "pclk";
1556 pinctrl-0 = <&pwm4_pins>;
1557 pinctrl-names = "default";
1558 #pwm-cells = <3>;
1559 status = "disabled";
1560 };
1561
1562 pwm5: pwm@fe6e0010 {
1563 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1564 reg = <0x0 0xfe6e0010 0x0 0x10>;
1565 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
1566 clock-names = "pwm", "pclk";
1567 pinctrl-0 = <&pwm5_pins>;
1568 pinctrl-names = "default";
1569 #pwm-cells = <3>;
1570 status = "disabled";
1571 };
1572
1573 pwm6: pwm@fe6e0020 {
1574 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1575 reg = <0x0 0xfe6e0020 0x0 0x10>;
1576 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
1577 clock-names = "pwm", "pclk";
1578 pinctrl-0 = <&pwm6_pins>;
1579 pinctrl-names = "default";
1580 #pwm-cells = <3>;
1581 status = "disabled";
1582 };
1583
1584 pwm7: pwm@fe6e0030 {
1585 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1586 reg = <0x0 0xfe6e0030 0x0 0x10>;
1587 clocks = <&cru CLK_PWM1>, <&cru PCLK_PWM1>;
1588 clock-names = "pwm", "pclk";
1589 pinctrl-0 = <&pwm7_pins>;
1590 pinctrl-names = "default";
1591 #pwm-cells = <3>;
1592 status = "disabled";
1593 };
1594
1595 pwm8: pwm@fe6f0000 {
1596 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1597 reg = <0x0 0xfe6f0000 0x0 0x10>;
1598 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
1599 clock-names = "pwm", "pclk";
1600 pinctrl-0 = <&pwm8m0_pins>;
1601 pinctrl-names = "default";
1602 #pwm-cells = <3>;
1603 status = "disabled";
1604 };
1605
1606 pwm9: pwm@fe6f0010 {
1607 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1608 reg = <0x0 0xfe6f0010 0x0 0x10>;
1609 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
1610 clock-names = "pwm", "pclk";
1611 pinctrl-0 = <&pwm9m0_pins>;
1612 pinctrl-names = "default";
1613 #pwm-cells = <3>;
1614 status = "disabled";
1615 };
1616
1617 pwm10: pwm@fe6f0020 {
1618 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1619 reg = <0x0 0xfe6f0020 0x0 0x10>;
1620 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
1621 clock-names = "pwm", "pclk";
1622 pinctrl-0 = <&pwm10m0_pins>;
1623 pinctrl-names = "default";
1624 #pwm-cells = <3>;
1625 status = "disabled";
1626 };
1627
1628 pwm11: pwm@fe6f0030 {
1629 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1630 reg = <0x0 0xfe6f0030 0x0 0x10>;
1631 clocks = <&cru CLK_PWM2>, <&cru PCLK_PWM2>;
1632 clock-names = "pwm", "pclk";
1633 pinctrl-0 = <&pwm11m0_pins>;
1634 pinctrl-names = "default";
1635 #pwm-cells = <3>;
1636 status = "disabled";
1637 };
1638
1639 pwm12: pwm@fe700000 {
1640 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1641 reg = <0x0 0xfe700000 0x0 0x10>;
1642 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
1643 clock-names = "pwm", "pclk";
1644 pinctrl-0 = <&pwm12m0_pins>;
1645 pinctrl-names = "default";
1646 #pwm-cells = <3>;
1647 status = "disabled";
1648 };
1649
1650 pwm13: pwm@fe700010 {
1651 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1652 reg = <0x0 0xfe700010 0x0 0x10>;
1653 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
1654 clock-names = "pwm", "pclk";
1655 pinctrl-0 = <&pwm13m0_pins>;
1656 pinctrl-names = "default";
1657 #pwm-cells = <3>;
1658 status = "disabled";
1659 };
1660
1661 pwm14: pwm@fe700020 {
1662 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1663 reg = <0x0 0xfe700020 0x0 0x10>;
1664 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
1665 clock-names = "pwm", "pclk";
1666 pinctrl-0 = <&pwm14m0_pins>;
1667 pinctrl-names = "default";
1668 #pwm-cells = <3>;
1669 status = "disabled";
1670 };
1671
1672 pwm15: pwm@fe700030 {
1673 compatible = "rockchip,rk3568-pwm", "rockchip,rk3328-pwm";
1674 reg = <0x0 0xfe700030 0x0 0x10>;
1675 clocks = <&cru CLK_PWM3>, <&cru PCLK_PWM3>;
1676 clock-names = "pwm", "pclk";
1677 pinctrl-0 = <&pwm15m0_pins>;
1678 pinctrl-names = "default";
1679 #pwm-cells = <3>;
1680 status = "disabled";
1681 };
1682
1683 combphy1: phy@fe830000 {
1684 compatible = "rockchip,rk3568-naneng-combphy";
1685 reg = <0x0 0xfe830000 0x0 0x100>;
1686 clocks = <&pmucru CLK_PCIEPHY1_REF>,
1687 <&cru PCLK_PIPEPHY1>,
1688 <&cru PCLK_PIPE>;
1689 clock-names = "ref", "apb", "pipe";
1690 assigned-clocks = <&pmucru CLK_PCIEPHY1_REF>;
1691 assigned-clock-rates = <100000000>;
1692 resets = <&cru SRST_PIPEPHY1>;
1693 rockchip,pipe-grf = <&pipegrf>;
1694 rockchip,pipe-phy-grf = <&pipe_phy_grf1>;
1695 #phy-cells = <1>;
1696 status = "disabled";
1697 };
1698
1699 combphy2: phy@fe840000 {
1700 compatible = "rockchip,rk3568-naneng-combphy";
1701 reg = <0x0 0xfe840000 0x0 0x100>;
1702 clocks = <&pmucru CLK_PCIEPHY2_REF>,
1703 <&cru PCLK_PIPEPHY2>,
1704 <&cru PCLK_PIPE>;
1705 clock-names = "ref", "apb", "pipe";
1706 assigned-clocks = <&pmucru CLK_PCIEPHY2_REF>;
1707 assigned-clock-rates = <100000000>;
1708 resets = <&cru SRST_PIPEPHY2>;
1709 rockchip,pipe-grf = <&pipegrf>;
1710 rockchip,pipe-phy-grf = <&pipe_phy_grf2>;
1711 #phy-cells = <1>;
1712 status = "disabled";
1713 };
1714
Chris Morgane2df30c2023-02-13 16:27:37 -06001715 csi_dphy: phy@fe870000 {
1716 compatible = "rockchip,rk3568-csi-dphy";
1717 reg = <0x0 0xfe870000 0x0 0x10000>;
1718 clocks = <&cru PCLK_MIPICSIPHY>;
1719 clock-names = "pclk";
1720 #phy-cells = <0>;
1721 resets = <&cru SRST_P_MIPICSIPHY>;
1722 reset-names = "apb";
1723 rockchip,grf = <&grf>;
1724 status = "disabled";
1725 };
1726
1727 dsi_dphy0: mipi-dphy@fe850000 {
1728 compatible = "rockchip,rk3568-dsi-dphy";
1729 reg = <0x0 0xfe850000 0x0 0x10000>;
1730 clock-names = "ref", "pclk";
1731 clocks = <&pmucru CLK_MIPIDSIPHY0_REF>, <&cru PCLK_MIPIDSIPHY0>;
1732 #phy-cells = <0>;
1733 power-domains = <&power RK3568_PD_VO>;
1734 reset-names = "apb";
1735 resets = <&cru SRST_P_MIPIDSIPHY0>;
1736 status = "disabled";
1737 };
1738
1739 dsi_dphy1: mipi-dphy@fe860000 {
1740 compatible = "rockchip,rk3568-dsi-dphy";
1741 reg = <0x0 0xfe860000 0x0 0x10000>;
1742 clock-names = "ref", "pclk";
1743 clocks = <&pmucru CLK_MIPIDSIPHY1_REF>, <&cru PCLK_MIPIDSIPHY1>;
1744 #phy-cells = <0>;
1745 power-domains = <&power RK3568_PD_VO>;
1746 reset-names = "apb";
1747 resets = <&cru SRST_P_MIPIDSIPHY1>;
1748 status = "disabled";
1749 };
1750
FUKAUMI Naoki85a8ef12022-10-04 01:30:30 +00001751 usb2phy0: usb2phy@fe8a0000 {
1752 compatible = "rockchip,rk3568-usb2phy";
1753 reg = <0x0 0xfe8a0000 0x0 0x10000>;
1754 clocks = <&pmucru CLK_USBPHY0_REF>;
1755 clock-names = "phyclk";
1756 clock-output-names = "clk_usbphy0_480m";
1757 interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>;
1758 rockchip,usbgrf = <&usb2phy0_grf>;
1759 #clock-cells = <0>;
1760 status = "disabled";
1761
1762 usb2phy0_host: host-port {
1763 #phy-cells = <0>;
1764 status = "disabled";
1765 };
1766
1767 usb2phy0_otg: otg-port {
1768 #phy-cells = <0>;
1769 status = "disabled";
1770 };
1771 };
1772
1773 usb2phy1: usb2phy@fe8b0000 {
1774 compatible = "rockchip,rk3568-usb2phy";
1775 reg = <0x0 0xfe8b0000 0x0 0x10000>;
1776 clocks = <&pmucru CLK_USBPHY1_REF>;
1777 clock-names = "phyclk";
1778 clock-output-names = "clk_usbphy1_480m";
1779 interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>;
1780 rockchip,usbgrf = <&usb2phy1_grf>;
1781 #clock-cells = <0>;
1782 status = "disabled";
1783
1784 usb2phy1_host: host-port {
1785 #phy-cells = <0>;
1786 status = "disabled";
1787 };
1788
1789 usb2phy1_otg: otg-port {
1790 #phy-cells = <0>;
1791 status = "disabled";
1792 };
1793 };
1794
1795 pinctrl: pinctrl {
1796 compatible = "rockchip,rk3568-pinctrl";
1797 rockchip,grf = <&grf>;
1798 rockchip,pmu = <&pmugrf>;
1799 #address-cells = <2>;
1800 #size-cells = <2>;
1801 ranges;
1802
1803 gpio0: gpio@fdd60000 {
1804 compatible = "rockchip,gpio-bank";
1805 reg = <0x0 0xfdd60000 0x0 0x100>;
1806 interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
1807 clocks = <&pmucru PCLK_GPIO0>, <&pmucru DBCLK_GPIO0>;
1808 gpio-controller;
Chris Morgane92754e2023-02-13 16:27:41 -06001809 gpio-ranges = <&pinctrl 0 0 32>;
FUKAUMI Naoki85a8ef12022-10-04 01:30:30 +00001810 #gpio-cells = <2>;
1811 interrupt-controller;
1812 #interrupt-cells = <2>;
1813 };
1814
1815 gpio1: gpio@fe740000 {
1816 compatible = "rockchip,gpio-bank";
1817 reg = <0x0 0xfe740000 0x0 0x100>;
1818 interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
1819 clocks = <&cru PCLK_GPIO1>, <&cru DBCLK_GPIO1>;
1820 gpio-controller;
Chris Morgane92754e2023-02-13 16:27:41 -06001821 gpio-ranges = <&pinctrl 0 32 32>;
FUKAUMI Naoki85a8ef12022-10-04 01:30:30 +00001822 #gpio-cells = <2>;
1823 interrupt-controller;
1824 #interrupt-cells = <2>;
1825 };
1826
1827 gpio2: gpio@fe750000 {
1828 compatible = "rockchip,gpio-bank";
1829 reg = <0x0 0xfe750000 0x0 0x100>;
1830 interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
1831 clocks = <&cru PCLK_GPIO2>, <&cru DBCLK_GPIO2>;
1832 gpio-controller;
Chris Morgane92754e2023-02-13 16:27:41 -06001833 gpio-ranges = <&pinctrl 0 64 32>;
FUKAUMI Naoki85a8ef12022-10-04 01:30:30 +00001834 #gpio-cells = <2>;
1835 interrupt-controller;
1836 #interrupt-cells = <2>;
1837 };
1838
1839 gpio3: gpio@fe760000 {
1840 compatible = "rockchip,gpio-bank";
1841 reg = <0x0 0xfe760000 0x0 0x100>;
1842 interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
1843 clocks = <&cru PCLK_GPIO3>, <&cru DBCLK_GPIO3>;
1844 gpio-controller;
Chris Morgane92754e2023-02-13 16:27:41 -06001845 gpio-ranges = <&pinctrl 0 96 32>;
FUKAUMI Naoki85a8ef12022-10-04 01:30:30 +00001846 #gpio-cells = <2>;
1847 interrupt-controller;
1848 #interrupt-cells = <2>;
1849 };
1850
1851 gpio4: gpio@fe770000 {
1852 compatible = "rockchip,gpio-bank";
1853 reg = <0x0 0xfe770000 0x0 0x100>;
1854 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
1855 clocks = <&cru PCLK_GPIO4>, <&cru DBCLK_GPIO4>;
1856 gpio-controller;
Chris Morgane92754e2023-02-13 16:27:41 -06001857 gpio-ranges = <&pinctrl 0 128 32>;
FUKAUMI Naoki85a8ef12022-10-04 01:30:30 +00001858 #gpio-cells = <2>;
1859 interrupt-controller;
1860 #interrupt-cells = <2>;
1861 };
1862 };
1863};
1864
1865#include "rk3568-pinctrl.dtsi"