blob: fc1af9b608ba716b9fb6803c7517c8480d184818 [file] [log] [blame]
Andre Przywara7514ed32018-07-04 14:16:36 +01001/*
2 * Copyright (C) 2015 Jens Kuske <jenskuske@gmail.com>
3 *
4 * This file is dual-licensed: you can use it either under the terms
5 * of the GPL or the X11 license, at your option. Note that this dual
6 * licensing only applies to this file, and not this project as a
7 * whole.
8 *
9 * a) This file is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of the
12 * License, or (at your option) any later version.
13 *
14 * This file is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * Or, alternatively,
20 *
21 * b) Permission is hereby granted, free of charge, to any person
22 * obtaining a copy of this software and associated documentation
23 * files (the "Software"), to deal in the Software without
24 * restriction, including without limitation the rights to use,
25 * copy, modify, merge, publish, distribute, sublicense, and/or
26 * sell copies of the Software, and to permit persons to whom the
27 * Software is furnished to do so, subject to the following
28 * conditions:
29 *
30 * The above copyright notice and this permission notice shall be
31 * included in all copies or substantial portions of the Software.
32 *
33 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
34 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
35 * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
36 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
37 * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
38 * WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
39 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
40 * OTHER DEALINGS IN THE SOFTWARE.
41 */
42
Andre Przywaraceda40a2022-09-13 00:52:52 +010043#include <dt-bindings/clock/sun6i-rtc.h>
Andre Przywara7514ed32018-07-04 14:16:36 +010044#include <dt-bindings/clock/sun8i-de2.h>
45#include <dt-bindings/clock/sun8i-h3-ccu.h>
46#include <dt-bindings/clock/sun8i-r-ccu.h>
47#include <dt-bindings/interrupt-controller/arm-gic.h>
48#include <dt-bindings/reset/sun8i-de2.h>
49#include <dt-bindings/reset/sun8i-h3-ccu.h>
50#include <dt-bindings/reset/sun8i-r-ccu.h>
51
52/ {
53 interrupt-parent = <&gic>;
54 #address-cells = <1>;
55 #size-cells = <1>;
56
57 chosen {
58 #address-cells = <1>;
59 #size-cells = <1>;
60 ranges;
61
62 framebuffer-hdmi {
63 compatible = "allwinner,simple-framebuffer",
64 "simple-framebuffer";
65 allwinner,pipeline = "mixer0-lcd0-hdmi";
66 clocks = <&display_clocks CLK_MIXER0>,
67 <&ccu CLK_TCON0>, <&ccu CLK_HDMI>;
68 status = "disabled";
69 };
70
71 framebuffer-tve {
72 compatible = "allwinner,simple-framebuffer",
73 "simple-framebuffer";
74 allwinner,pipeline = "mixer1-lcd1-tve";
75 clocks = <&display_clocks CLK_MIXER1>,
76 <&ccu CLK_TVE>;
77 status = "disabled";
78 };
79 };
80
81 clocks {
82 #address-cells = <1>;
83 #size-cells = <1>;
84 ranges;
85
86 osc24M: osc24M_clk {
87 #clock-cells = <0>;
88 compatible = "fixed-clock";
89 clock-frequency = <24000000>;
Chen-Yu Tsaib5fe5232020-01-12 23:36:13 +080090 clock-accuracy = <50000>;
Andre Przywara7514ed32018-07-04 14:16:36 +010091 clock-output-names = "osc24M";
92 };
93
94 osc32k: osc32k_clk {
95 #clock-cells = <0>;
96 compatible = "fixed-clock";
97 clock-frequency = <32768>;
Chen-Yu Tsaib5fe5232020-01-12 23:36:13 +080098 clock-accuracy = <50000>;
99 clock-output-names = "ext_osc32k";
Andre Przywara7514ed32018-07-04 14:16:36 +0100100 };
101 };
102
103 de: display-engine {
104 compatible = "allwinner,sun8i-h3-display-engine";
105 allwinner,pipelines = <&mixer0>;
106 status = "disabled";
107 };
108
109 soc {
110 compatible = "simple-bus";
111 #address-cells = <1>;
112 #size-cells = <1>;
Chen-Yu Tsaib5fe5232020-01-12 23:36:13 +0800113 dma-ranges;
Andre Przywara7514ed32018-07-04 14:16:36 +0100114 ranges;
115
116 display_clocks: clock@1000000 {
117 /* compatible is in per SoC .dtsi file */
Andre Przywara58f68612021-05-25 01:20:25 +0100118 reg = <0x01000000 0x10000>;
Chen-Yu Tsaib5fe5232020-01-12 23:36:13 +0800119 clocks = <&ccu CLK_BUS_DE>,
120 <&ccu CLK_DE>;
121 clock-names = "bus",
122 "mod";
Andre Przywara7514ed32018-07-04 14:16:36 +0100123 resets = <&ccu RST_BUS_DE>;
124 #clock-cells = <1>;
125 #reset-cells = <1>;
126 };
127
128 mixer0: mixer@1100000 {
129 compatible = "allwinner,sun8i-h3-de2-mixer-0";
130 reg = <0x01100000 0x100000>;
131 clocks = <&display_clocks CLK_BUS_MIXER0>,
132 <&display_clocks CLK_MIXER0>;
133 clock-names = "bus",
134 "mod";
135 resets = <&display_clocks RST_MIXER0>;
136
137 ports {
138 #address-cells = <1>;
139 #size-cells = <0>;
140
141 mixer0_out: port@1 {
142 reg = <1>;
143
144 mixer0_out_tcon0: endpoint {
145 remote-endpoint = <&tcon0_in_mixer0>;
146 };
147 };
148 };
149 };
150
Andre Przywara7514ed32018-07-04 14:16:36 +0100151 dma: dma-controller@1c02000 {
152 compatible = "allwinner,sun8i-h3-dma";
153 reg = <0x01c02000 0x1000>;
154 interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL_HIGH>;
155 clocks = <&ccu CLK_BUS_DMA>;
156 resets = <&ccu RST_BUS_DMA>;
157 #dma-cells = <1>;
158 };
159
160 tcon0: lcd-controller@1c0c000 {
161 compatible = "allwinner,sun8i-h3-tcon-tv",
162 "allwinner,sun8i-a83t-tcon-tv";
163 reg = <0x01c0c000 0x1000>;
164 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
165 clocks = <&ccu CLK_BUS_TCON0>, <&ccu CLK_TCON0>;
166 clock-names = "ahb", "tcon-ch1";
167 resets = <&ccu RST_BUS_TCON0>;
168 reset-names = "lcd";
169
170 ports {
171 #address-cells = <1>;
172 #size-cells = <0>;
173
174 tcon0_in: port@0 {
175 reg = <0>;
176
177 tcon0_in_mixer0: endpoint {
178 remote-endpoint = <&mixer0_out_tcon0>;
179 };
180 };
181
182 tcon0_out: port@1 {
183 #address-cells = <1>;
184 #size-cells = <0>;
185 reg = <1>;
186
187 tcon0_out_hdmi: endpoint@1 {
188 reg = <1>;
189 remote-endpoint = <&hdmi_in_tcon0>;
190 };
191 };
192 };
193 };
194
195 mmc0: mmc@1c0f000 {
196 /* compatible and clocks are in per SoC .dtsi file */
197 reg = <0x01c0f000 0x1000>;
198 pinctrl-names = "default";
199 pinctrl-0 = <&mmc0_pins>;
200 resets = <&ccu RST_BUS_MMC0>;
201 reset-names = "ahb";
202 interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
203 status = "disabled";
204 #address-cells = <1>;
205 #size-cells = <0>;
206 };
207
208 mmc1: mmc@1c10000 {
209 /* compatible and clocks are in per SoC .dtsi file */
210 reg = <0x01c10000 0x1000>;
211 pinctrl-names = "default";
212 pinctrl-0 = <&mmc1_pins>;
213 resets = <&ccu RST_BUS_MMC1>;
214 reset-names = "ahb";
215 interrupts = <GIC_SPI 61 IRQ_TYPE_LEVEL_HIGH>;
216 status = "disabled";
217 #address-cells = <1>;
218 #size-cells = <0>;
219 };
220
221 mmc2: mmc@1c11000 {
222 /* compatible and clocks are in per SoC .dtsi file */
223 reg = <0x01c11000 0x1000>;
224 resets = <&ccu RST_BUS_MMC2>;
225 reset-names = "ahb";
226 interrupts = <GIC_SPI 62 IRQ_TYPE_LEVEL_HIGH>;
227 status = "disabled";
228 #address-cells = <1>;
229 #size-cells = <0>;
230 };
231
Chen-Yu Tsaib5fe5232020-01-12 23:36:13 +0800232 sid: eeprom@1c14000 {
233 /* compatible is in per SoC .dtsi file */
234 reg = <0x1c14000 0x400>;
235 #address-cells = <1>;
236 #size-cells = <1>;
237
238 ths_calibration: thermal-sensor-calibration@34 {
239 reg = <0x34 4>;
240 };
241 };
242
Andre Przywara58f68612021-05-25 01:20:25 +0100243 msgbox: mailbox@1c17000 {
244 compatible = "allwinner,sun8i-h3-msgbox",
245 "allwinner,sun6i-a31-msgbox";
246 reg = <0x01c17000 0x1000>;
247 clocks = <&ccu CLK_BUS_MSGBOX>;
248 resets = <&ccu RST_BUS_MSGBOX>;
249 interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
250 #mbox-cells = <1>;
251 };
252
Andre Przywara7514ed32018-07-04 14:16:36 +0100253 usb_otg: usb@1c19000 {
254 compatible = "allwinner,sun8i-h3-musb";
255 reg = <0x01c19000 0x400>;
256 clocks = <&ccu CLK_BUS_OTG>;
257 resets = <&ccu RST_BUS_OTG>;
258 interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
259 interrupt-names = "mc";
260 phys = <&usbphy 0>;
261 phy-names = "usb";
262 extcon = <&usbphy 0>;
Chen-Yu Tsaib5fe5232020-01-12 23:36:13 +0800263 dr_mode = "otg";
Andre Przywara7514ed32018-07-04 14:16:36 +0100264 status = "disabled";
265 };
266
267 usbphy: phy@1c19400 {
268 compatible = "allwinner,sun8i-h3-usb-phy";
269 reg = <0x01c19400 0x2c>,
270 <0x01c1a800 0x4>,
271 <0x01c1b800 0x4>,
272 <0x01c1c800 0x4>,
273 <0x01c1d800 0x4>;
274 reg-names = "phy_ctrl",
275 "pmu0",
276 "pmu1",
277 "pmu2",
278 "pmu3";
279 clocks = <&ccu CLK_USB_PHY0>,
280 <&ccu CLK_USB_PHY1>,
281 <&ccu CLK_USB_PHY2>,
282 <&ccu CLK_USB_PHY3>;
283 clock-names = "usb0_phy",
284 "usb1_phy",
285 "usb2_phy",
286 "usb3_phy";
287 resets = <&ccu RST_USB_PHY0>,
288 <&ccu RST_USB_PHY1>,
289 <&ccu RST_USB_PHY2>,
290 <&ccu RST_USB_PHY3>;
291 reset-names = "usb0_reset",
292 "usb1_reset",
293 "usb2_reset",
294 "usb3_reset";
295 status = "disabled";
296 #phy-cells = <1>;
297 };
298
299 ehci0: usb@1c1a000 {
300 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
301 reg = <0x01c1a000 0x100>;
302 interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>;
303 clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>;
304 resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
Andre Przywara6621cc82023-01-12 11:18:05 +0000305 phys = <&usbphy 0>;
306 phy-names = "usb";
Andre Przywara7514ed32018-07-04 14:16:36 +0100307 status = "disabled";
308 };
309
310 ohci0: usb@1c1a400 {
311 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
312 reg = <0x01c1a400 0x100>;
313 interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
314 clocks = <&ccu CLK_BUS_EHCI0>, <&ccu CLK_BUS_OHCI0>,
315 <&ccu CLK_USB_OHCI0>;
316 resets = <&ccu RST_BUS_EHCI0>, <&ccu RST_BUS_OHCI0>;
Andre Przywara6621cc82023-01-12 11:18:05 +0000317 phys = <&usbphy 0>;
318 phy-names = "usb";
Andre Przywara7514ed32018-07-04 14:16:36 +0100319 status = "disabled";
320 };
321
322 ehci1: usb@1c1b000 {
323 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
324 reg = <0x01c1b000 0x100>;
325 interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>;
326 clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>;
327 resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>;
328 phys = <&usbphy 1>;
329 phy-names = "usb";
330 status = "disabled";
331 };
332
333 ohci1: usb@1c1b400 {
334 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
335 reg = <0x01c1b400 0x100>;
336 interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
337 clocks = <&ccu CLK_BUS_EHCI1>, <&ccu CLK_BUS_OHCI1>,
338 <&ccu CLK_USB_OHCI1>;
339 resets = <&ccu RST_BUS_EHCI1>, <&ccu RST_BUS_OHCI1>;
340 phys = <&usbphy 1>;
341 phy-names = "usb";
342 status = "disabled";
343 };
344
345 ehci2: usb@1c1c000 {
346 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
347 reg = <0x01c1c000 0x100>;
348 interrupts = <GIC_SPI 76 IRQ_TYPE_LEVEL_HIGH>;
349 clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>;
350 resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>;
351 phys = <&usbphy 2>;
352 phy-names = "usb";
353 status = "disabled";
354 };
355
356 ohci2: usb@1c1c400 {
357 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
358 reg = <0x01c1c400 0x100>;
359 interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_HIGH>;
360 clocks = <&ccu CLK_BUS_EHCI2>, <&ccu CLK_BUS_OHCI2>,
361 <&ccu CLK_USB_OHCI2>;
362 resets = <&ccu RST_BUS_EHCI2>, <&ccu RST_BUS_OHCI2>;
363 phys = <&usbphy 2>;
364 phy-names = "usb";
365 status = "disabled";
366 };
367
368 ehci3: usb@1c1d000 {
369 compatible = "allwinner,sun8i-h3-ehci", "generic-ehci";
370 reg = <0x01c1d000 0x100>;
371 interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>;
372 clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>;
373 resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>;
374 phys = <&usbphy 3>;
375 phy-names = "usb";
376 status = "disabled";
377 };
378
379 ohci3: usb@1c1d400 {
380 compatible = "allwinner,sun8i-h3-ohci", "generic-ohci";
381 reg = <0x01c1d400 0x100>;
382 interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>;
383 clocks = <&ccu CLK_BUS_EHCI3>, <&ccu CLK_BUS_OHCI3>,
384 <&ccu CLK_USB_OHCI3>;
385 resets = <&ccu RST_BUS_EHCI3>, <&ccu RST_BUS_OHCI3>;
386 phys = <&usbphy 3>;
387 phy-names = "usb";
388 status = "disabled";
389 };
390
391 ccu: clock@1c20000 {
392 /* compatible is in per SoC .dtsi file */
393 reg = <0x01c20000 0x400>;
Andre Przywaraceda40a2022-09-13 00:52:52 +0100394 clocks = <&osc24M>, <&rtc CLK_OSC32K>;
Andre Przywara7514ed32018-07-04 14:16:36 +0100395 clock-names = "hosc", "losc";
396 #clock-cells = <1>;
397 #reset-cells = <1>;
398 };
399
400 pio: pinctrl@1c20800 {
401 /* compatible is in per SoC .dtsi file */
402 reg = <0x01c20800 0x400>;
403 interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>,
404 <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
Andre Przywaraceda40a2022-09-13 00:52:52 +0100405 clocks = <&ccu CLK_BUS_PIO>, <&osc24M>,
406 <&rtc CLK_OSC32K>;
Andre Przywara7514ed32018-07-04 14:16:36 +0100407 clock-names = "apb", "hosc", "losc";
408 gpio-controller;
409 #gpio-cells = <3>;
410 interrupt-controller;
411 #interrupt-cells = <3>;
412
Chen-Yu Tsaib5fe5232020-01-12 23:36:13 +0800413 csi_pins: csi-pins {
414 pins = "PE0", "PE2", "PE3", "PE4", "PE5",
415 "PE6", "PE7", "PE8", "PE9", "PE10",
416 "PE11";
417 function = "csi";
418 };
419
420 emac_rgmii_pins: emac-rgmii-pins {
Andre Przywara7514ed32018-07-04 14:16:36 +0100421 pins = "PD0", "PD1", "PD2", "PD3", "PD4",
422 "PD5", "PD7", "PD8", "PD9", "PD10",
423 "PD12", "PD13", "PD15", "PD16", "PD17";
424 function = "emac";
425 drive-strength = <40>;
426 };
427
Chen-Yu Tsaib5fe5232020-01-12 23:36:13 +0800428 i2c0_pins: i2c0-pins {
Andre Przywara7514ed32018-07-04 14:16:36 +0100429 pins = "PA11", "PA12";
430 function = "i2c0";
431 };
432
Chen-Yu Tsaib5fe5232020-01-12 23:36:13 +0800433 i2c1_pins: i2c1-pins {
Andre Przywara7514ed32018-07-04 14:16:36 +0100434 pins = "PA18", "PA19";
435 function = "i2c1";
436 };
437
Chen-Yu Tsaib5fe5232020-01-12 23:36:13 +0800438 i2c2_pins: i2c2-pins {
Andre Przywara7514ed32018-07-04 14:16:36 +0100439 pins = "PE12", "PE13";
440 function = "i2c2";
441 };
442
Chen-Yu Tsaib5fe5232020-01-12 23:36:13 +0800443 mmc0_pins: mmc0-pins {
Andre Przywara7514ed32018-07-04 14:16:36 +0100444 pins = "PF0", "PF1", "PF2", "PF3",
445 "PF4", "PF5";
446 function = "mmc0";
447 drive-strength = <30>;
448 bias-pull-up;
449 };
450
Chen-Yu Tsaib5fe5232020-01-12 23:36:13 +0800451 mmc1_pins: mmc1-pins {
Andre Przywara7514ed32018-07-04 14:16:36 +0100452 pins = "PG0", "PG1", "PG2", "PG3",
453 "PG4", "PG5";
454 function = "mmc1";
455 drive-strength = <30>;
456 bias-pull-up;
457 };
458
Chen-Yu Tsaib5fe5232020-01-12 23:36:13 +0800459 mmc2_8bit_pins: mmc2-8bit-pins {
Andre Przywara7514ed32018-07-04 14:16:36 +0100460 pins = "PC5", "PC6", "PC8",
461 "PC9", "PC10", "PC11",
462 "PC12", "PC13", "PC14",
463 "PC15", "PC16";
464 function = "mmc2";
465 drive-strength = <30>;
466 bias-pull-up;
467 };
468
Chen-Yu Tsaib5fe5232020-01-12 23:36:13 +0800469 spdif_tx_pin: spdif-tx-pin {
Andre Przywara7514ed32018-07-04 14:16:36 +0100470 pins = "PA17";
471 function = "spdif";
472 };
473
Chen-Yu Tsaib5fe5232020-01-12 23:36:13 +0800474 spi0_pins: spi0-pins {
Andre Przywara7514ed32018-07-04 14:16:36 +0100475 pins = "PC0", "PC1", "PC2", "PC3";
476 function = "spi0";
477 };
478
Chen-Yu Tsaib5fe5232020-01-12 23:36:13 +0800479 spi1_pins: spi1-pins {
Andre Przywara7514ed32018-07-04 14:16:36 +0100480 pins = "PA15", "PA16", "PA14", "PA13";
481 function = "spi1";
482 };
483
Chen-Yu Tsaib5fe5232020-01-12 23:36:13 +0800484 uart0_pa_pins: uart0-pa-pins {
Andre Przywara7514ed32018-07-04 14:16:36 +0100485 pins = "PA4", "PA5";
486 function = "uart0";
487 };
488
Chen-Yu Tsaib5fe5232020-01-12 23:36:13 +0800489 uart1_pins: uart1-pins {
Andre Przywara7514ed32018-07-04 14:16:36 +0100490 pins = "PG6", "PG7";
491 function = "uart1";
492 };
493
Chen-Yu Tsaib5fe5232020-01-12 23:36:13 +0800494 uart1_rts_cts_pins: uart1-rts-cts-pins {
Andre Przywara7514ed32018-07-04 14:16:36 +0100495 pins = "PG8", "PG9";
496 function = "uart1";
497 };
498
Chen-Yu Tsaib5fe5232020-01-12 23:36:13 +0800499 uart2_pins: uart2-pins {
Andre Przywara7514ed32018-07-04 14:16:36 +0100500 pins = "PA0", "PA1";
501 function = "uart2";
502 };
503
Chen-Yu Tsaib5fe5232020-01-12 23:36:13 +0800504 uart2_rts_cts_pins: uart2-rts-cts-pins {
505 pins = "PA2", "PA3";
506 function = "uart2";
507 };
508
509 uart3_pins: uart3-pins {
Andre Przywara7514ed32018-07-04 14:16:36 +0100510 pins = "PA13", "PA14";
511 function = "uart3";
512 };
513
Chen-Yu Tsaib5fe5232020-01-12 23:36:13 +0800514 uart3_rts_cts_pins: uart3-rts-cts-pins {
Andre Przywara7514ed32018-07-04 14:16:36 +0100515 pins = "PA15", "PA16";
516 function = "uart3";
517 };
518 };
519
520 timer@1c20c00 {
Chen-Yu Tsaib5fe5232020-01-12 23:36:13 +0800521 compatible = "allwinner,sun8i-a23-timer";
Andre Przywara7514ed32018-07-04 14:16:36 +0100522 reg = <0x01c20c00 0xa0>;
523 interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>,
524 <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
525 clocks = <&osc24M>;
526 };
527
528 emac: ethernet@1c30000 {
529 compatible = "allwinner,sun8i-h3-emac";
530 syscon = <&syscon>;
531 reg = <0x01c30000 0x10000>;
532 interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
533 interrupt-names = "macirq";
534 resets = <&ccu RST_BUS_EMAC>;
535 reset-names = "stmmaceth";
536 clocks = <&ccu CLK_BUS_EMAC>;
537 clock-names = "stmmaceth";
Andre Przywara7514ed32018-07-04 14:16:36 +0100538 status = "disabled";
539
540 mdio: mdio {
541 #address-cells = <1>;
542 #size-cells = <0>;
543 compatible = "snps,dwmac-mdio";
544 };
545
546 mdio-mux {
547 compatible = "allwinner,sun8i-h3-mdio-mux";
548 #address-cells = <1>;
549 #size-cells = <0>;
550
551 mdio-parent-bus = <&mdio>;
552 /* Only one MDIO is usable at the time */
553 internal_mdio: mdio@1 {
554 compatible = "allwinner,sun8i-h3-mdio-internal";
555 reg = <1>;
556 #address-cells = <1>;
557 #size-cells = <0>;
558
559 int_mii_phy: ethernet-phy@1 {
560 compatible = "ethernet-phy-ieee802.3-c22";
561 reg = <1>;
562 clocks = <&ccu CLK_BUS_EPHY>;
563 resets = <&ccu RST_BUS_EPHY>;
564 };
565 };
566
567 external_mdio: mdio@2 {
568 reg = <2>;
569 #address-cells = <1>;
570 #size-cells = <0>;
571 };
572 };
573 };
574
Chen-Yu Tsaib5fe5232020-01-12 23:36:13 +0800575 mbus: dram-controller@1c62000 {
Samuel Holland2c597852022-04-27 15:31:27 -0500576 /* compatible is in per SoC .dtsi file */
577 reg = <0x01c62000 0x1000>,
578 <0x01c63000 0x1000>;
579 reg-names = "mbus", "dram";
580 clocks = <&ccu CLK_MBUS>,
581 <&ccu CLK_DRAM>,
582 <&ccu CLK_BUS_DRAM>;
583 clock-names = "mbus", "dram", "bus";
Andre Przywara58f68612021-05-25 01:20:25 +0100584 #address-cells = <1>;
585 #size-cells = <1>;
Chen-Yu Tsaib5fe5232020-01-12 23:36:13 +0800586 dma-ranges = <0x00000000 0x40000000 0xc0000000>;
587 #interconnect-cells = <1>;
588 };
589
Andre Przywara7514ed32018-07-04 14:16:36 +0100590 spi0: spi@1c68000 {
591 compatible = "allwinner,sun8i-h3-spi";
592 reg = <0x01c68000 0x1000>;
593 interrupts = <GIC_SPI 65 IRQ_TYPE_LEVEL_HIGH>;
594 clocks = <&ccu CLK_BUS_SPI0>, <&ccu CLK_SPI0>;
595 clock-names = "ahb", "mod";
596 dmas = <&dma 23>, <&dma 23>;
597 dma-names = "rx", "tx";
598 pinctrl-names = "default";
599 pinctrl-0 = <&spi0_pins>;
600 resets = <&ccu RST_BUS_SPI0>;
601 status = "disabled";
602 #address-cells = <1>;
603 #size-cells = <0>;
604 };
605
606 spi1: spi@1c69000 {
607 compatible = "allwinner,sun8i-h3-spi";
608 reg = <0x01c69000 0x1000>;
609 interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>;
610 clocks = <&ccu CLK_BUS_SPI1>, <&ccu CLK_SPI1>;
611 clock-names = "ahb", "mod";
612 dmas = <&dma 24>, <&dma 24>;
613 dma-names = "rx", "tx";
614 pinctrl-names = "default";
615 pinctrl-0 = <&spi1_pins>;
616 resets = <&ccu RST_BUS_SPI1>;
617 status = "disabled";
618 #address-cells = <1>;
619 #size-cells = <0>;
620 };
621
622 wdt0: watchdog@1c20ca0 {
623 compatible = "allwinner,sun6i-a31-wdt";
624 reg = <0x01c20ca0 0x20>;
625 interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>;
Chen-Yu Tsaib5fe5232020-01-12 23:36:13 +0800626 clocks = <&osc24M>;
Andre Przywara7514ed32018-07-04 14:16:36 +0100627 };
628
629 spdif: spdif@1c21000 {
630 #sound-dai-cells = <0>;
631 compatible = "allwinner,sun8i-h3-spdif";
632 reg = <0x01c21000 0x400>;
633 interrupts = <GIC_SPI 12 IRQ_TYPE_LEVEL_HIGH>;
634 clocks = <&ccu CLK_BUS_SPDIF>, <&ccu CLK_SPDIF>;
635 resets = <&ccu RST_BUS_SPDIF>;
636 clock-names = "apb", "spdif";
637 dmas = <&dma 2>;
638 dma-names = "tx";
639 status = "disabled";
640 };
641
642 pwm: pwm@1c21400 {
643 compatible = "allwinner,sun8i-h3-pwm";
644 reg = <0x01c21400 0x8>;
645 clocks = <&osc24M>;
646 #pwm-cells = <3>;
647 status = "disabled";
648 };
649
650 i2s0: i2s@1c22000 {
651 #sound-dai-cells = <0>;
652 compatible = "allwinner,sun8i-h3-i2s";
653 reg = <0x01c22000 0x400>;
654 interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>;
655 clocks = <&ccu CLK_BUS_I2S0>, <&ccu CLK_I2S0>;
656 clock-names = "apb", "mod";
657 dmas = <&dma 3>, <&dma 3>;
658 resets = <&ccu RST_BUS_I2S0>;
659 dma-names = "rx", "tx";
660 status = "disabled";
661 };
662
663 i2s1: i2s@1c22400 {
664 #sound-dai-cells = <0>;
665 compatible = "allwinner,sun8i-h3-i2s";
666 reg = <0x01c22400 0x400>;
667 interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
668 clocks = <&ccu CLK_BUS_I2S1>, <&ccu CLK_I2S1>;
669 clock-names = "apb", "mod";
670 dmas = <&dma 4>, <&dma 4>;
671 resets = <&ccu RST_BUS_I2S1>;
672 dma-names = "rx", "tx";
673 status = "disabled";
674 };
675
Andre Przywara58f68612021-05-25 01:20:25 +0100676 i2s2: i2s@1c22800 {
677 #sound-dai-cells = <0>;
678 compatible = "allwinner,sun8i-h3-i2s";
679 reg = <0x01c22800 0x400>;
680 interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
681 clocks = <&ccu CLK_BUS_I2S2>, <&ccu CLK_I2S2>;
682 clock-names = "apb", "mod";
683 dmas = <&dma 27>;
684 resets = <&ccu RST_BUS_I2S2>;
685 dma-names = "tx";
686 status = "disabled";
687 };
688
Andre Przywara7514ed32018-07-04 14:16:36 +0100689 codec: codec@1c22c00 {
690 #sound-dai-cells = <0>;
691 compatible = "allwinner,sun8i-h3-codec";
692 reg = <0x01c22c00 0x400>;
693 interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
694 clocks = <&ccu CLK_BUS_CODEC>, <&ccu CLK_AC_DIG>;
695 clock-names = "apb", "codec";
696 resets = <&ccu RST_BUS_CODEC>;
697 dmas = <&dma 15>, <&dma 15>;
698 dma-names = "rx", "tx";
699 allwinner,codec-analog-controls = <&codec_analog>;
700 status = "disabled";
701 };
702
703 uart0: serial@1c28000 {
704 compatible = "snps,dw-apb-uart";
705 reg = <0x01c28000 0x400>;
706 interrupts = <GIC_SPI 0 IRQ_TYPE_LEVEL_HIGH>;
707 reg-shift = <2>;
708 reg-io-width = <4>;
709 clocks = <&ccu CLK_BUS_UART0>;
710 resets = <&ccu RST_BUS_UART0>;
711 dmas = <&dma 6>, <&dma 6>;
712 dma-names = "rx", "tx";
713 status = "disabled";
714 };
715
716 uart1: serial@1c28400 {
717 compatible = "snps,dw-apb-uart";
718 reg = <0x01c28400 0x400>;
719 interrupts = <GIC_SPI 1 IRQ_TYPE_LEVEL_HIGH>;
720 reg-shift = <2>;
721 reg-io-width = <4>;
722 clocks = <&ccu CLK_BUS_UART1>;
723 resets = <&ccu RST_BUS_UART1>;
724 dmas = <&dma 7>, <&dma 7>;
725 dma-names = "rx", "tx";
726 status = "disabled";
727 };
728
729 uart2: serial@1c28800 {
730 compatible = "snps,dw-apb-uart";
731 reg = <0x01c28800 0x400>;
732 interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
733 reg-shift = <2>;
734 reg-io-width = <4>;
735 clocks = <&ccu CLK_BUS_UART2>;
736 resets = <&ccu RST_BUS_UART2>;
737 dmas = <&dma 8>, <&dma 8>;
738 dma-names = "rx", "tx";
739 status = "disabled";
740 };
741
742 uart3: serial@1c28c00 {
743 compatible = "snps,dw-apb-uart";
744 reg = <0x01c28c00 0x400>;
745 interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;
746 reg-shift = <2>;
747 reg-io-width = <4>;
748 clocks = <&ccu CLK_BUS_UART3>;
749 resets = <&ccu RST_BUS_UART3>;
750 dmas = <&dma 9>, <&dma 9>;
751 dma-names = "rx", "tx";
752 status = "disabled";
753 };
754
755 i2c0: i2c@1c2ac00 {
756 compatible = "allwinner,sun6i-a31-i2c";
757 reg = <0x01c2ac00 0x400>;
758 interrupts = <GIC_SPI 6 IRQ_TYPE_LEVEL_HIGH>;
759 clocks = <&ccu CLK_BUS_I2C0>;
760 resets = <&ccu RST_BUS_I2C0>;
761 pinctrl-names = "default";
762 pinctrl-0 = <&i2c0_pins>;
763 status = "disabled";
764 #address-cells = <1>;
765 #size-cells = <0>;
766 };
767
768 i2c1: i2c@1c2b000 {
769 compatible = "allwinner,sun6i-a31-i2c";
770 reg = <0x01c2b000 0x400>;
771 interrupts = <GIC_SPI 7 IRQ_TYPE_LEVEL_HIGH>;
772 clocks = <&ccu CLK_BUS_I2C1>;
773 resets = <&ccu RST_BUS_I2C1>;
774 pinctrl-names = "default";
775 pinctrl-0 = <&i2c1_pins>;
776 status = "disabled";
777 #address-cells = <1>;
778 #size-cells = <0>;
779 };
780
781 i2c2: i2c@1c2b400 {
782 compatible = "allwinner,sun6i-a31-i2c";
783 reg = <0x01c2b400 0x400>;
784 interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
785 clocks = <&ccu CLK_BUS_I2C2>;
786 resets = <&ccu RST_BUS_I2C2>;
787 pinctrl-names = "default";
788 pinctrl-0 = <&i2c2_pins>;
789 status = "disabled";
790 #address-cells = <1>;
791 #size-cells = <0>;
792 };
793
794 gic: interrupt-controller@1c81000 {
795 compatible = "arm,gic-400";
796 reg = <0x01c81000 0x1000>,
797 <0x01c82000 0x2000>,
798 <0x01c84000 0x2000>,
799 <0x01c86000 0x2000>;
800 interrupt-controller;
801 #interrupt-cells = <3>;
802 interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
803 };
804
Chen-Yu Tsaib5fe5232020-01-12 23:36:13 +0800805 csi: camera@1cb0000 {
806 compatible = "allwinner,sun8i-h3-csi";
807 reg = <0x01cb0000 0x1000>;
808 interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
809 clocks = <&ccu CLK_BUS_CSI>,
810 <&ccu CLK_CSI_SCLK>,
811 <&ccu CLK_DRAM_CSI>;
812 clock-names = "bus", "mod", "ram";
813 resets = <&ccu RST_BUS_CSI>;
814 pinctrl-names = "default";
815 pinctrl-0 = <&csi_pins>;
816 status = "disabled";
817 };
818
Andre Przywara7514ed32018-07-04 14:16:36 +0100819 hdmi: hdmi@1ee0000 {
820 compatible = "allwinner,sun8i-h3-dw-hdmi",
821 "allwinner,sun8i-a83t-dw-hdmi";
822 reg = <0x01ee0000 0x10000>;
823 reg-io-width = <1>;
824 interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
825 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
Andre Przywaraceda40a2022-09-13 00:52:52 +0100826 <&ccu CLK_HDMI>, <&rtc CLK_OSC32K>;
Samuel Holland2c597852022-04-27 15:31:27 -0500827 clock-names = "iahb", "isfr", "tmds", "cec";
Andre Przywara7514ed32018-07-04 14:16:36 +0100828 resets = <&ccu RST_BUS_HDMI1>;
829 reset-names = "ctrl";
830 phys = <&hdmi_phy>;
Chen-Yu Tsaib5fe5232020-01-12 23:36:13 +0800831 phy-names = "phy";
Andre Przywara7514ed32018-07-04 14:16:36 +0100832 status = "disabled";
833
834 ports {
835 #address-cells = <1>;
836 #size-cells = <0>;
837
838 hdmi_in: port@0 {
839 reg = <0>;
840
841 hdmi_in_tcon0: endpoint {
842 remote-endpoint = <&tcon0_out_hdmi>;
843 };
844 };
845
846 hdmi_out: port@1 {
847 reg = <1>;
848 };
849 };
850 };
851
852 hdmi_phy: hdmi-phy@1ef0000 {
853 compatible = "allwinner,sun8i-h3-hdmi-phy";
854 reg = <0x01ef0000 0x10000>;
855 clocks = <&ccu CLK_BUS_HDMI>, <&ccu CLK_HDMI_DDC>,
Chen-Yu Tsaib5fe5232020-01-12 23:36:13 +0800856 <&ccu CLK_PLL_VIDEO>;
Andre Przywara7514ed32018-07-04 14:16:36 +0100857 clock-names = "bus", "mod", "pll-0";
858 resets = <&ccu RST_BUS_HDMI0>;
859 reset-names = "phy";
860 #phy-cells = <0>;
861 };
862
863 rtc: rtc@1f00000 {
Chen-Yu Tsaib5fe5232020-01-12 23:36:13 +0800864 /* compatible is in per SoC .dtsi file */
865 reg = <0x01f00000 0x400>;
Andre Przywara7514ed32018-07-04 14:16:36 +0100866 interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>,
867 <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
Chen-Yu Tsaib5fe5232020-01-12 23:36:13 +0800868 clock-output-names = "osc32k", "osc32k-out", "iosc";
869 clocks = <&osc32k>;
870 #clock-cells = <1>;
Andre Przywara7514ed32018-07-04 14:16:36 +0100871 };
872
Samuel Holland2c597852022-04-27 15:31:27 -0500873 r_intc: interrupt-controller@1f00c00 {
874 compatible = "allwinner,sun8i-h3-r-intc",
875 "allwinner,sun6i-a31-r-intc";
876 interrupt-controller;
877 #interrupt-cells = <3>;
878 reg = <0x01f00c00 0x400>;
879 interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
880 };
881
Andre Przywara7514ed32018-07-04 14:16:36 +0100882 r_ccu: clock@1f01400 {
883 compatible = "allwinner,sun8i-h3-r-ccu";
884 reg = <0x01f01400 0x100>;
Andre Przywaraceda40a2022-09-13 00:52:52 +0100885 clocks = <&osc24M>, <&rtc CLK_OSC32K>, <&rtc CLK_IOSC>,
Chen-Yu Tsaib5fe5232020-01-12 23:36:13 +0800886 <&ccu CLK_PLL_PERIPH0>;
Andre Przywara7514ed32018-07-04 14:16:36 +0100887 clock-names = "hosc", "losc", "iosc", "pll-periph";
888 #clock-cells = <1>;
889 #reset-cells = <1>;
890 };
891
892 codec_analog: codec-analog@1f015c0 {
893 compatible = "allwinner,sun8i-h3-codec-analog";
894 reg = <0x01f015c0 0x4>;
895 };
896
897 ir: ir@1f02000 {
Chen-Yu Tsaib5fe5232020-01-12 23:36:13 +0800898 compatible = "allwinner,sun6i-a31-ir";
Andre Przywara7514ed32018-07-04 14:16:36 +0100899 clocks = <&r_ccu CLK_APB0_IR>, <&r_ccu CLK_IR>;
900 clock-names = "apb", "ir";
901 resets = <&r_ccu RST_APB0_IR>;
902 interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
Chen-Yu Tsaib5fe5232020-01-12 23:36:13 +0800903 reg = <0x01f02000 0x400>;
Andre Przywara7514ed32018-07-04 14:16:36 +0100904 status = "disabled";
905 };
906
907 r_i2c: i2c@1f02400 {
908 compatible = "allwinner,sun6i-a31-i2c";
909 reg = <0x01f02400 0x400>;
910 interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
911 pinctrl-names = "default";
912 pinctrl-0 = <&r_i2c_pins>;
913 clocks = <&r_ccu CLK_APB0_I2C>;
914 resets = <&r_ccu RST_APB0_I2C>;
915 status = "disabled";
916 #address-cells = <1>;
917 #size-cells = <0>;
918 };
919
Samuel Holland2c597852022-04-27 15:31:27 -0500920 r_uart: serial@1f02800 {
921 compatible = "snps,dw-apb-uart";
922 reg = <0x01f02800 0x400>;
923 interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
924 reg-shift = <2>;
925 reg-io-width = <4>;
926 clocks = <&r_ccu CLK_APB0_UART>;
927 resets = <&r_ccu RST_APB0_UART>;
928 pinctrl-names = "default";
929 pinctrl-0 = <&r_uart_pins>;
930 status = "disabled";
931 };
932
Andre Przywara7514ed32018-07-04 14:16:36 +0100933 r_pio: pinctrl@1f02c00 {
934 compatible = "allwinner,sun8i-h3-r-pinctrl";
935 reg = <0x01f02c00 0x400>;
936 interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
Andre Przywaraceda40a2022-09-13 00:52:52 +0100937 clocks = <&r_ccu CLK_APB0_PIO>, <&osc24M>,
938 <&rtc CLK_OSC32K>;
Andre Przywara7514ed32018-07-04 14:16:36 +0100939 clock-names = "apb", "hosc", "losc";
940 gpio-controller;
941 #gpio-cells = <3>;
942 interrupt-controller;
943 #interrupt-cells = <3>;
944
Chen-Yu Tsaib5fe5232020-01-12 23:36:13 +0800945 r_ir_rx_pin: r-ir-rx-pin {
Andre Przywara7514ed32018-07-04 14:16:36 +0100946 pins = "PL11";
947 function = "s_cir_rx";
948 };
949
Chen-Yu Tsaib5fe5232020-01-12 23:36:13 +0800950 r_i2c_pins: r-i2c-pins {
Andre Przywara7514ed32018-07-04 14:16:36 +0100951 pins = "PL0", "PL1";
952 function = "s_i2c";
953 };
Andre Przywara58f68612021-05-25 01:20:25 +0100954
955 r_pwm_pin: r-pwm-pin {
956 pins = "PL10";
957 function = "s_pwm";
958 };
Samuel Holland2c597852022-04-27 15:31:27 -0500959
960 r_uart_pins: r-uart-pins {
961 pins = "PL2", "PL3";
962 function = "s_uart";
963 };
Andre Przywara58f68612021-05-25 01:20:25 +0100964 };
965
966 r_pwm: pwm@1f03800 {
967 compatible = "allwinner,sun8i-h3-pwm";
968 reg = <0x01f03800 0x8>;
969 pinctrl-names = "default";
970 pinctrl-0 = <&r_pwm_pin>;
971 clocks = <&osc24M>;
972 #pwm-cells = <3>;
973 status = "disabled";
Andre Przywara7514ed32018-07-04 14:16:36 +0100974 };
975 };
976};