blob: ce81046e7370e3a2203f982a456cbec1826e1256 [file] [log] [blame]
wdenk3bac3512003-03-12 10:41:04 +00001/*
2**=====================================================================
3**
4** Copyright (C) 2000, 2001, 2002, 2003
5** The LEOX team <team@leox.org>, http://www.leox.org
6**
7** LEOX.org is about the development of free hardware and software resources
8** for system on chip.
9**
10** Description: U-Boot port on the LEOX's ELPT860 CPU board
11** ~~~~~~~~~~~
12**
13**=====================================================================
14**
Wolfgang Denk1a459662013-07-08 09:37:19 +020015 * SPDX-License-Identifier: GPL-2.0+
wdenk3bac3512003-03-12 10:41:04 +000016**
17**=====================================================================
18*/
19
20OUTPUT_ARCH(powerpc)
wdenk3bac3512003-03-12 10:41:04 +000021/* Do we need any of these for elf?
22 __DYNAMIC = 0; */
23SECTIONS
24{
25 /* Read-only sections, merged into text segment: */
26 . = + SIZEOF_HEADERS;
27 .interp : { *(.interp) }
28 .hash : { *(.hash) }
29 .dynsym : { *(.dynsym) }
30 .dynstr : { *(.dynstr) }
31 .rel.text : { *(.rel.text) }
Wolfgang Denkdd520bf2006-11-30 18:02:20 +010032 .rela.text : { *(.rela.text) }
wdenk3bac3512003-03-12 10:41:04 +000033 .rel.data : { *(.rel.data) }
Wolfgang Denkdd520bf2006-11-30 18:02:20 +010034 .rela.data : { *(.rela.data) }
35 .rel.rodata : { *(.rel.rodata) }
36 .rela.rodata : { *(.rela.rodata) }
wdenk3bac3512003-03-12 10:41:04 +000037 .rel.got : { *(.rel.got) }
38 .rela.got : { *(.rela.got) }
39 .rel.ctors : { *(.rel.ctors) }
40 .rela.ctors : { *(.rela.ctors) }
41 .rel.dtors : { *(.rel.dtors) }
42 .rela.dtors : { *(.rela.dtors) }
43 .rel.bss : { *(.rel.bss) }
44 .rela.bss : { *(.rela.bss) }
45 .rel.plt : { *(.rel.plt) }
46 .rela.plt : { *(.rela.plt) }
47 .init : { *(.init) }
48 .plt : { *(.plt) }
49 .text :
50 {
51 /* WARNING - the following is hand-optimized to fit within */
52 /* the sector layout of our flash chips! XXX FIXME XXX */
53
Stefan Roesea47a12b2010-04-15 16:07:28 +020054 arch/powerpc/cpu/mpc8xx/start.o (.text)
wdenk3bac3512003-03-12 10:41:04 +000055 common/dlmalloc.o (.text)
Peter Tyser78acc472010-04-12 22:28:05 -050056 lib/vsprintf.o (.text)
57 lib/crc32.o (.text)
wdenk3bac3512003-03-12 10:41:04 +000058
59 . = env_offset;
Jean-Christophe PLAGNIOL-VILLARD0cf4fd32008-09-10 22:48:01 +020060 common/env_embedded.o (.text)
wdenk3bac3512003-03-12 10:41:04 +000061
62 *(.text)
wdenk3bac3512003-03-12 10:41:04 +000063 *(.got1)
64 }
65 _etext = .;
66 PROVIDE (etext = .);
67 .rodata :
68 {
69 *(.rodata)
70 *(.rodata1)
Wolfgang Denk74812662005-12-12 16:06:05 +010071 *(.rodata.str1.4)
72 *(.eh_frame)
wdenk3bac3512003-03-12 10:41:04 +000073 }
74 .fini : { *(.fini) } =0
75 .ctors : { *(.ctors) }
76 .dtors : { *(.dtors) }
77
78 /* Read-write section, merged into data segment: */
79 . = (. + 0x0FFF) & 0xFFFFF000;
80 _erotext = .;
81 PROVIDE (erotext = .);
82 .reloc :
83 {
84 *(.got)
85 _GOT2_TABLE_ = .;
86 *(.got2)
87 _FIXUP_TABLE_ = .;
88 *(.fixup)
89 }
90 __got2_entries = (_FIXUP_TABLE_ - _GOT2_TABLE_) >>2;
91 __fixup_entries = (. - _FIXUP_TABLE_)>>2;
92
93 .data :
94 {
95 *(.data)
96 *(.data1)
97 *(.sdata)
98 *(.sdata2)
99 *(.dynamic)
100 CONSTRUCTORS
101 }
102 _edata = .;
103 PROVIDE (edata = .);
104
105 __start___ex_table = .;
106 __ex_table : { *(__ex_table) }
107 __stop___ex_table = .;
108
109 . = ALIGN(4096);
110 __init_begin = .;
111 .text.init : { *(.text.init) }
112 .data.init : { *(.data.init) }
113 . = ALIGN(4096);
114 __init_end = .;
115
116 __bss_start = .;
117 .bss :
118 {
119 *(.sbss) *(.scommon)
120 *(.dynbss)
121 *(.bss)
122 *(COMMON)
123 }
Albert ARIBAUD59930532013-03-30 00:19:53 +0000124 __bss_end = . ;
wdenk3bac3512003-03-12 10:41:04 +0000125 PROVIDE (end = .);
126}