blob: 596071f9b358383d0df52e6742e26be627240027 [file] [log] [blame]
Luka Perkove5841e12012-04-17 09:22:17 +00001#
2# Copyright (C) 2011-2012
3# Gerald Kerma <dreagle@doukki.net>
4# Simon Baatz <gmbnomis@gmail.com>
Luka Perkov3fdf7592012-12-03 03:24:15 +00005# Luka Perkov <luka@openwrt.org>
Luka Perkove5841e12012-04-17 09:22:17 +00006#
Wolfgang Denk1a459662013-07-08 09:37:19 +02007# SPDX-License-Identifier: GPL-2.0+
Luka Perkove5841e12012-04-17 09:22:17 +00008#
Anatolij Gustschinb1e6c4c2013-04-30 11:15:33 +00009# Refer doc/README.kwbimage for more details about how-to configure
Luka Perkove5841e12012-04-17 09:22:17 +000010# and create kirkwood boot image
11#
12
13# Boot Media configurations
14BOOT_FROM nand # change from nand to uart if building UART image
15NAND_ECC_MODE default
16NAND_PAGE_SIZE 0x0800
17
18# SOC registers configuration using bootrom header extension
19# Maximum KWBIMAGE_MAX_CONFIG configurations allowed
20
21# Configure RGMII-0 interface pad voltage to 1.8V
22DATA 0xffd100e0 0x1b1b1b9b
23
24#Dram initalization for SINGLE x16 CL=5 @ 400MHz
25DATA 0xffd01400 0x43000c30 # DDR Configuration register
26# bit13-0: 0xc30, (3120 DDR2 clks refresh rate)
27# bit23-14: 0x0,
28# bit24: 0x1, enable exit self refresh mode on DDR access
29# bit25: 0x1, required
30# bit29-26: 0x0,
31# bit31-30: 0x1,
32
33DATA 0xffd01404 0x37543000 # DDR Controller Control Low
34# bit4: 0x0, addr/cmd in smame cycle
35# bit5: 0x0, clk is driven during self refresh, we don't care for APX
36# bit6: 0x0, use recommended falling edge of clk for addr/cmd
37# bit14: 0x0, input buffer always powered up
38# bit18: 0x1, cpu lock transaction enabled
39# bit23-20: 0x5, recommended value for CL=5 and STARTBURST_DEL disabled bit31=0
40# bit27-24: 0x7, CL+2, STARTBURST sample stages, for freqs 400MHz, unbuffered DIMM
41# bit30-28: 0x3, required
42# bit31: 0x0, no additional STARTBURST delay
43
44DATA 0xffd01408 0x22125451 # DDR Timing (Low) (active cycles value +1)
45# bit3-0: TRAS lsbs
46# bit7-4: TRCD
47# bit11-8: TRP
48# bit15-12: TWR
49# bit19-16: TWTR
50# bit20: TRAS msb
51# bit23-21: 0x0
52# bit27-24: TRRD
53# bit31-28: TRTP
54
55DATA 0xffd0140c 0x00000a33 # DDR Timing (High)
56# bit6-0: TRFC
57# bit8-7: TR2R
58# bit10-9: TR2W
59# bit12-11: TW2W
60# bit31-13: 0x0, required
61
62DATA 0xffd01410 0x0000000c # DDR Address Control
63# bit1-0: 00, Cs0width (x8)
64# bit3-2: 11, Cs0size (1Gb)
65# bit5-4: 00, Cs1width (x8)
66# bit7-6: 11, Cs1size (1Gb)
67# bit9-8: 00, Cs2width (nonexistent
68# bit11-10: 00, Cs2size (nonexistent
69# bit13-12: 00, Cs3width (nonexistent
70# bit15-14: 00, Cs3size (nonexistent
71# bit16: 0, Cs0AddrSel
72# bit17: 0, Cs1AddrSel
73# bit18: 0, Cs2AddrSel
74# bit19: 0, Cs3AddrSel
75# bit31-20: 0x0, required
76
77DATA 0xffd01414 0x00000000 # DDR Open Pages Control
78# bit0: 0, OpenPage enabled
79# bit31-1: 0x0, required
80
81DATA 0xffd01418 0x00000000 # DDR Operation
82# bit3-0: 0x0, DDR cmd
83# bit31-4: 0x0, required
84
85DATA 0xffd0141c 0x00000c52 # DDR Mode
86# bit2-0: 0x2, BurstLen=2 required
87# bit3: 0x0, BurstType=0 required
88# bit6-4: 0x4, CL=5
89# bit7: 0x0, TestMode=0 normal
90# bit8: 0x0, DLL reset=0 normal
91# bit11-9: 0x6, auto-precharge write recovery ????????????
92# bit12: 0x0, PD must be zero
93# bit31-13: 0x0, required
94
95DATA 0xffd01420 0x00000040 # DDR Extended Mode
96# bit0: 0, DDR DLL enabled
97# bit1: 0, DDR drive strenght normal
98# bit2: 1, DDR ODT control lsd (disabled)
99# bit5-3: 0x0, required
100# bit6: 0, DDR ODT control msb, (disabled)
101# bit9-7: 0x0, required
102# bit10: 0, differential DQS enabled
103# bit11: 0, required
104# bit12: 0, DDR output buffer enabled
105# bit31-13: 0x0, required
106
107DATA 0xffd01424 0x0000f17f # DDR Controller Control High
108# bit2-0: 0x7, required
109# bit3: 0x1, MBUS Burst Chop disabled
110# bit6-4: 0x7, required
111# bit7: 0x0,
112# bit8: 0x1, add writepath sample stage, must be 1 for DDR freq >= 300MHz
113# bit9: 0x0, no half clock cycle addition to dataout
114# bit10: 0x0, 1/4 clock cycle skew enabled for addr/ctl signals
115# bit11: 0x0, 1/4 clock cycle skew disabled for write mesh
116# bit15-12: 0xf, required
117# bit31-16: 0, required
118
119DATA 0xffd01428 0x00085520 # DDR2 ODT Read Timing (default values)
120DATA 0xffd0147c 0x00008552 # DDR2 ODT Write Timing (default values)
121
122DATA 0xffd01500 0x00000000 # CS[0]n Base address to 0x0
123DATA 0xffd01504 0x0ffffff1 # CS[0]n Size
124# bit0: 0x1, Window enabled
125# bit1: 0x0, Write Protect disabled
126# bit3-2: 0x0, CS0 hit selected
127# bit23-4: 0xfffff, required
128# bit31-24: 0x0f, Size (i.e. 256MB)
129
130DATA 0xffd01508 0x10000000 # CS[1]n Base address to 256Mb
131DATA 0xffd0150c 0x00000000 # CS[1]n Size, window disabled
132
133DATA 0xffd01514 0x00000000 # CS[2]n Size, window disabled
134DATA 0xffd0151c 0x00000000 # CS[3]n Size, window disabled
135
136DATA 0xffd01494 0x00030000 # DDR ODT Control (Low)
137# bit3-0: ODT0Rd, MODT[0] asserted during read from DRAM CS1
138# bit7-4: ODT0Rd, MODT[0] asserted during read from DRAM CS0
139# bit19-16:2, ODT0Wr, MODT[0] asserted during write to DRAM CS1
140# bit23-20:1, ODT0Wr, MODT[0] asserted during write to DRAM CS0
141
142DATA 0xffd01498 0x00000000 # DDR ODT Control (High)
143# bit1-0: 0x0, ODT0 controlled by ODT Control (low) register above
144# bit3-2: 0x1, ODT1 active NEVER!
145# bit31-4: 0x0, required
146
147DATA 0xffd0149c 0x0000e803 # CPU ODT Control
148DATA 0xffd01480 0x00000001 # DDR Initialization Control
149# bit0: 0x1, enable DDR init upon this register write
150
151DATA 0xFFD20134 0x66666666 # L2 RAM Timing 0 Register
152DATA 0xFFD20138 0x66666666 # L2 RAM Timing 1 Register
153
154# End of Header extension
155DATA 0x0 0x0