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Troy Kiskyf8f9f792019-07-29 12:15:54 -07001// SPDX-License-Identifier: GPL-2.0+
2//
3// Copyright 2013-2019 Boundary Devices, Inc.
4// Copyright 2012 Freescale Semiconductor, Inc.
5// Copyright 2011 Linaro Ltd.
6
7#include <dt-bindings/clock/imx6qdl-clock.h>
8#include <dt-bindings/gpio/gpio.h>
9#include <dt-bindings/input/input.h>
10
Troy Kiskyf8f9f792019-07-29 12:15:54 -070011/ {
Troy Kiskyf8f9f792019-07-29 12:15:54 -070012 chosen {
13 stdout-path = &uart2;
14 };
15
Marcel Ziswilerd0399a42022-07-21 15:27:26 +020016 memory@10000000 {
17 device_type = "memory";
Troy Kiskyf8f9f792019-07-29 12:15:54 -070018 reg = <0x10000000 0x40000000>;
19 };
20
Marcel Ziswilerd0399a42022-07-21 15:27:26 +020021 regulators {
22 compatible = "simple-bus";
23 #address-cells = <1>;
24 #size-cells = <0>;
25
26 reg_2p5v: regulator@0 {
27 compatible = "regulator-fixed";
28 reg = <0>;
29 regulator-name = "2P5V";
30 regulator-min-microvolt = <2500000>;
31 regulator-max-microvolt = <2500000>;
32 regulator-always-on;
33 };
34
35 reg_3p3v: regulator@1 {
36 compatible = "regulator-fixed";
37 reg = <1>;
38 regulator-name = "3P3V";
39 regulator-min-microvolt = <3300000>;
40 regulator-max-microvolt = <3300000>;
41 regulator-always-on;
42 };
43
44 reg_usb_otg_vbus: regulator@2 {
45 compatible = "regulator-fixed";
46 reg = <2>;
47 regulator-name = "usb_otg_vbus";
48 regulator-min-microvolt = <5000000>;
49 regulator-max-microvolt = <5000000>;
50 gpio = <&gpio3 22 0>;
51 enable-active-high;
52 };
53
54 reg_can_xcvr: regulator@3 {
55 compatible = "regulator-fixed";
56 reg = <3>;
57 regulator-name = "CAN XCVR";
58 regulator-min-microvolt = <3300000>;
59 regulator-max-microvolt = <3300000>;
60 pinctrl-names = "default";
61 pinctrl-0 = <&pinctrl_can_xcvr>;
62 gpio = <&gpio1 2 GPIO_ACTIVE_LOW>;
63 };
64
65 reg_1p5v: regulator@4 {
66 compatible = "regulator-fixed";
67 reg = <4>;
68 regulator-name = "1P5V";
69 regulator-min-microvolt = <1500000>;
70 regulator-max-microvolt = <1500000>;
71 regulator-always-on;
72 };
73
74 reg_1p8v: regulator@5 {
75 compatible = "regulator-fixed";
76 reg = <5>;
77 regulator-name = "1P8V";
78 regulator-min-microvolt = <1800000>;
79 regulator-max-microvolt = <1800000>;
80 regulator-always-on;
81 };
82
83 reg_2p8v: regulator@6 {
84 compatible = "regulator-fixed";
85 reg = <6>;
86 regulator-name = "2P8V";
87 regulator-min-microvolt = <2800000>;
88 regulator-max-microvolt = <2800000>;
89 regulator-always-on;
90 };
91
92 reg_usb_h1_vbus: regulator@7 {
93 compatible = "regulator-fixed";
94 reg = <7>;
95 pinctrl-names = "default";
96 pinctrl-0 = <&pinctrl_usbh1>;
97 regulator-name = "usb_h1_vbus";
98 regulator-min-microvolt = <3300000>;
99 regulator-max-microvolt = <3300000>;
100 gpio = <&gpio7 12 GPIO_ACTIVE_HIGH>;
101 enable-active-high;
102 };
Troy Kiskyf8f9f792019-07-29 12:15:54 -0700103 };
104
Marcel Ziswilerd0399a42022-07-21 15:27:26 +0200105 mipi_xclk: mipi_xclk {
106 compatible = "pwm-clock";
107 #clock-cells = <0>;
108 clock-frequency = <22000000>;
109 clock-output-names = "mipi_pwm3";
110 pwms = <&pwm3 0 45>; /* 1 / 45 ns = 22 MHz */
111 status = "okay";
112 };
113
114 gpio-keys {
115 compatible = "gpio-keys";
116 pinctrl-names = "default";
117 pinctrl-0 = <&pinctrl_gpio_keys>;
118
119 power {
120 label = "Power Button";
121 gpios = <&gpio2 3 GPIO_ACTIVE_LOW>;
122 linux,code = <KEY_POWER>;
123 wakeup-source;
124 };
125
126 menu {
127 label = "Menu";
128 gpios = <&gpio2 1 GPIO_ACTIVE_LOW>;
129 linux,code = <KEY_MENU>;
130 };
131
132 home {
133 label = "Home";
134 gpios = <&gpio2 4 GPIO_ACTIVE_LOW>;
135 linux,code = <KEY_HOME>;
136 };
137
138 back {
139 label = "Back";
140 gpios = <&gpio2 2 GPIO_ACTIVE_LOW>;
141 linux,code = <KEY_BACK>;
142 };
143
144 volume-up {
145 label = "Volume Up";
146 gpios = <&gpio7 13 GPIO_ACTIVE_LOW>;
147 linux,code = <KEY_VOLUMEUP>;
148 };
149
150 volume-down {
151 label = "Volume Down";
152 gpios = <&gpio4 5 GPIO_ACTIVE_LOW>;
153 linux,code = <KEY_VOLUMEDOWN>;
154 };
155 };
156
157 sound {
158 compatible = "fsl,imx6q-sabrelite-sgtl5000",
159 "fsl,imx-audio-sgtl5000";
160 model = "imx6q-sabrelite-sgtl5000";
161 ssi-controller = <&ssi1>;
162 audio-codec = <&codec>;
163 audio-routing =
164 "MIC_IN", "Mic Jack",
165 "Mic Jack", "Mic Bias",
166 "Headphone Jack", "HP_OUT";
167 mux-int-port = <1>;
168 mux-ext-port = <4>;
169 };
170
171 backlight_lcd: backlight-lcd {
172 compatible = "pwm-backlight";
173 pwms = <&pwm1 0 5000000>;
174 brightness-levels = <0 4 8 16 32 64 128 255>;
175 default-brightness-level = <7>;
176 power-supply = <&reg_3p3v>;
177 status = "okay";
178 };
179
180 backlight_lvds: backlight-lvds {
181 compatible = "pwm-backlight";
182 pwms = <&pwm4 0 5000000>;
183 brightness-levels = <0 4 8 16 32 64 128 255>;
184 default-brightness-level = <7>;
185 power-supply = <&reg_3p3v>;
186 status = "okay";
187 };
188
189 lcd_display: disp0 {
190 compatible = "fsl,imx-parallel-display";
191 #address-cells = <1>;
192 #size-cells = <0>;
193 interface-pix-fmt = "bgr666";
194 pinctrl-names = "default";
195 pinctrl-0 = <&pinctrl_j15>;
196 status = "okay";
197
198 port@0 {
199 reg = <0>;
200
201 lcd_display_in: endpoint {
202 remote-endpoint = <&ipu1_di0_disp0>;
203 };
204 };
205
206 port@1 {
207 reg = <1>;
208
209 lcd_display_out: endpoint {
210 remote-endpoint = <&lcd_panel_in>;
211 };
212 };
213 };
214
215 panel-lcd {
216 compatible = "okaya,rs800480t-7x0gp";
217 backlight = <&backlight_lcd>;
218
219 port {
220 lcd_panel_in: endpoint {
221 remote-endpoint = <&lcd_display_out>;
222 };
223 };
224 };
225
226 panel-lvds0 {
227 compatible = "hannstar,hsd100pxn1";
228 backlight = <&backlight_lvds>;
229
230 port {
231 panel_in: endpoint {
232 remote-endpoint = <&lvds0_out>;
233 };
234 };
Troy Kiskyf8f9f792019-07-29 12:15:54 -0700235 };
236};
237
Marcel Ziswilerd0399a42022-07-21 15:27:26 +0200238&ipu1_csi0_from_ipu1_csi0_mux {
239 bus-width = <8>;
240 data-shift = <12>; /* Lines 19:12 used */
241 hsync-active = <1>;
242 vync-active = <1>;
243};
244
245&ipu1_csi0_mux_from_parallel_sensor {
246 remote-endpoint = <&ov5642_to_ipu1_csi0_mux>;
247};
248
249&ipu1_csi0 {
250 pinctrl-names = "default";
251 pinctrl-0 = <&pinctrl_ipu1_csi0>;
252};
253
254&audmux {
255 pinctrl-names = "default";
256 pinctrl-0 = <&pinctrl_audmux>;
257 status = "okay";
258};
259
260&can1 {
261 pinctrl-names = "default";
262 pinctrl-0 = <&pinctrl_can1>;
263 xceiver-supply = <&reg_can_xcvr>;
264 status = "okay";
265};
266
267&clks {
268 assigned-clocks = <&clks IMX6QDL_CLK_LDB_DI0_SEL>,
269 <&clks IMX6QDL_CLK_LDB_DI1_SEL>;
270 assigned-clock-parents = <&clks IMX6QDL_CLK_PLL3_USB_OTG>,
271 <&clks IMX6QDL_CLK_PLL3_USB_OTG>;
272};
273
Troy Kiskyf8f9f792019-07-29 12:15:54 -0700274&ecspi1 {
Marcel Ziswilerd0399a42022-07-21 15:27:26 +0200275 cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
Troy Kiskyf8f9f792019-07-29 12:15:54 -0700276 pinctrl-names = "default";
277 pinctrl-0 = <&pinctrl_ecspi1>;
278 status = "okay";
279
Marcel Ziswilerd0399a42022-07-21 15:27:26 +0200280 flash: flash@0 {
Troy Kiskyf8f9f792019-07-29 12:15:54 -0700281 compatible = "sst,sst25vf016b", "jedec,spi-nor";
282 spi-max-frequency = <20000000>;
283 reg = <0>;
Troy Kiskyf8f9f792019-07-29 12:15:54 -0700284 };
285};
286
287&fec {
Troy Kiskyf8f9f792019-07-29 12:15:54 -0700288 pinctrl-names = "default";
289 pinctrl-0 = <&pinctrl_enet>;
Marcel Ziswilerd0399a42022-07-21 15:27:26 +0200290 phy-mode = "rgmii";
291 phy-handle = <&ethphy>;
292 phy-reset-gpios = <&gpio3 23 GPIO_ACTIVE_LOW>;
Troy Kiskyf8f9f792019-07-29 12:15:54 -0700293 status = "okay";
Troy Kiskyf8f9f792019-07-29 12:15:54 -0700294
295 mdio {
Marcel Ziswilerd0399a42022-07-21 15:27:26 +0200296 #address-cells = <1>;
297 #size-cells = <0>;
Troy Kiskyf8f9f792019-07-29 12:15:54 -0700298
299 ethphy: ethernet-phy {
Marcel Ziswilerd0399a42022-07-21 15:27:26 +0200300 compatible = "ethernet-phy-ieee802.3-c22";
301 txen-skew-ps = <0>;
302 txc-skew-ps = <3000>;
303 rxdv-skew-ps = <0>;
304 rxc-skew-ps = <3000>;
305 rxd0-skew-ps = <0>;
306 rxd1-skew-ps = <0>;
307 rxd2-skew-ps = <0>;
308 rxd3-skew-ps = <0>;
309 txd0-skew-ps = <0>;
310 txd1-skew-ps = <0>;
311 txd2-skew-ps = <0>;
312 txd3-skew-ps = <0>;
Troy Kiskyf8f9f792019-07-29 12:15:54 -0700313 };
314 };
315};
316
Marcel Ziswilerd0399a42022-07-21 15:27:26 +0200317&hdmi {
318 ddc-i2c-bus = <&i2c2>;
319 status = "okay";
320};
321
Troy Kiskyf8f9f792019-07-29 12:15:54 -0700322&i2c1 {
323 clock-frequency = <100000>;
Marcel Ziswilerd0399a42022-07-21 15:27:26 +0200324 pinctrl-names = "default";
Troy Kiskyf8f9f792019-07-29 12:15:54 -0700325 pinctrl-0 = <&pinctrl_i2c1>;
Troy Kiskyf8f9f792019-07-29 12:15:54 -0700326 status = "okay";
Marcel Ziswilerd0399a42022-07-21 15:27:26 +0200327
328 codec: sgtl5000@a {
329 compatible = "fsl,sgtl5000";
330 reg = <0x0a>;
331 clocks = <&clks IMX6QDL_CLK_CKO>;
332 VDDA-supply = <&reg_2p5v>;
333 VDDIO-supply = <&reg_3p3v>;
334 };
Troy Kiskyf8f9f792019-07-29 12:15:54 -0700335};
336
337&i2c2 {
338 clock-frequency = <100000>;
Marcel Ziswilerd0399a42022-07-21 15:27:26 +0200339 pinctrl-names = "default";
Troy Kiskyf8f9f792019-07-29 12:15:54 -0700340 pinctrl-0 = <&pinctrl_i2c2>;
Troy Kiskyf8f9f792019-07-29 12:15:54 -0700341 status = "okay";
342
Marcel Ziswilerd0399a42022-07-21 15:27:26 +0200343 ov5640: camera@40 {
344 compatible = "ovti,ov5640";
345 pinctrl-names = "default";
346 pinctrl-0 = <&pinctrl_ov5640>;
347 reg = <0x40>;
348 clocks = <&mipi_xclk>;
349 clock-names = "xclk";
350 DOVDD-supply = <&reg_1p8v>;
351 AVDD-supply = <&reg_2p8v>;
352 DVDD-supply = <&reg_1p5v>;
353 reset-gpios = <&gpio2 5 GPIO_ACTIVE_LOW>; /* NANDF_D5 */
354 powerdown-gpios = <&gpio6 9 GPIO_ACTIVE_HIGH>; /* NANDF_WP_B */
355
356 port {
357 ov5640_to_mipi_csi2: endpoint {
358 remote-endpoint = <&mipi_csi2_in>;
359 clock-lanes = <0>;
360 data-lanes = <1 2>;
361 };
362 };
363 };
364
365 ov5642: camera@42 {
366 compatible = "ovti,ov5642";
367 pinctrl-names = "default";
368 pinctrl-0 = <&pinctrl_ov5642>;
369 clocks = <&clks IMX6QDL_CLK_CKO2>;
370 clock-names = "xclk";
371 reg = <0x42>;
372 reset-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>;
373 powerdown-gpios = <&gpio1 6 GPIO_ACTIVE_HIGH>;
374 gp-gpios = <&gpio1 16 GPIO_ACTIVE_HIGH>;
375 status = "disabled";
376
377 port {
378 ov5642_to_ipu1_csi0_mux: endpoint {
379 remote-endpoint = <&ipu1_csi0_mux_from_parallel_sensor>;
380 bus-width = <8>;
381 hsync-active = <1>;
382 vsync-active = <1>;
383 };
384 };
Troy Kiskyf8f9f792019-07-29 12:15:54 -0700385 };
386};
387
388&i2c3 {
389 clock-frequency = <100000>;
Marcel Ziswilerd0399a42022-07-21 15:27:26 +0200390 pinctrl-names = "default";
Troy Kiskyf8f9f792019-07-29 12:15:54 -0700391 pinctrl-0 = <&pinctrl_i2c3>;
Troy Kiskyf8f9f792019-07-29 12:15:54 -0700392 status = "okay";
393};
394
Marcel Ziswilerd0399a42022-07-21 15:27:26 +0200395&iomuxc {
396 pinctrl-names = "default";
397 pinctrl-0 = <&pinctrl_hog>;
398
399 imx6q-sabrelite {
400 pinctrl_hog: hoggrp {
401 fsl,pins = <
402 /* SGTL5000 sys_mclk */
403 MX6QDL_PAD_GPIO_0__CCM_CLKO1 0x030b0
404 >;
405 };
406
407 pinctrl_audmux: audmuxgrp {
408 fsl,pins = <
409 MX6QDL_PAD_SD2_DAT0__AUD4_RXD 0x130b0
410 MX6QDL_PAD_SD2_DAT3__AUD4_TXC 0x130b0
411 MX6QDL_PAD_SD2_DAT2__AUD4_TXD 0x110b0
412 MX6QDL_PAD_SD2_DAT1__AUD4_TXFS 0x130b0
413 >;
414 };
415
416 pinctrl_can1: can1grp {
417 fsl,pins = <
418 MX6QDL_PAD_KEY_COL2__FLEXCAN1_TX 0x1b0b0
419 MX6QDL_PAD_KEY_ROW2__FLEXCAN1_RX 0x1b0b0
420 >;
421 };
422
423 pinctrl_can_xcvr: can-xcvrgrp {
424 fsl,pins = <
425 /* Flexcan XCVR enable */
426 MX6QDL_PAD_GPIO_2__GPIO1_IO02 0x1b0b0
427 >;
428 };
429
430 pinctrl_ecspi1: ecspi1grp {
431 fsl,pins = <
432 MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1
433 MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1
434 MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1
435 MX6QDL_PAD_EIM_D19__GPIO3_IO19 0x000b1 /* CS */
436 >;
437 };
438
439 pinctrl_enet: enetgrp {
440 fsl,pins = <
441 MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x100b0
442 MX6QDL_PAD_ENET_MDC__ENET_MDC 0x100b0
443 MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x10030
444 MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x10030
445 MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x10030
446 MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x10030
447 MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x10030
448 MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x10030
449 MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x100b0
450 MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b030
451 MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b030
452 MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b030
453 MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b030
454 MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b030
455 MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b030
456 /* Phy reset */
457 MX6QDL_PAD_EIM_D23__GPIO3_IO23 0x000b0
458 >;
459 };
460
461 pinctrl_gpio_keys: gpio-keysgrp {
462 fsl,pins = <
463 /* Power Button */
464 MX6QDL_PAD_NANDF_D3__GPIO2_IO03 0x1b0b0
465 /* Menu Button */
466 MX6QDL_PAD_NANDF_D1__GPIO2_IO01 0x1b0b0
467 /* Home Button */
468 MX6QDL_PAD_NANDF_D4__GPIO2_IO04 0x1b0b0
469 /* Back Button */
470 MX6QDL_PAD_NANDF_D2__GPIO2_IO02 0x1b0b0
471 /* Volume Up Button */
472 MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0
473 /* Volume Down Button */
474 MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0
475 >;
476 };
477
478 pinctrl_i2c1: i2c1grp {
479 fsl,pins = <
480 MX6QDL_PAD_EIM_D21__I2C1_SCL 0x4001b8b1
481 MX6QDL_PAD_EIM_D28__I2C1_SDA 0x4001b8b1
482 >;
483 };
484
485 pinctrl_i2c2: i2c2grp {
486 fsl,pins = <
487 MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1
488 MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1
489 >;
490 };
491
492 pinctrl_i2c3: i2c3grp {
493 fsl,pins = <
494 MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1
495 MX6QDL_PAD_GPIO_16__I2C3_SDA 0x4001b8b1
496 >;
497 };
498
499 pinctrl_ipu1_csi0: ipu1csi0grp {
500 fsl,pins = <
501 MX6QDL_PAD_CSI0_DAT12__IPU1_CSI0_DATA12 0x1b0b0
502 MX6QDL_PAD_CSI0_DAT13__IPU1_CSI0_DATA13 0x1b0b0
503 MX6QDL_PAD_CSI0_DAT14__IPU1_CSI0_DATA14 0x1b0b0
504 MX6QDL_PAD_CSI0_DAT15__IPU1_CSI0_DATA15 0x1b0b0
505 MX6QDL_PAD_CSI0_DAT16__IPU1_CSI0_DATA16 0x1b0b0
506 MX6QDL_PAD_CSI0_DAT17__IPU1_CSI0_DATA17 0x1b0b0
507 MX6QDL_PAD_CSI0_DAT18__IPU1_CSI0_DATA18 0x1b0b0
508 MX6QDL_PAD_CSI0_DAT19__IPU1_CSI0_DATA19 0x1b0b0
509 MX6QDL_PAD_CSI0_PIXCLK__IPU1_CSI0_PIXCLK 0x1b0b0
510 MX6QDL_PAD_CSI0_MCLK__IPU1_CSI0_HSYNC 0x1b0b0
511 MX6QDL_PAD_CSI0_VSYNC__IPU1_CSI0_VSYNC 0x1b0b0
512 MX6QDL_PAD_CSI0_DATA_EN__IPU1_CSI0_DATA_EN 0x1b0b0
513 >;
514 };
515
516 pinctrl_j15: j15grp {
517 fsl,pins = <
518 MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x10
519 MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0x10
520 MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10
521 MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10
522 MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0x10
523 MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0x10
524 MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0x10
525 MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0x10
526 MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0x10
527 MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0x10
528 MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0x10
529 MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0x10
530 MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0x10
531 MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0x10
532 MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0x10
533 MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0x10
534 MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0x10
535 MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0x10
536 MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0x10
537 MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0x10
538 MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0x10
539 MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0x10
540 MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0x10
541 MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0x10
542 MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0x10
543 MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0x10
544 MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0x10
545 MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0x10
546 >;
547 };
548
549 pinctrl_ov5640: ov5640grp {
550 fsl,pins = <
551 MX6QDL_PAD_NANDF_D5__GPIO2_IO05 0x000b0
552 MX6QDL_PAD_NANDF_WP_B__GPIO6_IO09 0x0b0b0
553 >;
554 };
555
556 pinctrl_ov5642: ov5642grp {
557 fsl,pins = <
558 MX6QDL_PAD_SD1_DAT0__GPIO1_IO16 0x1b0b0
559 MX6QDL_PAD_GPIO_6__GPIO1_IO06 0x1b0b0
560 MX6QDL_PAD_GPIO_8__GPIO1_IO08 0x130b0
561 MX6QDL_PAD_GPIO_3__CCM_CLKO2 0x000b0
562 >;
563 };
564
565 pinctrl_pwm1: pwm1grp {
566 fsl,pins = <
567 MX6QDL_PAD_SD1_DAT3__PWM1_OUT 0x1b0b1
568 >;
569 };
570
571 pinctrl_pwm3: pwm3grp {
572 fsl,pins = <
573 MX6QDL_PAD_SD1_DAT1__PWM3_OUT 0x1b0b1
574 >;
575 };
576
577 pinctrl_pwm4: pwm4grp {
578 fsl,pins = <
579 MX6QDL_PAD_SD1_CMD__PWM4_OUT 0x1b0b1
580 >;
581 };
582
583 pinctrl_uart1: uart1grp {
584 fsl,pins = <
585 MX6QDL_PAD_SD3_DAT7__UART1_TX_DATA 0x1b0b1
586 MX6QDL_PAD_SD3_DAT6__UART1_RX_DATA 0x1b0b1
587 >;
588 };
589
590 pinctrl_uart2: uart2grp {
591 fsl,pins = <
592 MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1
593 MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1
594 >;
595 };
596
597 pinctrl_usbh1: usbh1grp {
598 fsl,pins = <
599 MX6QDL_PAD_GPIO_17__GPIO7_IO12 0x030b0
600 >;
601 };
602
603 pinctrl_usbotg: usbotggrp {
604 fsl,pins = <
605 MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059
606 MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0
607 /* power enable, high active */
608 MX6QDL_PAD_EIM_D22__GPIO3_IO22 0x000b0
609 >;
610 };
611
612 pinctrl_usdhc3: usdhc3grp {
613 fsl,pins = <
614 MX6QDL_PAD_SD3_CMD__SD3_CMD 0x17059
615 MX6QDL_PAD_SD3_CLK__SD3_CLK 0x10059
616 MX6QDL_PAD_SD3_DAT0__SD3_DATA0 0x17059
617 MX6QDL_PAD_SD3_DAT1__SD3_DATA1 0x17059
618 MX6QDL_PAD_SD3_DAT2__SD3_DATA2 0x17059
619 MX6QDL_PAD_SD3_DAT3__SD3_DATA3 0x17059
620 MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 /* CD */
621 MX6QDL_PAD_SD3_DAT4__GPIO7_IO01 0x1f0b0 /* WP */
622 >;
623 };
624
625 pinctrl_usdhc4: usdhc4grp {
626 fsl,pins = <
627 MX6QDL_PAD_SD4_CMD__SD4_CMD 0x17059
628 MX6QDL_PAD_SD4_CLK__SD4_CLK 0x10059
629 MX6QDL_PAD_SD4_DAT0__SD4_DATA0 0x17059
630 MX6QDL_PAD_SD4_DAT1__SD4_DATA1 0x17059
631 MX6QDL_PAD_SD4_DAT2__SD4_DATA2 0x17059
632 MX6QDL_PAD_SD4_DAT3__SD4_DATA3 0x17059
633 MX6QDL_PAD_NANDF_D6__GPIO2_IO06 0x1b0b0 /* CD */
634 >;
635 };
636 };
637};
638
639&ipu1_di0_disp0 {
640 remote-endpoint = <&lcd_display_in>;
641};
642
643&ldb {
644 status = "okay";
645
646 lvds-channel@0 {
647 status = "okay";
648
649 port@4 {
650 reg = <4>;
651
652 lvds0_out: endpoint {
653 remote-endpoint = <&panel_in>;
654 };
655 };
656 };
657};
658
Troy Kiskyf8f9f792019-07-29 12:15:54 -0700659&pcie {
660 status = "okay";
661};
662
663&pwm1 {
Marcel Ziswilerd0399a42022-07-21 15:27:26 +0200664 #pwm-cells = <2>;
Troy Kiskyf8f9f792019-07-29 12:15:54 -0700665 pinctrl-names = "default";
666 pinctrl-0 = <&pinctrl_pwm1>;
667 status = "okay";
668};
669
670&pwm3 {
Marcel Ziswilerd0399a42022-07-21 15:27:26 +0200671 #pwm-cells = <2>;
Troy Kiskyf8f9f792019-07-29 12:15:54 -0700672 pinctrl-names = "default";
673 pinctrl-0 = <&pinctrl_pwm3>;
674 status = "okay";
675};
676
677&pwm4 {
Marcel Ziswilerd0399a42022-07-21 15:27:26 +0200678 #pwm-cells = <2>;
Troy Kiskyf8f9f792019-07-29 12:15:54 -0700679 pinctrl-names = "default";
680 pinctrl-0 = <&pinctrl_pwm4>;
681 status = "okay";
682};
683
Marcel Ziswilerd0399a42022-07-21 15:27:26 +0200684&ssi1 {
685 status = "okay";
686};
687
Troy Kiskyf8f9f792019-07-29 12:15:54 -0700688&uart1 {
689 pinctrl-names = "default";
690 pinctrl-0 = <&pinctrl_uart1>;
691 status = "okay";
692};
693
694&uart2 {
695 pinctrl-names = "default";
696 pinctrl-0 = <&pinctrl_uart2>;
697 status = "okay";
698};
699
700&usbh1 {
Marcel Ziswilerd0399a42022-07-21 15:27:26 +0200701 vbus-supply = <&reg_usb_h1_vbus>;
Troy Kiskyf8f9f792019-07-29 12:15:54 -0700702 status = "okay";
703};
704
705&usbotg {
706 vbus-supply = <&reg_usb_otg_vbus>;
707 pinctrl-names = "default";
708 pinctrl-0 = <&pinctrl_usbotg>;
709 disable-over-current;
710 status = "okay";
711};
712
713&usdhc3 {
714 pinctrl-names = "default";
715 pinctrl-0 = <&pinctrl_usdhc3>;
Marcel Ziswilerd0399a42022-07-21 15:27:26 +0200716 cd-gpios = <&gpio7 0 GPIO_ACTIVE_LOW>;
717 wp-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
Troy Kiskyf8f9f792019-07-29 12:15:54 -0700718 vmmc-supply = <&reg_3p3v>;
719 status = "okay";
720};
721
722&usdhc4 {
723 pinctrl-names = "default";
724 pinctrl-0 = <&pinctrl_usdhc4>;
Marcel Ziswilerd0399a42022-07-21 15:27:26 +0200725 cd-gpios = <&gpio2 6 GPIO_ACTIVE_LOW>;
Troy Kiskyf8f9f792019-07-29 12:15:54 -0700726 vmmc-supply = <&reg_3p3v>;
727 status = "okay";
728};
Marcel Ziswilerd0399a42022-07-21 15:27:26 +0200729
730&mipi_csi {
731 status = "okay";
732
733 port@0 {
734 reg = <0>;
735
736 mipi_csi2_in: endpoint {
737 remote-endpoint = <&ov5640_to_mipi_csi2>;
738 clock-lanes = <0>;
739 data-lanes = <1 2>;
740 };
741 };
742};