blob: d9d04743ac81940a58270a684bbfc7eb8a0bf638 [file] [log] [blame]
Tom Rini4549e782018-05-06 18:27:01 -04001// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
Patrick Delaunay3d2d1152018-03-12 10:46:17 +01002/*
3 * Copyright : STMicroelectronics 2018
Patrick Delaunay3d2d1152018-03-12 10:46:17 +01004 */
5
6/ {
7 aliases {
8 gpio0 = &gpioa;
9 gpio1 = &gpiob;
10 gpio2 = &gpioc;
11 gpio3 = &gpiod;
12 gpio4 = &gpioe;
13 gpio5 = &gpiof;
14 gpio6 = &gpiog;
15 gpio7 = &gpioh;
16 gpio8 = &gpioi;
17 gpio9 = &gpioj;
18 gpio10 = &gpiok;
19 gpio25 = &gpioz;
Patrick Delaunay1258e462019-04-12 14:38:28 +020020 pinctrl0 = &pinctrl;
21 pinctrl1 = &pinctrl_z;
Patrick Delaunay3d2d1152018-03-12 10:46:17 +010022 };
23
Patrick Delaunay5564b4c2021-10-13 15:11:18 +020024 binman: binman {
25 multiple-images;
26 };
27
Patrick Delaunay35a54d42019-07-11 11:15:28 +020028 clocks {
Patrick Delaunay3d2d1152018-03-12 10:46:17 +010029 u-boot,dm-pre-reloc;
30 };
31
Patrick Delaunay67b76842019-07-30 19:16:15 +020032 /* need PSCI for sysreset during board_f */
33 psci {
34 u-boot,dm-pre-proper;
35 };
36
Patrick Delaunay35a54d42019-07-11 11:15:28 +020037 reboot {
Patrick Delaunay3d2d1152018-03-12 10:46:17 +010038 u-boot,dm-pre-reloc;
Patrick Delaunay500327e2020-07-06 13:26:53 +020039 compatible = "syscon-reboot";
40 regmap = <&rcc>;
41 offset = <0x404>;
42 mask = <0x1>;
Patrick Delaunay3d2d1152018-03-12 10:46:17 +010043 };
44
45 soc {
46 u-boot,dm-pre-reloc;
Marek Vasuta8c97f42020-04-22 13:18:13 +020047
48 ddr: ddr@5a003000 {
49 u-boot,dm-pre-reloc;
50
51 compatible = "st,stm32mp1-ddr";
52
Patrice Chotardb9a0cc82021-11-15 11:39:13 +010053 reg = <0x5a003000 0x550
54 0x5a004000 0x234>;
Marek Vasuta8c97f42020-04-22 13:18:13 +020055
56 clocks = <&rcc AXIDCG>,
57 <&rcc DDRC1>,
58 <&rcc DDRC2>,
59 <&rcc DDRPHYC>,
60 <&rcc DDRCAPB>,
61 <&rcc DDRPHYCAPB>;
62
63 clock-names = "axidcg",
64 "ddrc1",
65 "ddrc2",
66 "ddrphyc",
67 "ddrcapb",
68 "ddrphycapb";
69
70 status = "okay";
71 };
Patrick Delaunaye16750f2018-03-20 11:45:14 +010072 };
Patrick Delaunay3d2d1152018-03-12 10:46:17 +010073};
74
Patrick Delaunaybfe1f082019-02-27 17:01:27 +010075&bsec {
Patrick Delaunay95bd49a2020-05-25 12:19:41 +020076 u-boot,dm-pre-reloc;
Patrick Delaunay35a54d42019-07-11 11:15:28 +020077};
78
79&clk_csi {
Patrick Delaunaybfe1f082019-02-27 17:01:27 +010080 u-boot,dm-pre-reloc;
81};
82
Patrick Delaunay3d2d1152018-03-12 10:46:17 +010083&clk_hsi {
84 u-boot,dm-pre-reloc;
85};
86
87&clk_hse {
88 u-boot,dm-pre-reloc;
89};
90
Patrick Delaunay3d2d1152018-03-12 10:46:17 +010091&clk_lsi {
92 u-boot,dm-pre-reloc;
93};
94
Patrick Delaunay35a54d42019-07-11 11:15:28 +020095&clk_lse {
Patrick Delaunay3d2d1152018-03-12 10:46:17 +010096 u-boot,dm-pre-reloc;
97};
98
Patrick Delaunay4a87fea2020-05-25 12:19:48 +020099&cpu0_opp_table {
100 u-boot,dm-spl;
101 opp-650000000 {
102 u-boot,dm-spl;
103 };
104 opp-800000000 {
105 u-boot,dm-spl;
106 };
107};
108
Patrick Delaunay3d2d1152018-03-12 10:46:17 +0100109&gpioa {
Patrick Delaunay3d2d1152018-03-12 10:46:17 +0100110 u-boot,dm-pre-reloc;
111};
112
113&gpiob {
Patrick Delaunay3d2d1152018-03-12 10:46:17 +0100114 u-boot,dm-pre-reloc;
115};
116
117&gpioc {
Patrick Delaunay3d2d1152018-03-12 10:46:17 +0100118 u-boot,dm-pre-reloc;
119};
120
121&gpiod {
Patrick Delaunay3d2d1152018-03-12 10:46:17 +0100122 u-boot,dm-pre-reloc;
123};
124
125&gpioe {
Patrick Delaunay3d2d1152018-03-12 10:46:17 +0100126 u-boot,dm-pre-reloc;
127};
128
129&gpiof {
Patrick Delaunay3d2d1152018-03-12 10:46:17 +0100130 u-boot,dm-pre-reloc;
131};
132
133&gpiog {
Patrick Delaunay3d2d1152018-03-12 10:46:17 +0100134 u-boot,dm-pre-reloc;
135};
136
137&gpioh {
Patrick Delaunay3d2d1152018-03-12 10:46:17 +0100138 u-boot,dm-pre-reloc;
139};
140
141&gpioi {
Patrick Delaunay3d2d1152018-03-12 10:46:17 +0100142 u-boot,dm-pre-reloc;
143};
144
145&gpioj {
Patrick Delaunay3d2d1152018-03-12 10:46:17 +0100146 u-boot,dm-pre-reloc;
147};
148
149&gpiok {
Patrick Delaunay3d2d1152018-03-12 10:46:17 +0100150 u-boot,dm-pre-reloc;
151};
152
153&gpioz {
Patrick Delaunay3d2d1152018-03-12 10:46:17 +0100154 u-boot,dm-pre-reloc;
155};
Patrice Chotard75500a42019-04-30 17:26:21 +0200156
Patrick Delaunay6d923002019-07-30 19:16:14 +0200157&iwdg2 {
158 u-boot,dm-pre-reloc;
159};
160
Patrick Delaunay2c258092019-07-30 19:16:16 +0200161/* pre-reloc probe = reserve video frame buffer in video_reserve() */
162&ltdc {
163 u-boot,dm-pre-proper;
164};
165
Patrick Delaunay5a536df2020-10-15 15:01:12 +0200166/* temp = waiting kernel update */
167&m4_rproc {
168 resets = <&rcc MCU_R>,
169 <&rcc MCU_HOLD_BOOT_R>;
170 reset-names = "mcu_rst", "hold_boot";
171};
172
Patrick Delaunay35a54d42019-07-11 11:15:28 +0200173&pinctrl {
Patrice Chotard75500a42019-04-30 17:26:21 +0200174 u-boot,dm-pre-reloc;
175};
Patrick Delaunay35a54d42019-07-11 11:15:28 +0200176
177&pinctrl_z {
178 u-boot,dm-pre-reloc;
179};
180
Patrick Delaunay7915b992020-01-28 10:10:59 +0100181&pwr_regulators {
Patrick Delaunay35a54d42019-07-11 11:15:28 +0200182 u-boot,dm-pre-reloc;
183};
184
185&rcc {
186 u-boot,dm-pre-reloc;
Patrick Delaunay8d93a972020-01-28 10:11:03 +0100187 #address-cells = <1>;
188 #size-cells = <0>;
Patrick Delaunay35a54d42019-07-11 11:15:28 +0200189};
190
Patrick Delaunay0b733552020-07-06 14:48:58 +0200191&usart1 {
192 resets = <&rcc USART1_R>;
193};
194
195&usart2 {
196 resets = <&rcc USART2_R>;
197};
198
199&usart3 {
200 resets = <&rcc USART3_R>;
201};
202
203&uart4 {
204 resets = <&rcc UART4_R>;
205};
206
207&uart5 {
208 resets = <&rcc UART5_R>;
209};
210
211&usart6 {
212 resets = <&rcc USART6_R>;
213};
214
215&uart7 {
216 resets = <&rcc UART7_R>;
217};
218
219&uart8{
220 resets = <&rcc UART8_R>;
221};
222
Patrick Delaunay5564b4c2021-10-13 15:11:18 +0200223#if defined(CONFIG_STM32MP15x_STM32IMAGE)
224&binman {
225 u-boot-stm32 {
226 filename = "u-boot.stm32";
227 mkimage {
Patrice Chotardb9a0cc82021-11-15 11:39:13 +0100228 args = "-T stm32image -a 0xc0100000 -e 0xc0100000";
Patrick Delaunay5564b4c2021-10-13 15:11:18 +0200229 u-boot {
230 };
231 };
232 };
233};
234#endif
235
236#if defined(CONFIG_SPL)
237&binman {
238 spl-stm32 {
239 filename = "u-boot-spl.stm32";
240 mkimage {
Patrice Chotardb9a0cc82021-11-15 11:39:13 +0100241 args = "-T stm32image -a 0x2ffc2500 -e 0x2ffc2500";
Patrick Delaunay5564b4c2021-10-13 15:11:18 +0200242 u-boot-spl {
243 };
244 };
245 };
246};
247#endif