blob: 0a27f3c43efb80905e720ab2405a11792e03e5c6 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Mike Frysinger75ba6d62009-02-23 10:29:47 -05002/*
3 * SMSC LAN9[12]1[567] Network driver
4 *
5 * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de>
Mike Frysinger75ba6d62009-02-23 10:29:47 -05006 */
7
8#ifndef _SMC911X_H_
9#define _SMC911X_H_
10
Simon Glass90526e92020-05-10 11:39:56 -060011#include <net.h>
12
Mike Frysinger75ba6d62009-02-23 10:29:47 -050013/* Below are the register offsets and bit definitions
14 * of the Lan911x memory space
15 */
Ben Warren736fead2009-07-20 22:01:11 -070016#define RX_DATA_FIFO 0x00
Mike Frysinger75ba6d62009-02-23 10:29:47 -050017
Ben Warren736fead2009-07-20 22:01:11 -070018#define TX_DATA_FIFO 0x20
Mike Frysinger75ba6d62009-02-23 10:29:47 -050019#define TX_CMD_A_INT_ON_COMP 0x80000000
20#define TX_CMD_A_INT_BUF_END_ALGN 0x03000000
21#define TX_CMD_A_INT_4_BYTE_ALGN 0x00000000
22#define TX_CMD_A_INT_16_BYTE_ALGN 0x01000000
23#define TX_CMD_A_INT_32_BYTE_ALGN 0x02000000
24#define TX_CMD_A_INT_DATA_OFFSET 0x001F0000
25#define TX_CMD_A_INT_FIRST_SEG 0x00002000
26#define TX_CMD_A_INT_LAST_SEG 0x00001000
27#define TX_CMD_A_BUF_SIZE 0x000007FF
28#define TX_CMD_B_PKT_TAG 0xFFFF0000
29#define TX_CMD_B_ADD_CRC_DISABLE 0x00002000
30#define TX_CMD_B_DISABLE_PADDING 0x00001000
31#define TX_CMD_B_PKT_BYTE_LENGTH 0x000007FF
32
Ben Warren736fead2009-07-20 22:01:11 -070033#define RX_STATUS_FIFO 0x40
Mike Frysinger75ba6d62009-02-23 10:29:47 -050034#define RX_STS_PKT_LEN 0x3FFF0000
35#define RX_STS_ES 0x00008000
36#define RX_STS_BCST 0x00002000
37#define RX_STS_LEN_ERR 0x00001000
38#define RX_STS_RUNT_ERR 0x00000800
39#define RX_STS_MCAST 0x00000400
40#define RX_STS_TOO_LONG 0x00000080
41#define RX_STS_COLL 0x00000040
42#define RX_STS_ETH_TYPE 0x00000020
43#define RX_STS_WDOG_TMT 0x00000010
44#define RX_STS_MII_ERR 0x00000008
45#define RX_STS_DRIBBLING 0x00000004
46#define RX_STS_CRC_ERR 0x00000002
Ben Warren736fead2009-07-20 22:01:11 -070047#define RX_STATUS_FIFO_PEEK 0x44
48#define TX_STATUS_FIFO 0x48
Mike Frysinger75ba6d62009-02-23 10:29:47 -050049#define TX_STS_TAG 0xFFFF0000
50#define TX_STS_ES 0x00008000
51#define TX_STS_LOC 0x00000800
52#define TX_STS_NO_CARR 0x00000400
53#define TX_STS_LATE_COLL 0x00000200
54#define TX_STS_MANY_COLL 0x00000100
55#define TX_STS_COLL_CNT 0x00000078
56#define TX_STS_MANY_DEFER 0x00000004
57#define TX_STS_UNDERRUN 0x00000002
58#define TX_STS_DEFERRED 0x00000001
Ben Warren736fead2009-07-20 22:01:11 -070059#define TX_STATUS_FIFO_PEEK 0x4C
60#define ID_REV 0x50
Mike Frysinger75ba6d62009-02-23 10:29:47 -050061#define ID_REV_CHIP_ID 0xFFFF0000 /* RO */
62#define ID_REV_REV_ID 0x0000FFFF /* RO */
63
Ben Warren736fead2009-07-20 22:01:11 -070064#define INT_CFG 0x54
Mike Frysinger75ba6d62009-02-23 10:29:47 -050065#define INT_CFG_INT_DEAS 0xFF000000 /* R/W */
66#define INT_CFG_INT_DEAS_CLR 0x00004000
67#define INT_CFG_INT_DEAS_STS 0x00002000
68#define INT_CFG_IRQ_INT 0x00001000 /* RO */
69#define INT_CFG_IRQ_EN 0x00000100 /* R/W */
Ben Warren736fead2009-07-20 22:01:11 -070070 /* R/W Not Affected by SW Reset */
71#define INT_CFG_IRQ_POL 0x00000010
72 /* R/W Not Affected by SW Reset */
73#define INT_CFG_IRQ_TYPE 0x00000001
Mike Frysinger75ba6d62009-02-23 10:29:47 -050074
Ben Warren736fead2009-07-20 22:01:11 -070075#define INT_STS 0x58
Mike Frysinger75ba6d62009-02-23 10:29:47 -050076#define INT_STS_SW_INT 0x80000000 /* R/WC */
77#define INT_STS_TXSTOP_INT 0x02000000 /* R/WC */
78#define INT_STS_RXSTOP_INT 0x01000000 /* R/WC */
79#define INT_STS_RXDFH_INT 0x00800000 /* R/WC */
80#define INT_STS_RXDF_INT 0x00400000 /* R/WC */
81#define INT_STS_TX_IOC 0x00200000 /* R/WC */
82#define INT_STS_RXD_INT 0x00100000 /* R/WC */
83#define INT_STS_GPT_INT 0x00080000 /* R/WC */
84#define INT_STS_PHY_INT 0x00040000 /* RO */
85#define INT_STS_PME_INT 0x00020000 /* R/WC */
86#define INT_STS_TXSO 0x00010000 /* R/WC */
87#define INT_STS_RWT 0x00008000 /* R/WC */
88#define INT_STS_RXE 0x00004000 /* R/WC */
89#define INT_STS_TXE 0x00002000 /* R/WC */
90/*#define INT_STS_ERX 0x00001000*/ /* R/WC */
91#define INT_STS_TDFU 0x00000800 /* R/WC */
92#define INT_STS_TDFO 0x00000400 /* R/WC */
93#define INT_STS_TDFA 0x00000200 /* R/WC */
94#define INT_STS_TSFF 0x00000100 /* R/WC */
95#define INT_STS_TSFL 0x00000080 /* R/WC */
96/*#define INT_STS_RXDF 0x00000040*/ /* R/WC */
97#define INT_STS_RDFO 0x00000040 /* R/WC */
98#define INT_STS_RDFL 0x00000020 /* R/WC */
99#define INT_STS_RSFF 0x00000010 /* R/WC */
100#define INT_STS_RSFL 0x00000008 /* R/WC */
101#define INT_STS_GPIO2_INT 0x00000004 /* R/WC */
102#define INT_STS_GPIO1_INT 0x00000002 /* R/WC */
103#define INT_STS_GPIO0_INT 0x00000001 /* R/WC */
Ben Warren736fead2009-07-20 22:01:11 -0700104#define INT_EN 0x5C
Mike Frysinger75ba6d62009-02-23 10:29:47 -0500105#define INT_EN_SW_INT_EN 0x80000000 /* R/W */
106#define INT_EN_TXSTOP_INT_EN 0x02000000 /* R/W */
107#define INT_EN_RXSTOP_INT_EN 0x01000000 /* R/W */
108#define INT_EN_RXDFH_INT_EN 0x00800000 /* R/W */
109/*#define INT_EN_RXDF_INT_EN 0x00400000*/ /* R/W */
110#define INT_EN_TIOC_INT_EN 0x00200000 /* R/W */
111#define INT_EN_RXD_INT_EN 0x00100000 /* R/W */
112#define INT_EN_GPT_INT_EN 0x00080000 /* R/W */
113#define INT_EN_PHY_INT_EN 0x00040000 /* R/W */
114#define INT_EN_PME_INT_EN 0x00020000 /* R/W */
115#define INT_EN_TXSO_EN 0x00010000 /* R/W */
116#define INT_EN_RWT_EN 0x00008000 /* R/W */
117#define INT_EN_RXE_EN 0x00004000 /* R/W */
118#define INT_EN_TXE_EN 0x00002000 /* R/W */
119/*#define INT_EN_ERX_EN 0x00001000*/ /* R/W */
120#define INT_EN_TDFU_EN 0x00000800 /* R/W */
121#define INT_EN_TDFO_EN 0x00000400 /* R/W */
122#define INT_EN_TDFA_EN 0x00000200 /* R/W */
123#define INT_EN_TSFF_EN 0x00000100 /* R/W */
124#define INT_EN_TSFL_EN 0x00000080 /* R/W */
125/*#define INT_EN_RXDF_EN 0x00000040*/ /* R/W */
126#define INT_EN_RDFO_EN 0x00000040 /* R/W */
127#define INT_EN_RDFL_EN 0x00000020 /* R/W */
128#define INT_EN_RSFF_EN 0x00000010 /* R/W */
129#define INT_EN_RSFL_EN 0x00000008 /* R/W */
130#define INT_EN_GPIO2_INT 0x00000004 /* R/W */
131#define INT_EN_GPIO1_INT 0x00000002 /* R/W */
132#define INT_EN_GPIO0_INT 0x00000001 /* R/W */
133
Ben Warren736fead2009-07-20 22:01:11 -0700134#define BYTE_TEST 0x64
135#define FIFO_INT 0x68
Mike Frysinger75ba6d62009-02-23 10:29:47 -0500136#define FIFO_INT_TX_AVAIL_LEVEL 0xFF000000 /* R/W */
137#define FIFO_INT_TX_STS_LEVEL 0x00FF0000 /* R/W */
138#define FIFO_INT_RX_AVAIL_LEVEL 0x0000FF00 /* R/W */
139#define FIFO_INT_RX_STS_LEVEL 0x000000FF /* R/W */
140
Ben Warren736fead2009-07-20 22:01:11 -0700141#define RX_CFG 0x6C
Mike Frysinger75ba6d62009-02-23 10:29:47 -0500142#define RX_CFG_RX_END_ALGN 0xC0000000 /* R/W */
143#define RX_CFG_RX_END_ALGN4 0x00000000 /* R/W */
144#define RX_CFG_RX_END_ALGN16 0x40000000 /* R/W */
145#define RX_CFG_RX_END_ALGN32 0x80000000 /* R/W */
146#define RX_CFG_RX_DMA_CNT 0x0FFF0000 /* R/W */
147#define RX_CFG_RX_DUMP 0x00008000 /* R/W */
148#define RX_CFG_RXDOFF 0x00001F00 /* R/W */
149/*#define RX_CFG_RXBAD 0x00000001*/ /* R/W */
150
Ben Warren736fead2009-07-20 22:01:11 -0700151#define TX_CFG 0x70
Mike Frysinger75ba6d62009-02-23 10:29:47 -0500152/*#define TX_CFG_TX_DMA_LVL 0xE0000000*/ /* R/W */
Ben Warren736fead2009-07-20 22:01:11 -0700153 /* R/W Self Clearing */
154/*#define TX_CFG_TX_DMA_CNT 0x0FFF0000*/
Mike Frysinger75ba6d62009-02-23 10:29:47 -0500155#define TX_CFG_TXS_DUMP 0x00008000 /* Self Clearing */
156#define TX_CFG_TXD_DUMP 0x00004000 /* Self Clearing */
157#define TX_CFG_TXSAO 0x00000004 /* R/W */
158#define TX_CFG_TX_ON 0x00000002 /* R/W */
159#define TX_CFG_STOP_TX 0x00000001 /* Self Clearing */
160
Ben Warren736fead2009-07-20 22:01:11 -0700161#define HW_CFG 0x74
Mike Frysinger75ba6d62009-02-23 10:29:47 -0500162#define HW_CFG_TTM 0x00200000 /* R/W */
163#define HW_CFG_SF 0x00100000 /* R/W */
164#define HW_CFG_TX_FIF_SZ 0x000F0000 /* R/W */
165#define HW_CFG_TR 0x00003000 /* R/W */
166#define HW_CFG_PHY_CLK_SEL 0x00000060 /* R/W */
167#define HW_CFG_PHY_CLK_SEL_INT_PHY 0x00000000 /* R/W */
168#define HW_CFG_PHY_CLK_SEL_EXT_PHY 0x00000020 /* R/W */
169#define HW_CFG_PHY_CLK_SEL_CLK_DIS 0x00000040 /* R/W */
170#define HW_CFG_SMI_SEL 0x00000010 /* R/W */
171#define HW_CFG_EXT_PHY_DET 0x00000008 /* RO */
172#define HW_CFG_EXT_PHY_EN 0x00000004 /* R/W */
173#define HW_CFG_32_16_BIT_MODE 0x00000004 /* RO */
174#define HW_CFG_SRST_TO 0x00000002 /* RO */
175#define HW_CFG_SRST 0x00000001 /* Self Clearing */
176
Ben Warren736fead2009-07-20 22:01:11 -0700177#define RX_DP_CTRL 0x78
Mike Frysinger75ba6d62009-02-23 10:29:47 -0500178#define RX_DP_CTRL_RX_FFWD 0x80000000 /* R/W */
179#define RX_DP_CTRL_FFWD_BUSY 0x80000000 /* RO */
180
Ben Warren736fead2009-07-20 22:01:11 -0700181#define RX_FIFO_INF 0x7C
Mike Frysinger75ba6d62009-02-23 10:29:47 -0500182#define RX_FIFO_INF_RXSUSED 0x00FF0000 /* RO */
183#define RX_FIFO_INF_RXDUSED 0x0000FFFF /* RO */
184
Ben Warren736fead2009-07-20 22:01:11 -0700185#define TX_FIFO_INF 0x80
Mike Frysinger75ba6d62009-02-23 10:29:47 -0500186#define TX_FIFO_INF_TSUSED 0x00FF0000 /* RO */
187#define TX_FIFO_INF_TDFREE 0x0000FFFF /* RO */
188
Ben Warren736fead2009-07-20 22:01:11 -0700189#define PMT_CTRL 0x84
Mike Frysinger75ba6d62009-02-23 10:29:47 -0500190#define PMT_CTRL_PM_MODE 0x00003000 /* Self Clearing */
191#define PMT_CTRL_PHY_RST 0x00000400 /* Self Clearing */
192#define PMT_CTRL_WOL_EN 0x00000200 /* R/W */
193#define PMT_CTRL_ED_EN 0x00000100 /* R/W */
Ben Warren736fead2009-07-20 22:01:11 -0700194 /* R/W Not Affected by SW Reset */
195#define PMT_CTRL_PME_TYPE 0x00000040
Mike Frysinger75ba6d62009-02-23 10:29:47 -0500196#define PMT_CTRL_WUPS 0x00000030 /* R/WC */
197#define PMT_CTRL_WUPS_NOWAKE 0x00000000 /* R/WC */
198#define PMT_CTRL_WUPS_ED 0x00000010 /* R/WC */
199#define PMT_CTRL_WUPS_WOL 0x00000020 /* R/WC */
200#define PMT_CTRL_WUPS_MULTI 0x00000030 /* R/WC */
201#define PMT_CTRL_PME_IND 0x00000008 /* R/W */
202#define PMT_CTRL_PME_POL 0x00000004 /* R/W */
Ben Warren736fead2009-07-20 22:01:11 -0700203 /* R/W Not Affected by SW Reset */
204#define PMT_CTRL_PME_EN 0x00000002
Mike Frysinger75ba6d62009-02-23 10:29:47 -0500205#define PMT_CTRL_READY 0x00000001 /* RO */
206
Ben Warren736fead2009-07-20 22:01:11 -0700207#define GPIO_CFG 0x88
Mike Frysinger75ba6d62009-02-23 10:29:47 -0500208#define GPIO_CFG_LED3_EN 0x40000000 /* R/W */
209#define GPIO_CFG_LED2_EN 0x20000000 /* R/W */
210#define GPIO_CFG_LED1_EN 0x10000000 /* R/W */
211#define GPIO_CFG_GPIO2_INT_POL 0x04000000 /* R/W */
212#define GPIO_CFG_GPIO1_INT_POL 0x02000000 /* R/W */
213#define GPIO_CFG_GPIO0_INT_POL 0x01000000 /* R/W */
214#define GPIO_CFG_EEPR_EN 0x00700000 /* R/W */
215#define GPIO_CFG_GPIOBUF2 0x00040000 /* R/W */
216#define GPIO_CFG_GPIOBUF1 0x00020000 /* R/W */
217#define GPIO_CFG_GPIOBUF0 0x00010000 /* R/W */
218#define GPIO_CFG_GPIODIR2 0x00000400 /* R/W */
219#define GPIO_CFG_GPIODIR1 0x00000200 /* R/W */
220#define GPIO_CFG_GPIODIR0 0x00000100 /* R/W */
221#define GPIO_CFG_GPIOD4 0x00000010 /* R/W */
222#define GPIO_CFG_GPIOD3 0x00000008 /* R/W */
223#define GPIO_CFG_GPIOD2 0x00000004 /* R/W */
224#define GPIO_CFG_GPIOD1 0x00000002 /* R/W */
225#define GPIO_CFG_GPIOD0 0x00000001 /* R/W */
226
Ben Warren736fead2009-07-20 22:01:11 -0700227#define GPT_CFG 0x8C
Mike Frysinger75ba6d62009-02-23 10:29:47 -0500228#define GPT_CFG_TIMER_EN 0x20000000 /* R/W */
229#define GPT_CFG_GPT_LOAD 0x0000FFFF /* R/W */
230
Ben Warren736fead2009-07-20 22:01:11 -0700231#define GPT_CNT 0x90
Mike Frysinger75ba6d62009-02-23 10:29:47 -0500232#define GPT_CNT_GPT_CNT 0x0000FFFF /* RO */
233
Ben Warren736fead2009-07-20 22:01:11 -0700234#define ENDIAN 0x98
235#define FREE_RUN 0x9C
236#define RX_DROP 0xA0
237#define MAC_CSR_CMD 0xA4
Mike Frysinger75ba6d62009-02-23 10:29:47 -0500238#define MAC_CSR_CMD_CSR_BUSY 0x80000000 /* Self Clearing */
239#define MAC_CSR_CMD_R_NOT_W 0x40000000 /* R/W */
240#define MAC_CSR_CMD_CSR_ADDR 0x000000FF /* R/W */
241
Ben Warren736fead2009-07-20 22:01:11 -0700242#define MAC_CSR_DATA 0xA8
243#define AFC_CFG 0xAC
Mike Frysinger75ba6d62009-02-23 10:29:47 -0500244#define AFC_CFG_AFC_HI 0x00FF0000 /* R/W */
245#define AFC_CFG_AFC_LO 0x0000FF00 /* R/W */
246#define AFC_CFG_BACK_DUR 0x000000F0 /* R/W */
247#define AFC_CFG_FCMULT 0x00000008 /* R/W */
248#define AFC_CFG_FCBRD 0x00000004 /* R/W */
249#define AFC_CFG_FCADD 0x00000002 /* R/W */
250#define AFC_CFG_FCANY 0x00000001 /* R/W */
251
Ben Warren736fead2009-07-20 22:01:11 -0700252#define E2P_CMD 0xB0
Mike Frysinger75ba6d62009-02-23 10:29:47 -0500253#define E2P_CMD_EPC_BUSY 0x80000000 /* Self Clearing */
254#define E2P_CMD_EPC_CMD 0x70000000 /* R/W */
255#define E2P_CMD_EPC_CMD_READ 0x00000000 /* R/W */
256#define E2P_CMD_EPC_CMD_EWDS 0x10000000 /* R/W */
257#define E2P_CMD_EPC_CMD_EWEN 0x20000000 /* R/W */
258#define E2P_CMD_EPC_CMD_WRITE 0x30000000 /* R/W */
259#define E2P_CMD_EPC_CMD_WRAL 0x40000000 /* R/W */
260#define E2P_CMD_EPC_CMD_ERASE 0x50000000 /* R/W */
261#define E2P_CMD_EPC_CMD_ERAL 0x60000000 /* R/W */
262#define E2P_CMD_EPC_CMD_RELOAD 0x70000000 /* R/W */
263#define E2P_CMD_EPC_TIMEOUT 0x00000200 /* RO */
264#define E2P_CMD_MAC_ADDR_LOADED 0x00000100 /* RO */
265#define E2P_CMD_EPC_ADDR 0x000000FF /* R/W */
266
Ben Warren736fead2009-07-20 22:01:11 -0700267#define E2P_DATA 0xB4
Mike Frysinger75ba6d62009-02-23 10:29:47 -0500268#define E2P_DATA_EEPROM_DATA 0x000000FF /* R/W */
269/* end of LAN register offsets and bit definitions */
270
271/* MAC Control and Status registers */
272#define MAC_CR 0x01 /* R/W */
273
274/* MAC_CR - MAC Control Register */
275#define MAC_CR_RXALL 0x80000000
276/* TODO: delete this bit? It is not described in the data sheet. */
277#define MAC_CR_HBDIS 0x10000000
278#define MAC_CR_RCVOWN 0x00800000
279#define MAC_CR_LOOPBK 0x00200000
280#define MAC_CR_FDPX 0x00100000
281#define MAC_CR_MCPAS 0x00080000
282#define MAC_CR_PRMS 0x00040000
283#define MAC_CR_INVFILT 0x00020000
284#define MAC_CR_PASSBAD 0x00010000
285#define MAC_CR_HFILT 0x00008000
286#define MAC_CR_HPFILT 0x00002000
287#define MAC_CR_LCOLL 0x00001000
288#define MAC_CR_BCAST 0x00000800
289#define MAC_CR_DISRTY 0x00000400
290#define MAC_CR_PADSTR 0x00000100
291#define MAC_CR_BOLMT_MASK 0x000000C0
292#define MAC_CR_DFCHK 0x00000020
293#define MAC_CR_TXEN 0x00000008
294#define MAC_CR_RXEN 0x00000004
295
296#define ADDRH 0x02 /* R/W mask 0x0000FFFFUL */
297#define ADDRL 0x03 /* R/W mask 0xFFFFFFFFUL */
298#define HASHH 0x04 /* R/W */
299#define HASHL 0x05 /* R/W */
300
301#define MII_ACC 0x06 /* R/W */
302#define MII_ACC_PHY_ADDR 0x0000F800
303#define MII_ACC_MIIRINDA 0x000007C0
304#define MII_ACC_MII_WRITE 0x00000002
305#define MII_ACC_MII_BUSY 0x00000001
306
307#define MII_DATA 0x07 /* R/W mask 0x0000FFFFUL */
308
309#define FLOW 0x08 /* R/W */
310#define FLOW_FCPT 0xFFFF0000
311#define FLOW_FCPASS 0x00000004
312#define FLOW_FCEN 0x00000002
313#define FLOW_FCBSY 0x00000001
314
315#define VLAN1 0x09 /* R/W mask 0x0000FFFFUL */
316#define VLAN1_VTI1 0x0000ffff
317
318#define VLAN2 0x0A /* R/W mask 0x0000FFFFUL */
319#define VLAN2_VTI2 0x0000ffff
320
321#define WUFF 0x0B /* WO */
322
323#define WUCSR 0x0C /* R/W */
324#define WUCSR_GUE 0x00000200
325#define WUCSR_WUFR 0x00000040
326#define WUCSR_MPR 0x00000020
327#define WUCSR_WAKE_EN 0x00000004
328#define WUCSR_MPEN 0x00000002
329
330/* Chip ID values */
Phil Edworthyaf5de5d2011-05-31 03:53:11 +0000331#define CHIP_89218 0x218a
Mike Frysinger75ba6d62009-02-23 10:29:47 -0500332#define CHIP_9115 0x115
333#define CHIP_9116 0x116
334#define CHIP_9117 0x117
335#define CHIP_9118 0x118
336#define CHIP_9211 0x9211
337#define CHIP_9215 0x115a
338#define CHIP_9216 0x116a
339#define CHIP_9217 0x117a
340#define CHIP_9218 0x118a
Daniel Mackc55096c2009-04-08 13:23:38 +0200341#define CHIP_9220 0x9220
Andreas Pretzsch2ea20ef2009-07-09 21:50:05 +0200342#define CHIP_9221 0x9221
Mike Frysinger75ba6d62009-02-23 10:29:47 -0500343
Mike Frysinger75ba6d62009-02-23 10:29:47 -0500344#endif