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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Simon Glass18530302013-03-19 04:58:56 +00002/*
3 * Copyright (c) 2011 The Chromium OS Authors.
4 *
Simon Glass18530302013-03-19 04:58:56 +00005 * This file is derived from the flashrom project.
6 */
7
Bin Meng9eb43392016-02-01 01:40:36 -08008#ifndef _ICH_H_
9#define _ICH_H_
10
Simon Glass18530302013-03-19 04:58:56 +000011struct ich7_spi_regs {
12 uint16_t spis;
13 uint16_t spic;
14 uint32_t spia;
15 uint64_t spid[8];
16 uint64_t _pad;
17 uint32_t bbar;
18 uint16_t preop;
19 uint16_t optype;
20 uint8_t opmenu[8];
21} __packed;
22
23struct ich9_spi_regs {
Bin Meng9eb43392016-02-01 01:40:36 -080024 uint32_t bfpr; /* 0x00 */
Simon Glass18530302013-03-19 04:58:56 +000025 uint16_t hsfs;
26 uint16_t hsfc;
27 uint32_t faddr;
28 uint32_t _reserved0;
Bin Meng9eb43392016-02-01 01:40:36 -080029 uint32_t fdata[16]; /* 0x10 */
30 uint32_t frap; /* 0x50 */
Simon Glass18530302013-03-19 04:58:56 +000031 uint32_t freg[5];
32 uint32_t _reserved1[3];
Bin Meng9eb43392016-02-01 01:40:36 -080033 uint32_t pr[5]; /* 0x74 */
Simon Glass18530302013-03-19 04:58:56 +000034 uint32_t _reserved2[2];
Bin Meng9eb43392016-02-01 01:40:36 -080035 uint8_t ssfs; /* 0x90 */
Simon Glass18530302013-03-19 04:58:56 +000036 uint8_t ssfc[3];
Bin Meng9eb43392016-02-01 01:40:36 -080037 uint16_t preop; /* 0x94 */
Simon Glass18530302013-03-19 04:58:56 +000038 uint16_t optype;
Bin Meng9eb43392016-02-01 01:40:36 -080039 uint8_t opmenu[8]; /* 0x98 */
Simon Glass18530302013-03-19 04:58:56 +000040 uint32_t bbar;
41 uint8_t _reserved3[12];
Bin Meng9eb43392016-02-01 01:40:36 -080042 uint32_t fdoc; /* 0xb0 */
Simon Glass18530302013-03-19 04:58:56 +000043 uint32_t fdod;
44 uint8_t _reserved4[8];
Bin Meng9eb43392016-02-01 01:40:36 -080045 uint32_t afc; /* 0xc0 */
Simon Glass18530302013-03-19 04:58:56 +000046 uint32_t lvscc;
47 uint32_t uvscc;
48 uint8_t _reserved5[4];
Bin Meng9eb43392016-02-01 01:40:36 -080049 uint32_t fpb; /* 0xd0 */
Simon Glass18530302013-03-19 04:58:56 +000050 uint8_t _reserved6[28];
Bin Meng9eb43392016-02-01 01:40:36 -080051 uint32_t srdl; /* 0xf0 */
Simon Glass18530302013-03-19 04:58:56 +000052 uint32_t srdc;
Simon Glass5093bad2015-01-27 22:13:43 -070053 uint32_t scs;
54 uint32_t bcr;
Simon Glass18530302013-03-19 04:58:56 +000055} __packed;
56
57enum {
58 SPIS_SCIP = 0x0001,
59 SPIS_GRANT = 0x0002,
60 SPIS_CDS = 0x0004,
61 SPIS_FCERR = 0x0008,
62 SSFS_AEL = 0x0010,
63 SPIS_LOCK = 0x8000,
64 SPIS_RESERVED_MASK = 0x7ff0,
65 SSFS_RESERVED_MASK = 0x7fe2
66};
67
68enum {
69 SPIC_SCGO = 0x000002,
70 SPIC_ACS = 0x000004,
71 SPIC_SPOP = 0x000008,
72 SPIC_DBC = 0x003f00,
73 SPIC_DS = 0x004000,
74 SPIC_SME = 0x008000,
75 SSFC_SCF_MASK = 0x070000,
76 SSFC_RESERVED = 0xf80000,
77
78 /* Mask for speed byte, biuts 23:16 of SSFC */
79 SSFC_SCF_33MHZ = 0x01,
80};
81
82enum {
83 HSFS_FDONE = 0x0001,
84 HSFS_FCERR = 0x0002,
85 HSFS_AEL = 0x0004,
86 HSFS_BERASE_MASK = 0x0018,
87 HSFS_BERASE_SHIFT = 3,
88 HSFS_SCIP = 0x0020,
89 HSFS_FDOPSS = 0x2000,
90 HSFS_FDV = 0x4000,
91 HSFS_FLOCKDN = 0x8000
92};
93
94enum {
95 HSFC_FGO = 0x0001,
96 HSFC_FCYCLE_MASK = 0x0006,
97 HSFC_FCYCLE_SHIFT = 1,
98 HSFC_FDBC_MASK = 0x3f00,
99 HSFC_FDBC_SHIFT = 8,
100 HSFC_FSMIE = 0x8000
101};
102
Simon Glass18530302013-03-19 04:58:56 +0000103struct spi_trans {
Bernhard Messerklinger0709ddb2019-08-02 08:38:34 +0200104 uint8_t cmd;
Simon Glass18530302013-03-19 04:58:56 +0000105 const uint8_t *out;
106 uint32_t bytesout;
107 uint8_t *in;
108 uint32_t bytesin;
109 uint8_t type;
110 uint8_t opcode;
111 uint32_t offset;
112};
113
Stefan Roese4759dff2017-04-24 09:48:04 +0200114#define SPI_OPCODE_WRSR 0x01
115#define SPI_OPCODE_PAGE_PROGRAM 0x02
116#define SPI_OPCODE_READ 0x03
117#define SPI_OPCODE_WRDIS 0x04
118#define SPI_OPCODE_RDSR 0x05
Bin Meng9eb43392016-02-01 01:40:36 -0800119#define SPI_OPCODE_WREN 0x06
120#define SPI_OPCODE_FAST_READ 0x0b
Stefan Roese4759dff2017-04-24 09:48:04 +0200121#define SPI_OPCODE_ERASE_SECT 0x20
122#define SPI_OPCODE_READ_ID 0x9f
123#define SPI_OPCODE_ERASE_BLOCK 0xd8
124
125#define SPI_OPCODE_TYPE_READ_NO_ADDRESS 0
126#define SPI_OPCODE_TYPE_WRITE_NO_ADDRESS 1
127#define SPI_OPCODE_TYPE_READ_WITH_ADDRESS 2
128#define SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS 3
129
130#define SPI_OPMENU_0 SPI_OPCODE_WRSR
131#define SPI_OPTYPE_0 SPI_OPCODE_TYPE_WRITE_NO_ADDRESS
132
133#define SPI_OPMENU_1 SPI_OPCODE_PAGE_PROGRAM
134#define SPI_OPTYPE_1 SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS
135
136#define SPI_OPMENU_2 SPI_OPCODE_READ
137#define SPI_OPTYPE_2 SPI_OPCODE_TYPE_READ_WITH_ADDRESS
138
139#define SPI_OPMENU_3 SPI_OPCODE_RDSR
140#define SPI_OPTYPE_3 SPI_OPCODE_TYPE_READ_NO_ADDRESS
141
142#define SPI_OPMENU_4 SPI_OPCODE_ERASE_SECT
143#define SPI_OPTYPE_4 SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS
144
145#define SPI_OPMENU_5 SPI_OPCODE_READ_ID
146#define SPI_OPTYPE_5 SPI_OPCODE_TYPE_READ_NO_ADDRESS
147
148#define SPI_OPMENU_6 SPI_OPCODE_ERASE_BLOCK
149#define SPI_OPTYPE_6 SPI_OPCODE_TYPE_WRITE_WITH_ADDRESS
150
151#define SPI_OPMENU_7 SPI_OPCODE_FAST_READ
152#define SPI_OPTYPE_7 SPI_OPCODE_TYPE_READ_WITH_ADDRESS
153
154#define SPI_OPPREFIX ((SPI_OPCODE_WREN << 8) | SPI_OPCODE_WREN)
155#define SPI_OPTYPE ((SPI_OPTYPE_7 << 14) | (SPI_OPTYPE_6 << 12) | \
156 (SPI_OPTYPE_5 << 10) | (SPI_OPTYPE_4 << 8) | \
157 (SPI_OPTYPE_3 << 6) | (SPI_OPTYPE_2 << 4) | \
158 (SPI_OPTYPE_1 << 2) | (SPI_OPTYPE_0 << 0))
159#define SPI_OPMENU_UPPER ((SPI_OPMENU_7 << 24) | (SPI_OPMENU_6 << 16) | \
160 (SPI_OPMENU_5 << 8) | (SPI_OPMENU_4 << 0))
161#define SPI_OPMENU_LOWER ((SPI_OPMENU_3 << 24) | (SPI_OPMENU_2 << 16) | \
162 (SPI_OPMENU_1 << 8) | (SPI_OPMENU_0 << 0))
Bin Meng9eb43392016-02-01 01:40:36 -0800163
Bernhard Messerklinger0709ddb2019-08-02 08:38:34 +0200164#define ICH_BOUNDARY 0x1000
165
Simon Glass1facebd2019-12-06 21:42:46 -0700166#define HSFSTS_FDBC_SHIFT 24
167#define HSFSTS_FDBC_MASK (0x3f << HSFSTS_FDBC_SHIFT)
168#define HSFSTS_WET BIT(21)
169#define HSFSTS_FCYCLE_SHIFT 17
170#define HSFSTS_FCYCLE_MASK (0xf << HSFSTS_FCYCLE_SHIFT)
171
172/* Supported flash cycle types */
173enum hsfsts_cycle_t {
174 HSFSTS_CYCLE_READ = 0,
175 HSFSTS_CYCLE_WRITE = 2,
176 HSFSTS_CYCLE_4K_ERASE,
177 HSFSTS_CYCLE_64K_ERASE,
178 HSFSTS_CYCLE_RDSFDP,
179 HSFSTS_CYCLE_RDID,
180 HSFSTS_CYCLE_WR_STATUS,
181 HSFSTS_CYCLE_RD_STATUS,
182};
183
184#define HSFSTS_FGO BIT(16)
185#define HSFSTS_FLOCKDN BIT(15)
186#define HSFSTS_FDV BIT(14)
187#define HSFSTS_FDOPSS BIT(13)
188#define HSFSTS_WRSDIS BIT(11)
189#define HSFSTS_SAF_CE BIT(8)
190#define HSFSTS_SAF_ACTIVE BIT(7)
191#define HSFSTS_SAF_LE BIT(6)
192#define HSFSTS_SCIP BIT(5)
193#define HSFSTS_SAF_DLE BIT(4)
194#define HSFSTS_SAF_ERROR BIT(3)
195#define HSFSTS_AEL BIT(2)
196#define HSFSTS_FCERR BIT(1)
197#define HSFSTS_FDONE BIT(0)
198#define HSFSTS_W1C_BITS 0xff
199
200/* Maximum bytes of data that can fit in FDATAn (0x10) registers */
201#define SPIBAR_FDATA_FIFO_SIZE 0x40
202
203#define SPIBAR_HWSEQ_XFER_TIMEOUT_MS 5000
204
Bin Meng6e670b52016-02-01 01:40:38 -0800205enum ich_version {
206 ICHV_7,
207 ICHV_9,
Simon Glass3937df32019-12-06 21:42:49 -0700208 ICHV_APL,
Bin Meng6e670b52016-02-01 01:40:38 -0800209};
210
Bin Meng9eb43392016-02-01 01:40:36 -0800211struct ich_spi_priv {
Bin Meng9eb43392016-02-01 01:40:36 -0800212 int opmenu;
213 int menubytes;
214 void *base; /* Base of register set */
215 int preop;
216 int optype;
217 int addr;
218 int data;
219 unsigned databytes;
220 int status;
221 int control;
222 int bbar;
223 int bcr;
224 uint32_t *pr; /* only for ich9 */
225 int speed; /* pointer to speed control */
226 ulong max_speed; /* Maximum bus speed in MHz */
227 ulong cur_speed; /* Current bus speed */
228 struct spi_trans trans; /* current transaction in progress */
Simon Glass17e75442019-12-06 21:42:38 -0700229 struct udevice *pch; /* PCH, used to control SPI access */
Bin Meng9eb43392016-02-01 01:40:36 -0800230};
231
232#endif /* _ICH_H_ */