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Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Heiko Schocher7254d922015-05-18 13:32:31 +02002/*
3 * Copyright (C) 2013 Boundary Devices
Heiko Schocher7254d922015-05-18 13:32:31 +02004 */
5/* ZQ Calibration */
6DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xa1390003
7DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001F001F
8DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F
9DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x001F001F
10DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x001F001F
11/*
12 * DQS gating, read delay, write delay calibration values
13 */
14DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x42190217
15DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x017B017B
16DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x4176017B
17DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x015F016C
18DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x4C4C4D4C
19DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x4A4D4C48
20DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x3F3F3F40
21DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x3538382E
22/* read data bit delay */
23DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333
24DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333
25DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333
26DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333
27DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333
28DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333
29DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333
30DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333
31/* Complete calibration by forced measurment */
32DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800
33DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800
34/* in DDR3, 64-bit mode, only MMDC0 is initiated */
35DATA 4, MX6_MMDC_P0_MDPDC, 0x00020025
36DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030
37DATA 4, MX6_MMDC_P0_MDCFG0, 0x676B5313
38DATA 4, MX6_MMDC_P0_MDCFG1, 0xB66E8B63
39DATA 4, MX6_MMDC_P0_MDCFG2, 0x01FF00DB
40DATA 4, MX6_MMDC_P0_MDMISC, 0x00001740
41DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000
42DATA 4, MX6_MMDC_P0_MDRWD, 0x000026d2
43DATA 4, MX6_MMDC_P0_MDOR, 0x006B1023
44DATA 4, MX6_MMDC_P0_MDASP, 0x00000027
45DATA 4, MX6_MMDC_P0_MDCTL, 0x84190000
46
47DATA 4, MX6_MMDC_P0_MDSCR, 0x04008032
48DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033
49DATA 4, MX6_MMDC_P0_MDSCR, 0x00048031
50DATA 4, MX6_MMDC_P0_MDSCR, 0x05208030
51DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040
52
53/* final ddr setup */
54DATA 4, MX6_MMDC_P0_MDREF, 0x00005800
55DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00011117
56DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00011117
57DATA 4, MX6_MMDC_P0_MDPDC, 0x00025565
58DATA 4, MX6_MMDC_P0_MAPSR, 0x00011006
59DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000