blob: 06f2f73a03f3236aa5acf260a72643d149ed5a24 [file] [log] [blame]
Jagan Tekic1f09502021-04-26 18:23:46 +05301// SPDX-License-Identifier: GPL-2.0+
2/*
3 * Copyright (C) 2020 Jagan Teki <jagan@amarulasolutions.com>
4 */
5
Marcel Ziswiler7cf55972021-10-23 01:15:13 +02006/ {
7 binman: binman {
8 multiple-images;
9 };
Tim Harveybb6a4c52023-08-24 12:01:42 -070010
11#ifdef CONFIG_OPTEE
12 firmware {
13 optee {
14 compatible = "linaro,optee-tz";
15 method = "smc";
16 };
17 };
18#endif
Marcel Ziswiler7cf55972021-10-23 01:15:13 +020019};
20
Tim Harvey93cac452023-08-24 12:03:56 -070021#ifdef CONFIG_FSL_CAAM
22&crypto {
23 bootph-pre-ram;
24};
25#endif
26
Marcel Ziswilerdbd5ca22022-11-07 22:22:41 +010027&soc {
Simon Glass8c103c32023-02-13 08:56:33 -070028 bootph-all;
29 bootph-pre-ram;
Jagan Tekic1f09502021-04-26 18:23:46 +053030};
31
32&aips1 {
Simon Glass8c103c32023-02-13 08:56:33 -070033 bootph-all;
34 bootph-pre-ram;
Jagan Tekic1f09502021-04-26 18:23:46 +053035};
36
37&aips2 {
Simon Glass8c103c32023-02-13 08:56:33 -070038 bootph-pre-ram;
Jagan Tekic1f09502021-04-26 18:23:46 +053039};
40
41&aips3 {
Simon Glass8c103c32023-02-13 08:56:33 -070042 bootph-pre-ram;
Jagan Tekic1f09502021-04-26 18:23:46 +053043};
44
Marcel Ziswiler7cf55972021-10-23 01:15:13 +020045&binman {
46 u-boot-spl-ddr {
Marcel Ziswilerf08c3fee2021-10-23 01:15:14 +020047 align = <4>;
48 align-size = <4>;
Marcel Ziswiler7cf55972021-10-23 01:15:13 +020049 filename = "u-boot-spl-ddr.bin";
50 pad-byte = <0xff>;
Marcel Ziswiler7cf55972021-10-23 01:15:13 +020051
52 u-boot-spl {
53 align-end = <4>;
Marcel Ziswiler86b7f202021-10-23 01:15:15 +020054 filename = "u-boot-spl.bin";
Marcel Ziswiler7cf55972021-10-23 01:15:13 +020055 };
56
Peng Fan25daa2c2022-07-26 16:41:20 +080057 ddr-1d-imem-fw {
Marcel Ziswiler7cf55972021-10-23 01:15:13 +020058 filename = "lpddr4_pmu_train_1d_imem.bin";
Peng Fanc065a6c2022-07-26 16:41:22 +080059 align-end = <4>;
Marcel Ziswilerf17fb6c2021-10-23 01:15:16 +020060 type = "blob-ext";
Marcel Ziswiler7cf55972021-10-23 01:15:13 +020061 };
62
Peng Fan25daa2c2022-07-26 16:41:20 +080063 ddr-1d-dmem-fw {
Marcel Ziswiler7cf55972021-10-23 01:15:13 +020064 filename = "lpddr4_pmu_train_1d_dmem.bin";
Peng Fanc065a6c2022-07-26 16:41:22 +080065 align-end = <4>;
Marcel Ziswilerf17fb6c2021-10-23 01:15:16 +020066 type = "blob-ext";
Marcel Ziswiler7cf55972021-10-23 01:15:13 +020067 };
68
Peng Fan25daa2c2022-07-26 16:41:20 +080069 ddr-2d-imem-fw {
Marcel Ziswiler7cf55972021-10-23 01:15:13 +020070 filename = "lpddr4_pmu_train_2d_imem.bin";
Peng Fanc065a6c2022-07-26 16:41:22 +080071 align-end = <4>;
Marcel Ziswilerf17fb6c2021-10-23 01:15:16 +020072 type = "blob-ext";
Marcel Ziswiler7cf55972021-10-23 01:15:13 +020073 };
74
Peng Fan25daa2c2022-07-26 16:41:20 +080075 ddr-2d-dmem-fw {
Marcel Ziswiler7cf55972021-10-23 01:15:13 +020076 filename = "lpddr4_pmu_train_2d_dmem.bin";
Peng Fanc065a6c2022-07-26 16:41:22 +080077 align-end = <4>;
Marcel Ziswilerf17fb6c2021-10-23 01:15:16 +020078 type = "blob-ext";
Marcel Ziswiler7cf55972021-10-23 01:15:13 +020079 };
80 };
81
82 spl {
83 filename = "spl.bin";
84
85 mkimage {
86 args = "-n spl/u-boot-spl.cfgout -T imx8mimage -e 0x7e1000";
87
88 blob {
89 filename = "u-boot-spl-ddr.bin";
90 };
91 };
92 };
93
94 itb {
95 filename = "u-boot.itb";
96
97 fit {
98 description = "Configuration to load ATF before U-Boot";
Marek Vasut6039e0e2023-05-28 23:00:30 +020099#ifndef CONFIG_IMX_HAB
Marcel Ziswiler7cf55972021-10-23 01:15:13 +0200100 fit,external-offset = <CONFIG_FIT_EXTERNAL_OFFSET>;
Marek Vasut6039e0e2023-05-28 23:00:30 +0200101#endif
Marcel Ziswiler7cf55972021-10-23 01:15:13 +0200102 fit,fdt-list = "of-list";
Marcel Ziswilerf08c3fee2021-10-23 01:15:14 +0200103 #address-cells = <1>;
Marcel Ziswiler7cf55972021-10-23 01:15:13 +0200104
105 images {
106 uboot {
Marcel Ziswiler7cf55972021-10-23 01:15:13 +0200107 arch = "arm64";
108 compression = "none";
Marcel Ziswilerf08c3fee2021-10-23 01:15:14 +0200109 description = "U-Boot (64-bit)";
Simon Glass98463902022-10-20 18:22:39 -0600110 load = <CONFIG_TEXT_BASE>;
Marcel Ziswilerf08c3fee2021-10-23 01:15:14 +0200111 type = "standalone";
Marcel Ziswiler7cf55972021-10-23 01:15:13 +0200112
Patrick Wildt49f55652022-01-13 15:22:17 +0100113 uboot-blob {
Marcel Ziswiler7cf55972021-10-23 01:15:13 +0200114 filename = "u-boot-nodtb.bin";
Marcel Ziswilerf17fb6c2021-10-23 01:15:16 +0200115 type = "blob-ext";
Marcel Ziswiler7cf55972021-10-23 01:15:13 +0200116 };
117 };
118
Marek Vasut9694c0532022-12-22 01:46:37 +0100119#ifndef CONFIG_ARMV8_PSCI
Marcel Ziswiler7cf55972021-10-23 01:15:13 +0200120 atf {
Marcel Ziswiler7cf55972021-10-23 01:15:13 +0200121 arch = "arm64";
122 compression = "none";
Marcel Ziswilerf08c3fee2021-10-23 01:15:14 +0200123 description = "ARM Trusted Firmware";
Marcel Ziswiler7cf55972021-10-23 01:15:13 +0200124 entry = <0x920000>;
Marcel Ziswilerf08c3fee2021-10-23 01:15:14 +0200125 load = <0x920000>;
126 type = "firmware";
Marcel Ziswiler7cf55972021-10-23 01:15:13 +0200127
Patrick Wildt49f55652022-01-13 15:22:17 +0100128 atf-blob {
Marcel Ziswiler7cf55972021-10-23 01:15:13 +0200129 filename = "bl31.bin";
Marcel Ziswiler310de882022-04-08 10:06:56 +0200130 type = "atf-bl31";
Marcel Ziswiler7cf55972021-10-23 01:15:13 +0200131 };
132 };
Marek Vasut9694c0532022-12-22 01:46:37 +0100133#endif
Marcel Ziswiler7cf55972021-10-23 01:15:13 +0200134
135 binman_fip: fip {
Marcel Ziswiler7cf55972021-10-23 01:15:13 +0200136 arch = "arm64";
137 compression = "none";
Marcel Ziswilerf08c3fee2021-10-23 01:15:14 +0200138 description = "Trusted Firmware FIP";
Marcel Ziswiler7cf55972021-10-23 01:15:13 +0200139 load = <0x40310000>;
Marcel Ziswilerf08c3fee2021-10-23 01:15:14 +0200140 type = "firmware";
Marcel Ziswiler7cf55972021-10-23 01:15:13 +0200141 };
142
143 @fdt-SEQ {
Marcel Ziswilerf08c3fee2021-10-23 01:15:14 +0200144 compression = "none";
Marcel Ziswiler7cf55972021-10-23 01:15:13 +0200145 description = "NAME";
146 type = "flat_dt";
Marcel Ziswiler7cf55972021-10-23 01:15:13 +0200147
Patrick Wildt49f55652022-01-13 15:22:17 +0100148 uboot-fdt-blob {
Marcel Ziswiler7cf55972021-10-23 01:15:13 +0200149 filename = "u-boot.dtb";
Marcel Ziswilerf17fb6c2021-10-23 01:15:16 +0200150 type = "blob-ext";
Marcel Ziswiler7cf55972021-10-23 01:15:13 +0200151 };
152 };
153 };
154
155 configurations {
156 default = "@config-DEFAULT-SEQ";
157
Simon Glass98244a82023-08-23 19:18:01 -0600158 @config-SEQ {
Marcel Ziswiler7cf55972021-10-23 01:15:13 +0200159 description = "NAME";
Marcel Ziswilerf08c3fee2021-10-23 01:15:14 +0200160 fdt = "fdt-SEQ";
Marcel Ziswiler7cf55972021-10-23 01:15:13 +0200161 firmware = "uboot";
Marek Vasut9694c0532022-12-22 01:46:37 +0100162#ifndef CONFIG_ARMV8_PSCI
Marcel Ziswiler7cf55972021-10-23 01:15:13 +0200163 loadables = "atf";
Marek Vasut9694c0532022-12-22 01:46:37 +0100164#endif
Marcel Ziswiler7cf55972021-10-23 01:15:13 +0200165 };
166 };
167 };
168 };
169
170 imx-boot {
171 filename = "flash.bin";
172 pad-byte = <0x00>;
173
Mamta Shuklade997212022-07-12 14:36:18 +0000174#ifdef CONFIG_FSPI_CONF_HEADER
175 fspi_conf_block {
176 filename = CONFIG_FSPI_CONF_FILE;
177 type = "blob-ext";
178 size = <0x1000>;
179 };
180
181 spl {
182 filename = "spl.bin";
183 offset = <0x1000>;
184 type = "blob-ext";
185 };
186
187 binman_uboot: uboot {
188 filename = "u-boot.itb";
189 offset = <0x58C00>;
190 type = "blob-ext";
191 };
192#else
Marcel Ziswilerf17fb6c2021-10-23 01:15:16 +0200193 spl {
Marcel Ziswiler7cf55972021-10-23 01:15:13 +0200194 filename = "spl.bin";
Marcel Ziswilerf08c3fee2021-10-23 01:15:14 +0200195 offset = <0x0>;
Marcel Ziswilerf17fb6c2021-10-23 01:15:16 +0200196 type = "blob-ext";
Marcel Ziswiler7cf55972021-10-23 01:15:13 +0200197 };
198
Marcel Ziswilerf17fb6c2021-10-23 01:15:16 +0200199 binman_uboot: uboot {
Marcel Ziswiler7cf55972021-10-23 01:15:13 +0200200 filename = "u-boot.itb";
Marcel Ziswilerf08c3fee2021-10-23 01:15:14 +0200201 offset = <0x57c00>;
Marcel Ziswilerf17fb6c2021-10-23 01:15:16 +0200202 type = "blob-ext";
Marcel Ziswiler7cf55972021-10-23 01:15:13 +0200203 };
Mamta Shuklade997212022-07-12 14:36:18 +0000204#endif
Marcel Ziswiler7cf55972021-10-23 01:15:13 +0200205 };
206};
207
Jagan Tekic1f09502021-04-26 18:23:46 +0530208&clk {
Simon Glass8c103c32023-02-13 08:56:33 -0700209 bootph-all;
210 bootph-pre-ram;
Jagan Tekic1f09502021-04-26 18:23:46 +0530211 /delete-property/ assigned-clocks;
212 /delete-property/ assigned-clock-parents;
213 /delete-property/ assigned-clock-rates;
214};
215
216&iomuxc {
Simon Glass8c103c32023-02-13 08:56:33 -0700217 bootph-pre-ram;
Jagan Tekic1f09502021-04-26 18:23:46 +0530218};
219
220&osc_24m {
Simon Glass8c103c32023-02-13 08:56:33 -0700221 bootph-all;
222 bootph-pre-ram;
Jagan Tekic1f09502021-04-26 18:23:46 +0530223};
Marcel Ziswiler24a7a3c2022-07-21 15:27:40 +0200224
Tim Harvey93cac452023-08-24 12:03:56 -0700225#ifdef CONFIG_FSL_CAAM
226&sec_jr0 {
227 bootph-pre-ram;
228};
229
230&sec_jr1 {
231 bootph-pre-ram;
232};
233
234&sec_jr2 {
235 bootph-pre-ram;
236};
237#endif
238
Marcel Ziswiler24a7a3c2022-07-21 15:27:40 +0200239&spba1 {
Simon Glass8c103c32023-02-13 08:56:33 -0700240 bootph-all;
241 bootph-pre-ram;
Marcel Ziswiler24a7a3c2022-07-21 15:27:40 +0200242};
243
244&spba2 {
Simon Glass8c103c32023-02-13 08:56:33 -0700245 bootph-all;
246 bootph-pre-ram;
Marcel Ziswiler24a7a3c2022-07-21 15:27:40 +0200247};