| Jagan Teki | 0d47bc7 | 2018-12-22 21:32:49 +0530 | [diff] [blame] | 1 | config CLK_SUNXI |
| 2 | bool "Clock support for Allwinner SoCs" |
| 3 | depends on CLK && ARCH_SUNXI |
| Jagan Teki | 99ba430 | 2019-01-18 22:18:13 +0530 | [diff] [blame] | 4 | select DM_RESET |
| Jagan Teki | 0d47bc7 | 2018-12-22 21:32:49 +0530 | [diff] [blame] | 5 | default y |
| 6 | help |
| 7 | This enables support for common clock driver API on Allwinner |
| 8 | SoCs. |
| 9 | |
| 10 | if CLK_SUNXI |
| 11 | |
| Jagan Teki | e945816 | 2018-08-02 15:43:02 +0530 | [diff] [blame^] | 12 | config CLK_SUN8I_H3 |
| 13 | bool "Clock driver for Allwinner H3/H5" |
| 14 | default MACH_SUNXI_H3_H5 |
| 15 | help |
| 16 | This enables common clock driver support for platforms based |
| 17 | on Allwinner H3/H5 SoC. |
| 18 | |
| Jagan Teki | 0d47bc7 | 2018-12-22 21:32:49 +0530 | [diff] [blame] | 19 | config CLK_SUN50I_A64 |
| 20 | bool "Clock driver for Allwinner A64" |
| 21 | default MACH_SUN50I |
| 22 | help |
| 23 | This enables common clock driver support for platforms based |
| 24 | on Allwinner A64 SoC. |
| 25 | |
| 26 | endif # CLK_SUNXI |