blob: b85244a89ad9cfeaaf7456f8679118b09b9acc06 [file] [log] [blame]
wdenk03329902003-06-20 22:36:30 +00001/*
2 * (C) Copyright 2001, 2002, 2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/* ------------------------------------------------------------------------- */
25/*
26 * Configuration settings for the A-3000 board (Artis Microsystems Inc.).
27 * http://artismicro.com
28 */
29
30/* ------------------------------------------------------------------------- */
31
32/*
33 * board/config.h - configuration options, board specific
34 */
35
36#ifndef __CONFIG_H
37#define __CONFIG_H
38
39/*
40 * High Level Configuration Options
41 * (easy to change)
42 */
43
44#define CONFIG_MPC824X 1
45#define CONFIG_MPC8245 1
46#define CONFIG_A3000 1
47
Wolfgang Denk2ae18242010-10-06 09:05:45 +020048#define CONFIG_SYS_TEXT_BASE 0xFFF00000
wdenk03329902003-06-20 22:36:30 +000049
50#define CONFIG_CONS_INDEX 1
51#define CONFIG_BAUDRATE 9600
wdenk03329902003-06-20 22:36:30 +000052
53#define CONFIG_BOOTDELAY 5
54
wdenk03329902003-06-20 22:36:30 +000055
Jon Loeliger498ff9a2007-07-05 19:13:52 -050056/*
Jon Loeliger11799432007-07-10 09:02:57 -050057 * BOOTP options
58 */
59#define CONFIG_BOOTP_BOOTFILESIZE
60#define CONFIG_BOOTP_BOOTPATH
61#define CONFIG_BOOTP_GATEWAY
62#define CONFIG_BOOTP_HOSTNAME
63
64
65/*
Jon Loeliger498ff9a2007-07-05 19:13:52 -050066 * Command line configuration.
67 */
68#include <config_cmd_default.h>
wdenk03329902003-06-20 22:36:30 +000069
70
71/*
72 * Miscellaneous configurable options
73 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020074#undef CONFIG_SYS_LONGHELP /* undef to save memory */
75#define CONFIG_SYS_PROMPT "A3000> " /* Monitor Command Prompt */
76#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk03329902003-06-20 22:36:30 +000077
78/* Print Buffer Size
79 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020080#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
81#define CONFIG_SYS_MAXARGS 8 /* Max number of command args */
82#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
83#define CONFIG_SYS_LOAD_ADDR 0x00400000 /* Default load address */
wdenk03329902003-06-20 22:36:30 +000084
85/*-----------------------------------------------------------------------
86 * PCI stuff
87 *-----------------------------------------------------------------------
88 */
89#define CONFIG_HARD_I2C 1 /* To enable I2C support */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020090#undef CONFIG_SOFT_I2C /* I2C bit-banged */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020091#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
92#define CONFIG_SYS_I2C_SLAVE 0x7F
wdenk03329902003-06-20 22:36:30 +000093
94/*-----------------------------------------------------------------------
95 * PCI stuff
96 *-----------------------------------------------------------------------
97 */
Wolfgang Denk53677ef2008-05-20 16:00:29 +020098#define CONFIG_PCI /* include pci support */
99#undef CONFIG_PCI_PNP
100#define CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */
wdenk03329902003-06-20 22:36:30 +0000101
wdenk03329902003-06-20 22:36:30 +0000102
103/* #define CONFIG_TULIP */
104/* #define CONFIG_EEPRO100 */
wdenk8bde7f72003-06-27 21:31:46 +0000105#define CONFIG_NATSEMI
wdenk03329902003-06-20 22:36:30 +0000106
107#define PCI_ENET0_IOADDR 0x80000000
108#define PCI_ENET0_MEMADDR 0x80000000
109#define PCI_ENET1_IOADDR 0x81000000
110#define PCI_ENET1_MEMADDR 0x81000000
111#define PCI_ENET2_IOADDR 0x82000000
112#define PCI_ENET2_MEMADDR 0x82000000
wdenk8564acf2003-07-14 22:13:32 +0000113#define PCI_ENET3_IOADDR 0x83000000
114#define PCI_ENET3_MEMADDR 0x83000000
wdenk03329902003-06-20 22:36:30 +0000115
116
117/*-----------------------------------------------------------------------
118 * Start addresses for the final memory configuration
119 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200120 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenk03329902003-06-20 22:36:30 +0000121 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200122#define CONFIG_SYS_SDRAM_BASE 0x00000000
wdenk03329902003-06-20 22:36:30 +0000123
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200124#define CONFIG_SYS_FLASH_BASE0_PRELIM 0xFF000000 /* FLASH bank on RCS#0 */
125#define CONFIG_SYS_FLASH_BASE1_PRELIM 0xFF000000 /* FLASH bank on RCS#1 */
126#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH_BASE0_PRELIM
127#define CONFIG_SYS_FLASH_BANKS { CONFIG_SYS_FLASH_BASE0_PRELIM }
wdenk03329902003-06-20 22:36:30 +0000128
129/* even though FLASHP_BASE is FF800000, with 4MB is RCS0, the
130 * reset vector is actually located at FFB00100, but the 8245
131 * takes care of us.
132 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200133#define CONFIG_SYS_RESET_ADDRESS 0xFFF00100
wdenk03329902003-06-20 22:36:30 +0000134
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200135#define CONFIG_SYS_EUMB_ADDR 0xFC000000
wdenk03329902003-06-20 22:36:30 +0000136
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200137#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200138#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
139#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenk03329902003-06-20 22:36:30 +0000140
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200141#define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */
142#define CONFIG_SYS_MEMTEST_END 0x02000000 /* 0 ... 32 MB in DRAM */
wdenk03329902003-06-20 22:36:30 +0000143
144 /* Maximum amount of RAM.
145 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200146#define CONFIG_SYS_MAX_RAM_SIZE 0x04000000 /* 0 .. 128 MB of (S)DRAM */
wdenk03329902003-06-20 22:36:30 +0000147
148
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200149#if CONFIG_SYS_MONITOR_BASE >= CONFIG_SYS_FLASH_BASE
150#undef CONFIG_SYS_RAMBOOT
wdenk03329902003-06-20 22:36:30 +0000151#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200152#define CONFIG_SYS_RAMBOOT
wdenk03329902003-06-20 22:36:30 +0000153#endif
154
155/*
156 * NS16550 Configuration
157 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200158#define CONFIG_SYS_NS16550
159#define CONFIG_SYS_NS16550_SERIAL
wdenk03329902003-06-20 22:36:30 +0000160
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200161#define CONFIG_SYS_NS16550_REG_SIZE 1
wdenk03329902003-06-20 22:36:30 +0000162
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200163#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
wdenk03329902003-06-20 22:36:30 +0000164
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200165#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_EUMB_ADDR + 0x4500)
166#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_EUMB_ADDR + 0x4600)
wdenk03329902003-06-20 22:36:30 +0000167
168/*-----------------------------------------------------------------------
169 * Definitions for initial stack pointer and data area
170 */
171
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200172/* #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000
Wolfgang Denk553f0982010-10-26 13:32:32 +0200174#define CONFIG_SYS_INIT_RAM_SIZE 0x1000
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200175#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
wdenk03329902003-06-20 22:36:30 +0000176
177
178/*
179 * Low Level Configuration Settings
180 * (address mappings, register initial values, etc.)
181 * You should know what you are doing if you make changes here.
182 * For the detail description refer to the MPC8240 user's manual.
183 */
184
185#define CONFIG_SYS_CLK_FREQ 33333333 /* external frequency to pll */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200186#define CONFIG_SYS_HZ 1000
wdenk03329902003-06-20 22:36:30 +0000187
188 /* Bit-field values for MCCR1.
189 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200190#define CONFIG_SYS_ROMNAL 7
191#define CONFIG_SYS_ROMFAL 11
192#define CONFIG_SYS_DBUS_SIZE 0x3
wdenk03329902003-06-20 22:36:30 +0000193
194 /* Bit-field values for MCCR2.
195 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200196#define CONFIG_SYS_TSWAIT 0x5 /* Transaction Start Wait States timer */
197#define CONFIG_SYS_REFINT 0x400 /* Refresh interval FIXME: was 0t430 */
wdenk03329902003-06-20 22:36:30 +0000198
199 /* Burst To Precharge. Bits of this value go to MCCR3 and MCCR4.
200 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200201#define CONFIG_SYS_BSTOPRE 121
wdenk03329902003-06-20 22:36:30 +0000202
203 /* Bit-field values for MCCR3.
204 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200205#define CONFIG_SYS_REFREC 8 /* Refresh to activate interval */
wdenk03329902003-06-20 22:36:30 +0000206
207 /* Bit-field values for MCCR4.
208 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200209#define CONFIG_SYS_PRETOACT 3 /* Precharge to activate interval FIXME: was 2 */
210#define CONFIG_SYS_ACTTOPRE 5 /* Activate to Precharge interval FIXME: was 5 */
211#define CONFIG_SYS_ACTORW 3 /* FIXME was 2 */
212#define CONFIG_SYS_SDMODE_CAS_LAT 3 /* SDMODE CAS latancy */
213#define CONFIG_SYS_SDMODE_WRAP 0 /* SDMODE wrap type */
214#define CONFIG_SYS_REGISTERD_TYPE_BUFFER 1
215#define CONFIG_SYS_EXTROM 1
216#define CONFIG_SYS_REGDIMM 0
wdenk03329902003-06-20 22:36:30 +0000217
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200218#define CONFIG_SYS_PGMAX 0x32 /* how long the 8240 reatins the currently accessed page in memory FIXME: was 0x32*/
wdenk03329902003-06-20 22:36:30 +0000219
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200220#define CONFIG_SYS_SDRAM_DSCD 0x20 /* SDRAM data in sample clock delay - note bottom 3 bits MUST be 0 */
wdenk03329902003-06-20 22:36:30 +0000221
222/* Memory bank settings.
223 * Only bits 20-29 are actually used from these vales to set the
224 * start/end addresses. The upper two bits will always be 0, and the lower
225 * 20 bits will be 0x00000 for a start address, or 0xfffff for an end
226 * address. Refer to the MPC8240 book.
227 */
228
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200229#define CONFIG_SYS_BANK0_START 0x00000000
230#define CONFIG_SYS_BANK0_END (CONFIG_SYS_MAX_RAM_SIZE - 1)
231#define CONFIG_SYS_BANK0_ENABLE 1
232#define CONFIG_SYS_BANK1_START 0x3ff00000
233#define CONFIG_SYS_BANK1_END 0x3fffffff
234#define CONFIG_SYS_BANK1_ENABLE 0
235#define CONFIG_SYS_BANK2_START 0x3ff00000
236#define CONFIG_SYS_BANK2_END 0x3fffffff
237#define CONFIG_SYS_BANK2_ENABLE 0
238#define CONFIG_SYS_BANK3_START 0x3ff00000
239#define CONFIG_SYS_BANK3_END 0x3fffffff
240#define CONFIG_SYS_BANK3_ENABLE 0
241#define CONFIG_SYS_BANK4_START 0x3ff00000
242#define CONFIG_SYS_BANK4_END 0x3fffffff
243#define CONFIG_SYS_BANK4_ENABLE 0
244#define CONFIG_SYS_BANK5_START 0x3ff00000
245#define CONFIG_SYS_BANK5_END 0x3fffffff
246#define CONFIG_SYS_BANK5_ENABLE 0
247#define CONFIG_SYS_BANK6_START 0x3ff00000
248#define CONFIG_SYS_BANK6_END 0x3fffffff
249#define CONFIG_SYS_BANK6_ENABLE 0
250#define CONFIG_SYS_BANK7_START 0x3ff00000
251#define CONFIG_SYS_BANK7_END 0x3fffffff
252#define CONFIG_SYS_BANK7_ENABLE 0
wdenk03329902003-06-20 22:36:30 +0000253
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200254#define CONFIG_SYS_ODCR 0xff
wdenk03329902003-06-20 22:36:30 +0000255
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200256#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
257#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
wdenk03329902003-06-20 22:36:30 +0000258
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200259#define CONFIG_SYS_IBAT1L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10 | BATL_MEMCOHERENCE)
260#define CONFIG_SYS_IBAT1U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
wdenk03329902003-06-20 22:36:30 +0000261
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200262#define CONFIG_SYS_IBAT2L (0x80000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
263#define CONFIG_SYS_IBAT2U (0x80000000 | BATU_BL_256M | BATU_VS | BATU_VP)
wdenk03329902003-06-20 22:36:30 +0000264
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200265#define CONFIG_SYS_IBAT3L (0xF0000000 | BATL_PP_10 | BATL_CACHEINHIBIT)
266#define CONFIG_SYS_IBAT3U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP)
wdenk03329902003-06-20 22:36:30 +0000267
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200268#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
269#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
270#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
271#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
272#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
273#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
274#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
275#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
wdenk03329902003-06-20 22:36:30 +0000276
277/*
278 * For booting Linux, the board info and command line data
279 * have to be in the first 8 MB of memory, since this is
280 * the maximum mapped by the Linux kernel during initialization.
281 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200282#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenk03329902003-06-20 22:36:30 +0000283
284/*-----------------------------------------------------------------------
285 * FLASH organization
286 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200287#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of flash banks */
288#define CONFIG_SYS_MAX_FLASH_SECT 128 /* Max number of sectors per flash */
wdenk03329902003-06-20 22:36:30 +0000289
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200290#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
291#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
wdenk03329902003-06-20 22:36:30 +0000292
293
294 /* Warining: environment is not EMBEDDED in the U-Boot code.
295 * It's stored in flash separately.
296 */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200297#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200298#define CONFIG_ENV_ADDR 0xFFFE0000
299#define CONFIG_ENV_SIZE 0x00020000 /* Size of the Environment */
300#define CONFIG_ENV_SECT_SIZE 0x00020000 /* Size of the Environment Sector */
wdenk03329902003-06-20 22:36:30 +0000301
302/*-----------------------------------------------------------------------
303 * Cache Configuration
304 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200305#define CONFIG_SYS_CACHELINE_SIZE 32
Jon Loeliger498ff9a2007-07-05 19:13:52 -0500306#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200307# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
wdenk03329902003-06-20 22:36:30 +0000308#endif
309
wdenk03329902003-06-20 22:36:30 +0000310#endif /* __CONFIG_H */