| Fabien Parent | e96bedf | 2021-02-15 19:21:12 +0100 | [diff] [blame^] | 1 | // SPDX-License-Identifier: GPL-2.0 OR MIT |
| 2 | /* |
| 3 | * Copyright (C) 2021 BayLibre SAS. |
| 4 | * Author: Fabien Parent <fparent@baylibre.com> |
| 5 | */ |
| 6 | |
| 7 | /dts-v1/; |
| 8 | |
| 9 | #include <config.h> |
| 10 | #include "mt8183.dtsi" |
| 11 | |
| 12 | / { |
| 13 | model = "MediaTek MT8183 pumpkin board"; |
| 14 | compatible = "mediatek,mt8183-pumpkin", "mediatek,mt8183"; |
| 15 | |
| 16 | memory@40000000 { |
| 17 | device_type = "memory"; |
| 18 | reg = <0 0x40000000 0 0x80000000>; |
| 19 | }; |
| 20 | |
| 21 | reserved-memory { |
| 22 | #address-cells = <2>; |
| 23 | #size-cells = <2>; |
| 24 | ranges; |
| 25 | |
| 26 | /* 192 KiB reserved for ARM Trusted Firmware (BL31) */ |
| 27 | bl31_secmon_reserved: secmon@54600000 { |
| 28 | no-map; |
| 29 | reg = <0 0x54600000 0x0 0x30000>; |
| 30 | }; |
| 31 | |
| 32 | /* 12 MiB reserved for OP-TEE (BL32) |
| 33 | * +-----------------------+ 0x43e0_0000 |
| 34 | * | SHMEM 2MiB | |
| 35 | * +-----------------------+ 0x43c0_0000 |
| 36 | * | | TA_RAM 8MiB | |
| 37 | * + TZDRAM +--------------+ 0x4340_0000 |
| 38 | * | | TEE_RAM 2MiB | |
| 39 | * +-----------------------+ 0x4320_0000 |
| 40 | */ |
| 41 | optee_reserved: optee@43200000 { |
| 42 | no-map; |
| 43 | reg = <0 0x43200000 0 0x00c00000>; |
| 44 | }; |
| 45 | }; |
| 46 | |
| 47 | chosen { |
| 48 | stdout-path = &uart0; |
| 49 | }; |
| 50 | |
| 51 | reg_1p8v: regulator-1p8v { |
| 52 | compatible = "regulator-fixed"; |
| 53 | regulator-name = "fixed-1.8V"; |
| 54 | regulator-min-microvolt = <1800000>; |
| 55 | regulator-max-microvolt = <1800000>; |
| 56 | regulator-boot-on; |
| 57 | regulator-always-on; |
| 58 | }; |
| 59 | |
| 60 | reg_3p3v: regulator-3p3v { |
| 61 | compatible = "regulator-fixed"; |
| 62 | regulator-name = "fixed-3.3V"; |
| 63 | regulator-min-microvolt = <3300000>; |
| 64 | regulator-max-microvolt = <3300000>; |
| 65 | regulator-boot-on; |
| 66 | regulator-always-on; |
| 67 | }; |
| 68 | }; |
| 69 | |
| 70 | &watchdog { |
| 71 | status = "okay"; |
| 72 | }; |
| 73 | |
| 74 | &uart0 { |
| 75 | status = "okay"; |
| 76 | }; |
| 77 | |
| 78 | &mmc0 { |
| 79 | bus-width = <4>; |
| 80 | max-frequency = <200000000>; |
| 81 | cap-mmc-highspeed; |
| 82 | mmc-hs200-1_8v; |
| 83 | cap-mmc-hw-reset; |
| 84 | vmmc-supply = <®_3p3v>; |
| 85 | vqmmc-supply = <®_1p8v>; |
| 86 | non-removable; |
| 87 | status = "okay"; |
| 88 | }; |
| 89 | |
| 90 | &usb { |
| 91 | status = "okay"; |
| 92 | }; |
| 93 | |
| 94 | &ssusb { |
| 95 | mediatek,force-vbus; |
| 96 | maximum-speed = "high-speed"; |
| 97 | dr_mode = "peripheral"; |
| 98 | status = "okay"; |
| 99 | }; |