blob: 758e85e89df701dca3a14d0a603bab743e26c8f9 [file] [log] [blame]
Tom Rini83d290c2018-05-06 17:58:06 -04001/* SPDX-License-Identifier: GPL-2.0+ */
Andy Yan2c1e11d2017-06-01 18:00:55 +08002/*
3 * (C) Copyright 2016 Rockchip Electronics Co., Ltd
Andy Yan2c1e11d2017-06-01 18:00:55 +08004 */
5#ifndef __CONFIG_RV1108_COMMON_H
6#define __CONFIG_RV1108_COMMON_H
7
Kever Yang15f09a12019-03-28 11:01:23 +08008#include <asm/arch-rockchip/hardware.h>
Andy Yan2c1e11d2017-06-01 18:00:55 +08009#include "rockchip-common.h"
10
Kever Yang5f246802019-07-22 19:59:09 +080011#define CONFIG_IRAM_BASE 0x10080000
12
Andy Yan2c1e11d2017-06-01 18:00:55 +080013#define CONFIG_SYS_CBSIZE 1024
14#define CONFIG_SKIP_LOWLEVEL_INIT
15
16#define CONFIG_SYS_TIMER_RATE (24 * 1000 * 1000)
17/* TIMER1,initialized by ddr initialize code */
18#define CONFIG_SYS_TIMER_BASE 0x10350020
19#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8)
20
Andy Yan2c1e11d2017-06-01 18:00:55 +080021#define CONFIG_SYS_SDRAM_BASE 0x60000000
Andy Yan2c1e11d2017-06-01 18:00:55 +080022#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_TEXT_BASE + 0x100000)
23#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x2000000)
24
William Wucbeedaf2017-08-09 11:36:27 +080025/* rockchip ohci host driver */
26#define CONFIG_USB_OHCI_NEW
27#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1
Andy Yan2c1e11d2017-06-01 18:00:55 +080028#endif
Otavio Salvadord3f4bce2018-11-30 11:34:17 -020029
30#ifndef CONFIG_SPL_BUILD
31#define ENV_MEM_LAYOUT_SETTINGS \
32 "scriptaddr=0x60000000\0" \
33 "fdt_addr_r=0x61f00000\0" \
34 "kernel_addr_r=0x62000000\0" \
35 "ramdisk_addr_r=0x64000000\0"
36
37#include <config_distro_bootcmd.h>
38#define CONFIG_EXTRA_ENV_SETTINGS \
39 ENV_MEM_LAYOUT_SETTINGS \
40 "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
41 "partitions=" PARTS_DEFAULT \
42 BOOTENV
43#endif