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wdenke2211742002-11-02 23:30:20 +00001/*
2 * (C) Copyright 2002 ELTEC Elektronik AG
3 * Frank Gottschling <fgottschling@eltec.de>
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
wdenke2211742002-11-02 23:30:20 +000031#define GTREGREAD(x) 0xffffffff /* needed for debug */
32
33/*
34 * High Level Configuration Options
35 * (easy to change)
36 */
37
Wolfgang Denk2ae18242010-10-06 09:05:45 +020038#define CONFIG_SYS_TEXT_BASE 0xFFF00000
39
wdenke2211742002-11-02 23:30:20 +000040/* these hardware addresses are pretty bogus, please change them to
41 suit your needs */
42
43/* first ethernet */
44#define CONFIG_ETHADDR 00:00:5b:ee:de:ad
45
46#define CONFIG_IPADDR 192.168.0.105
47#define CONFIG_SERVERIP 192.168.0.100
48
49#define CONFIG_BAB7xx 1 /* this is an BAB740/BAB750 board */
50
51#define CONFIG_BAUDRATE 9600 /* console baudrate */
52
53#undef CONFIG_WATCHDOG
54
55#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
56
57#define CONFIG_ZERO_BOOTDELAY_CHECK
58
59#undef CONFIG_BOOTARGS
60#define CONFIG_BOOTCOMMAND \
61 "bootp 1000000; " \
62 "setenv bootargs root=ramfs console=ttyS00,9600 " \
Wolfgang Denkfe126d82005-11-20 21:40:11 +010063 "ip=${ipaddr}:${serverip}:${rootpath}:${gatewayip}:" \
64 "${netmask}:${hostname}:eth0:none; " \
wdenke2211742002-11-02 23:30:20 +000065 "bootm"
66
67#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020068#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate changes */
wdenke2211742002-11-02 23:30:20 +000069
Jon Loeliger5d2ebe12007-07-09 21:16:53 -050070/*
71 * BOOTP options
72 */
73#define CONFIG_BOOTP_SUBNETMASK
74#define CONFIG_BOOTP_GATEWAY
75#define CONFIG_BOOTP_HOSTNAME
76#define CONFIG_BOOTP_BOOTPATH
77
78#define CONFIG_BOOTP_BOOTFILESIZE
79
wdenke2211742002-11-02 23:30:20 +000080
Jon Loeligerde8b2a62007-07-05 19:32:07 -050081/*
82 * Command line configuration.
83 */
84#include <config_cmd_default.h>
wdenke2211742002-11-02 23:30:20 +000085
Jon Loeligerde8b2a62007-07-05 19:32:07 -050086#define CONFIG_CMD_PCI
87#define CONFIG_CMD_JFFS2
Wolfgang Denk5728be32007-08-06 01:01:49 +020088#define CONFIG_CMD_SCSI
Jon Loeligerde8b2a62007-07-05 19:32:07 -050089#define CONFIG_CMD_IDE
Wolfgang Denk5728be32007-08-06 01:01:49 +020090#define CONFIG_CMD_DATE
91#define CONFIG_CMD_FDC
Jon Loeligerde8b2a62007-07-05 19:32:07 -050092#define CONFIG_CMD_ELF
93
wdenke2211742002-11-02 23:30:20 +000094
95/*
96 * Miscellaneous configurable options
97 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020098#define CONFIG_SYS_LONGHELP /* undef to save memory */
99#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
wdenke2211742002-11-02 23:30:20 +0000100
101/*
102 * choose between COM1 and COM2 as serial console
103 */
104#define CONFIG_CONS_INDEX 1
105
Jon Loeligerde8b2a62007-07-05 19:32:07 -0500106#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200107#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenke2211742002-11-02 23:30:20 +0000108#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200109#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenke2211742002-11-02 23:30:20 +0000110#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200111#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
112#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
113#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenke2211742002-11-02 23:30:20 +0000114
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200115#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */
116#define CONFIG_SYS_MEMTEST_END 0x04000000 /* 0 ... 64 MB in DRAM */
wdenke2211742002-11-02 23:30:20 +0000117
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200118#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */
wdenke2211742002-11-02 23:30:20 +0000119
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200120#define CONFIG_SYS_HZ 1000 /* dec. freq: 1 ms ticks */
wdenke2211742002-11-02 23:30:20 +0000121
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200122#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
wdenke2211742002-11-02 23:30:20 +0000123
124/*
125 * Low Level Configuration Settings
126 * (address mappings, register initial values, etc.)
127 * You should know what you are doing if you make changes here.
128 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200129#define CONFIG_SYS_BOARD_ASM_INIT
wdenke2211742002-11-02 23:30:20 +0000130#define CONFIG_MISC_INIT_R
131
132/*
133 * Choose the address mapping scheme for the MPC106 mem controller.
134 * Default is mapping B (CHRP), set this define to choose mapping A (PReP).
135 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200136#define CONFIG_SYS_ADDRESS_MAP_A
137#ifdef CONFIG_SYS_ADDRESS_MAP_A
wdenke2211742002-11-02 23:30:20 +0000138
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200139#define CONFIG_SYS_PCI_MEMORY_BUS 0x80000000
140#define CONFIG_SYS_PCI_MEMORY_PHYS 0x00000000
141#define CONFIG_SYS_PCI_MEMORY_SIZE 0x80000000
wdenke2211742002-11-02 23:30:20 +0000142
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200143#define CONFIG_SYS_PCI_MEM_BUS 0x00000000
144#define CONFIG_SYS_PCI_MEM_PHYS 0xc0000000
145#define CONFIG_SYS_PCI_MEM_SIZE 0x3f000000
wdenke2211742002-11-02 23:30:20 +0000146
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200147#define CONFIG_SYS_ISA_MEM_BUS 0
148#define CONFIG_SYS_ISA_MEM_PHYS 0
149#define CONFIG_SYS_ISA_MEM_SIZE 0
wdenke2211742002-11-02 23:30:20 +0000150
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200151#define CONFIG_SYS_PCI_IO_BUS 0x1000
152#define CONFIG_SYS_PCI_IO_PHYS 0x81000000
153#define CONFIG_SYS_PCI_IO_SIZE 0x01000000-CONFIG_SYS_PCI_IO_BUS
wdenke2211742002-11-02 23:30:20 +0000154
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200155#define CONFIG_SYS_ISA_IO_BUS 0x00000000
156#define CONFIG_SYS_ISA_IO_PHYS 0x80000000
157#define CONFIG_SYS_ISA_IO_SIZE 0x00800000
wdenke2211742002-11-02 23:30:20 +0000158
159#else
160
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200161#define CONFIG_SYS_PCI_MEMORY_BUS 0x00000000
162#define CONFIG_SYS_PCI_MEMORY_PHYS 0x00000000
163#define CONFIG_SYS_PCI_MEMORY_SIZE 0x40000000
wdenke2211742002-11-02 23:30:20 +0000164
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200165#define CONFIG_SYS_PCI_MEM_BUS 0x80000000
166#define CONFIG_SYS_PCI_MEM_PHYS 0x80000000
167#define CONFIG_SYS_PCI_MEM_SIZE 0x7d000000
wdenke2211742002-11-02 23:30:20 +0000168
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200169#define CONFIG_SYS_ISA_MEM_BUS 0x00000000
170#define CONFIG_SYS_ISA_MEM_PHYS 0xfd000000
171#define CONFIG_SYS_ISA_MEM_SIZE 0x01000000
wdenke2211742002-11-02 23:30:20 +0000172
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200173#define CONFIG_SYS_PCI_IO_BUS 0x00800000
174#define CONFIG_SYS_PCI_IO_PHYS 0xfe800000
175#define CONFIG_SYS_PCI_IO_SIZE 0x00400000
wdenke2211742002-11-02 23:30:20 +0000176
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200177#define CONFIG_SYS_ISA_IO_BUS 0x00000000
178#define CONFIG_SYS_ISA_IO_PHYS 0xfe000000
179#define CONFIG_SYS_ISA_IO_SIZE 0x00800000
wdenke2211742002-11-02 23:30:20 +0000180
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200181#endif /*CONFIG_SYS_ADDRESS_MAP_A */
wdenke2211742002-11-02 23:30:20 +0000182
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200183#define CONFIG_SYS_60X_PCI_MEM_OFFSET 0x00000000
wdenke2211742002-11-02 23:30:20 +0000184
185/* driver defines FDC,IDE,... */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200186#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_ISA_IO_PHYS
187#define CONFIG_SYS_ISA_IO CONFIG_SYS_ISA_IO_PHYS
188#define CONFIG_SYS_60X_PCI_IO_OFFSET CONFIG_SYS_ISA_IO_PHYS
wdenke2211742002-11-02 23:30:20 +0000189
190/*
191 * Start addresses for the final memory configuration
192 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200193 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenke2211742002-11-02 23:30:20 +0000194 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200195#define CONFIG_SYS_SDRAM_BASE 0x00000000
196#define CONFIG_SYS_FLASH_BASE 0xfff00000
wdenke2211742002-11-02 23:30:20 +0000197
198/*
199 * Definitions for initial stack pointer and data area
200 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200201#define CONFIG_SYS_INIT_RAM_ADDR 0x00fd0000 /* above the memtest region */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200202#define CONFIG_SYS_INIT_RAM_SIZE 0x4000
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200203#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200204#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenke2211742002-11-02 23:30:20 +0000205
206/*
207 * Flash mapping/organization on the MPC10x.
208 */
209#define FLASH_BASE0_PRELIM 0xff800000
210#define FLASH_BASE1_PRELIM 0xffc00000
211
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200212#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
213#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
wdenke2211742002-11-02 23:30:20 +0000214
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200215#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
216#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
wdenke2211742002-11-02 23:30:20 +0000217
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200218/*
219 * JFFS2 partitions
220 *
221 */
222/* No command line, one static partition */
Stefan Roese68d7d652009-03-19 13:30:36 +0100223#undef CONFIG_CMD_MTDPARTS
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200224#define CONFIG_JFFS2_DEV "nor"
225#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF
226#define CONFIG_JFFS2_PART_OFFSET 0x00000000
227
228/* mtdparts command line support
229 *
230 * Note: fake mtd_id used, no linux mtd map file
231 */
232/*
Stefan Roese68d7d652009-03-19 13:30:36 +0100233#define CONFIG_CMD_MTDPARTS
Wolfgang Denk700a0c62005-08-08 01:03:24 +0200234#define MTDIDS_DEFAULT "nor0=bab7xx-0"
235#define MTDPARTS_DEFAULT "mtdparts=bab7xx-0:-(jffs2)"
236*/
wdenke2211742002-11-02 23:30:20 +0000237
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200238#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
239#define CONFIG_SYS_MONITOR_LEN 0x40000 /* Reserve 256 kB for Monitor */
240#define CONFIG_SYS_MALLOC_LEN 0x20000 /* Reserve 128 kB for malloc() */
241#undef CONFIG_SYS_MEMTEST
wdenke2211742002-11-02 23:30:20 +0000242
243/*
244 * Environment settings
245 */
246#define CONFIG_ENV_OVERWRITE
Jean-Christophe PLAGNIOL-VILLARD9314cee2008-09-10 22:47:59 +0200247#define CONFIG_ENV_IS_IN_NVRAM 1 /* use NVRAM for environment vars */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200248#define CONFIG_SYS_NVRAM_SIZE 0x1ff0 /* NVRAM size (8kB), we must protect the clock data (16 bytes) */
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200249#define CONFIG_ENV_SIZE 0x400 /* Size of Environment vars (1kB) */
wdenke2211742002-11-02 23:30:20 +0000250/*
251 * We store the environment and an image of revision eeprom in the upper part of the NVRAM. Thus,
252 * user applications can use the remaining space for other purposes.
253 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200254#define CONFIG_ENV_ADDR (CONFIG_SYS_NVRAM_SIZE +0x10 -0x800)
255#define CONFIG_SYS_NV_SROM_COPY_ADDR (CONFIG_SYS_NVRAM_SIZE +0x10 -0x400)
256#define CONFIG_SYS_NVRAM_ACCESS_ROUTINE /* This board needs a special routine to access the NVRAM */
257#define CONFIG_SYS_SROM_SIZE 0x100 /* shadow of revision info is in nvram */
wdenke2211742002-11-02 23:30:20 +0000258
259/*
260 * Serial devices
261 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200262#define CONFIG_SYS_NS16550
263#define CONFIG_SYS_NS16550_SERIAL
264#define CONFIG_SYS_NS16550_REG_SIZE 1
265#define CONFIG_SYS_NS16550_CLK 1843200
266#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_ISA_IO + CONFIG_SYS_NS87308_UART1_BASE)
267#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_ISA_IO + CONFIG_SYS_NS87308_UART2_BASE)
wdenke2211742002-11-02 23:30:20 +0000268
269/*
270 * PCI stuff
271 */
272#define CONFIG_PCI /* include pci support */
Andre Schwarz76221a62010-10-05 11:59:31 +0200273#define CONFIG_SYS_EARLY_PCI_INIT
wdenke2211742002-11-02 23:30:20 +0000274#define CONFIG_PCI_PNP /* pci plug-and-play */
275#define CONFIG_PCI_HOST PCI_HOST_AUTO
276#undef CONFIG_PCI_SCAN_SHOW
277
278/*
279 * Video console (graphic: SMI LynxEM, keyboard: i8042)
280 */
281#define CONFIG_VIDEO
282#define CONFIG_CFB_CONSOLE
283#define CONFIG_VIDEO_SMI_LYNXEM
284#define CONFIG_I8042_KBD
285#define CONFIG_VIDEO_LOGO
286#define CONFIG_CONSOLE_TIME
287#define CONFIG_CONSOLE_EXTRA_INFO
288#define CONFIG_CONSOLE_CURSOR
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200289#define CONFIG_SYS_CONSOLE_BLINK_COUNT 30000 /* approx. 2 HZ */
wdenke2211742002-11-02 23:30:20 +0000290
291/*
292 * IDE/SCSI globals
293 */
294#ifndef __ASSEMBLY__
295extern unsigned int eltec_board;
296extern unsigned int ata_reset_time;
297extern unsigned int scsi_reset_time;
298extern unsigned short scsi_dev_id;
299extern unsigned int scsi_max_scsi_id;
300extern unsigned char scsi_sym53c8xx_ccf;
301#endif
302
303/*
304 * ATAPI Support (experimental)
305 */
306#define CONFIG_ATAPI
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200307#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 2 IDE busses */
308#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */
wdenke2211742002-11-02 23:30:20 +0000309
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200310#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_60X_PCI_IO_OFFSET /* base address */
311#define CONFIG_SYS_ATA_IDE0_OFFSET 0x1F0 /* default ide0 offste */
312#define CONFIG_SYS_ATA_IDE1_OFFSET 0x170 /* default ide1 offset */
313#define CONFIG_SYS_ATA_DATA_OFFSET 0 /* data reg offset */
314#define CONFIG_SYS_ATA_REG_OFFSET 0 /* reg offset */
315#define CONFIG_SYS_ATA_ALT_OFFSET 0x200 /* alternate register offset */
wdenke2211742002-11-02 23:30:20 +0000316
317#define ATA_RESET_TIME (ata_reset_time)
318
319#undef CONFIG_IDE_PCMCIA /* no pcmcia interface required */
320#undef CONFIG_IDE_LED /* no led for ide supported */
321
322/*
323 * SCSI support (experimental) only SYM53C8xx supported
324 */
325#define CONFIG_SCSI_SYM53C8XX
326#define CONFIG_SCSI_DEV_ID (scsi_dev_id) /* 875 or 860 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200327#define CONFIG_SYS_SCSI_SYM53C8XX_CCF (scsi_sym53c8xx_ccf) /* value for none 40 mhz clocks */
328#define CONFIG_SYS_SCSI_MAX_LUN 8 /* number of supported LUNs */
329#define CONFIG_SYS_SCSI_MAX_SCSI_ID (scsi_max_scsi_id) /* max SCSI ID (0-6) */
330#define CONFIG_SYS_SCSI_MAX_DEVICE (15 * CONFIG_SYS_SCSI_MAX_LUN) /* max. Target devices */
331#define CONFIG_SYS_SCSI_SPIN_UP_TIME (scsi_reset_time)
wdenke2211742002-11-02 23:30:20 +0000332
333/*
334 * Partion suppport
335 */
336#define CONFIG_DOS_PARTITION
337#define CONFIG_MAC_PARTITION
338#define CONFIG_ISO_PARTITION
339
340/*
341 * Winbond Configuration
342 */
Jean-Christophe PLAGNIOL-VILLARDab6878c2008-08-13 01:40:40 +0200343#define CONFIG_WINBOND_83C553 1 /* has a winbond bridge */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200344#define CONFIG_SYS_USE_WINBOND_IDE 0 /* use winbond 83c553 internal ide */
345#define CONFIG_SYS_WINBOND_ISA_CFG_ADDR 0x80005800 /* pci-isa bridge config addr */
346#define CONFIG_SYS_WINBOND_IDE_CFG_ADDR 0x80005900 /* ide config addr */
wdenke2211742002-11-02 23:30:20 +0000347
348/*
349 * NS87308 Configuration
350 */
Jean-Christophe PLAGNIOL-VILLARD55d6d2d2008-08-13 01:40:40 +0200351#define CONFIG_NS87308 /* Nat Semi super-io cntr on ISA bus */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200352#define CONFIG_SYS_NS87308_BADDR_10 1
353#define CONFIG_SYS_NS87308_DEVS (CONFIG_SYS_NS87308_UART1 | \
354 CONFIG_SYS_NS87308_UART2 | \
355 CONFIG_SYS_NS87308_KBC1 | \
356 CONFIG_SYS_NS87308_MOUSE | \
357 CONFIG_SYS_NS87308_FDC | \
358 CONFIG_SYS_NS87308_RARP | \
359 CONFIG_SYS_NS87308_GPIO | \
360 CONFIG_SYS_NS87308_POWRMAN | \
361 CONFIG_SYS_NS87308_RTC_APC )
wdenke2211742002-11-02 23:30:20 +0000362
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200363#define CONFIG_SYS_NS87308_PS2MOD
364#define CONFIG_SYS_NS87308_GPIO_BASE 0x0220
365#define CONFIG_SYS_NS87308_PWMAN_BASE 0x0460
366#define CONFIG_SYS_NS87308_PMC2 0x00 /* SuperI/O clock source is 24MHz via X1 */
wdenke2211742002-11-02 23:30:20 +0000367
368/*
369 * set up the NVRAM access registers
370 * NVRAM's controlled by the configurable CS line from the 87308
371 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200372#define CONFIG_SYS_NS87308_CS0_BASE 0x0076
373#define CONFIG_SYS_NS87308_CS0_CONF 0x40
374#define CONFIG_SYS_NS87308_CS1_BASE 0x0070
375#define CONFIG_SYS_NS87308_CS1_CONF 0x1C
376#define CONFIG_SYS_NS87308_CS2_BASE 0x0071
377#define CONFIG_SYS_NS87308_CS2_CONF 0x1C
wdenke2211742002-11-02 23:30:20 +0000378
379#define CONFIG_RTC_MK48T59
380
381/*
382 * Initial BATs
383 */
384#if 1
385
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200386#define CONFIG_SYS_IBAT0L 0
387#define CONFIG_SYS_IBAT0U 0
388#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT1L
389#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT1U
wdenke2211742002-11-02 23:30:20 +0000390
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200391#define CONFIG_SYS_IBAT1L 0
392#define CONFIG_SYS_IBAT1U 0
393#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
394#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
wdenke2211742002-11-02 23:30:20 +0000395
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200396#define CONFIG_SYS_IBAT2L 0
397#define CONFIG_SYS_IBAT2U 0
398#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
399#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
wdenke2211742002-11-02 23:30:20 +0000400
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200401#define CONFIG_SYS_IBAT3L 0
402#define CONFIG_SYS_IBAT3U 0
403#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
404#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
wdenke2211742002-11-02 23:30:20 +0000405
406#else
407
408/* SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200409#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE | BATL_RW)
410#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP)
411#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT1L
412#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT1U
wdenke2211742002-11-02 23:30:20 +0000413
414/* address range for flashes */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200415#define CONFIG_SYS_IBAT1L (CONFIG_SYS_FLASH_BASE | BATL_RW | BATL_CACHEINHIBIT)
416#define CONFIG_SYS_IBAT1U (CONFIG_SYS_FLASH_BASE | BATU_BL_16M | BATU_VS | BATU_VP)
417#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
418#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
wdenke2211742002-11-02 23:30:20 +0000419
420/* ISA IO space */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200421#define CONFIG_SYS_IBAT2L (CONFIG_SYS_ISA_IO | BATL_RW | BATL_CACHEINHIBIT)
422#define CONFIG_SYS_IBAT2U (CONFIG_SYS_ISA_IO | BATU_BL_16M | BATU_VS | BATU_VP)
423#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
424#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
wdenke2211742002-11-02 23:30:20 +0000425
426/* ISA memory space */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200427#define CONFIG_SYS_IBAT3L (CONFIG_SYS_ISA_MEM | BATL_RW | BATL_CACHEINHIBIT)
428#define CONFIG_SYS_IBAT3U (CONFIG_SYS_ISA_MEM | BATU_BL_16M | BATU_VS | BATU_VP)
429#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
430#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
wdenke2211742002-11-02 23:30:20 +0000431
432#endif
433
434/*
435 * Speed settings are board specific
436 */
437#ifndef __ASSEMBLY__
438extern unsigned long bab7xx_get_bus_freq (void);
439extern unsigned long bab7xx_get_gclk_freq (void);
440#endif
Wolfgang Denkee80fa72010-06-13 18:38:23 +0200441#define CONFIG_SYS_BUS_CLK bab7xx_get_bus_freq()
442#define CONFIG_SYS_CPU_CLK bab7xx_get_gclk_freq()
wdenke2211742002-11-02 23:30:20 +0000443
444/*
445 * For booting Linux, the board info and command line data
446 * have to be in the first 8 MB of memory, since this is
447 * the maximum mapped by the Linux kernel during initialization.
448 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200449#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenke2211742002-11-02 23:30:20 +0000450
451/*
452 * Cache Configuration
453 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200454#define CONFIG_SYS_CACHELINE_SIZE 32 /* For all MPC74xx CPUs */
Jon Loeligerde8b2a62007-07-05 19:32:07 -0500455#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200456#define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
wdenke2211742002-11-02 23:30:20 +0000457#endif
458
459/*
460 * L2 Cache Configuration is board specific for BAB740/BAB750
461 * Init values read from revision srom.
462 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200463#undef CONFIG_SYS_L2
wdenke2211742002-11-02 23:30:20 +0000464#define L2_INIT (L2CR_L2SIZ_HM | L2CR_L2CLK_3 | L2CR_L2RAM_BURST | \
wdenk8bde7f72003-06-27 21:31:46 +0000465 L2CR_L2OH_5 | L2CR_L2CTL | L2CR_L2WT)
wdenke2211742002-11-02 23:30:20 +0000466#define L2_ENABLE (L2_INIT | L2CR_L2E)
467
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200468#define CONFIG_SYS_L2_BAB7xx
wdenke2211742002-11-02 23:30:20 +0000469
wdenke2211742002-11-02 23:30:20 +0000470#define CONFIG_TULIP
471#define CONFIG_TULIP_SELECT_MEDIA
472
473#endif /* __CONFIG_H */