blob: 57336f9fc80178a0e0281945ff3d8afc1f5b35c3 [file] [log] [blame]
wdenk5b1d7132002-11-03 00:07:02 +00001 /*
2 * A collection of structures, addresses, and values associated with
3 * the Motorola 860T FADS board. Copied from the MBX stuff.
4 * Magnus Damm added defines for 8xxrom and extended bd_info.
5 * Helmut Buchsbaum added bitvalues for BCSRx
6 *
7 * Copyright (c) 1998 Dan Malek (dmalek@jlc.net)
8 */
9
10/*
11 * 1999-nov-26: The FADS is using the following physical memorymap:
12 *
13 * ff020000 -> ff02ffff : pcmcia io remapping
14 * ff010000 -> ff01ffff : BCSR connected to CS1, setup by U-Boot
15 * ff000000 -> ff00ffff : IMAP internal in the cpu
16 * e0000000 -> f3ffffff : pcmcia memory remapping by m8xx_pcmcia
17 * fe000000 -> fe1fffff : flash connected to CS0, setup by U-Boot
18 * 00000000 -> nnnnnnnn : sdram/dram setup by U-Boot
19*/
20
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020021#define CONFIG_SYS_PCMCIA_IO_ADDR 0xff020000
22#define CONFIG_SYS_PCMCIA_IO_SIZE 0x10000
23#define CONFIG_SYS_PCMCIA_MEM_ADDR 0xe0000000
24#define CONFIG_SYS_PCMCIA_MEM_SIZE 0x10000
25#define CONFIG_SYS_IMMR 0xFF000000
26#define CONFIG_SYS_SDRAM_SIZE (4<<20) /* standard FADS has 4M */
27#define CONFIG_SYS_SDRAM_BASE 0x00000000
28#define CONFIG_SYS_FLASH_BASE 0x02800000
wdenk5b1d7132002-11-03 00:07:02 +000029#define BCSR_ADDR ((uint) 0xff010000)
30#define FLASH_BASE0_PRELIM 0x02800000 /* FLASH bank #0 */
31
32/* ------------------------------------------------------------------------- */
33
34/*
35 * board/config.h - configuration options, board specific
36 */
37
38#ifndef __CONFIG_H
39#define __CONFIG_H
40
Wolfgang Denk2ae18242010-10-06 09:05:45 +020041#define CONFIG_SYS_TEXT_BASE 0xFE000000
42
wdenk5b1d7132002-11-03 00:07:02 +000043#define CONFIG_ETHADDR 08:00:22:50:70:63 /* Ethernet address */
44#define CONFIG_ENV_OVERWRITE 1 /* Overwrite the environment */
45
46#define CONFIG_VIDEO 1 /* To enable video controller support */
47#define CONFIG_HARD_I2C 1 /* To I2C with hardware support */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020048#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
49#define CONFIG_SYS_I2C_SLAVE 0x7F
wdenk5b1d7132002-11-03 00:07:02 +000050
wdenk5b1d7132002-11-03 00:07:02 +000051/*#define CONFIG_PCMCIA 1 / * To enable PCMCIA support */
52
53/* Video related */
54
55#define CONFIG_VIDEO_LOGO 1 /* Show the logo */
56#define CONFIG_VIDEO_ENCODER_AD7176 1 /* Enable this encoder */
57#define CONFIG_VIDEO_ENCODER_AD7176_ADDR 0x54 /* Default on fads */
58#define CONFIG_VIDEO_SIZE (2*1024*1024)
59/* #define CONFIG_VIDEO_ADDR (gd->bd->bi_memsize - CONFIG_VIDEO_SIZE) Frame buffer address */
60
61/* Wireless 56Khz 4PPM keyboard on SMCx */
62
wdenk682011f2003-06-03 23:54:09 +000063/*#define CONFIG_KEYBOARD 1 */
wdenk5b1d7132002-11-03 00:07:02 +000064#define CONFIG_WL_4PPM_KEYBOARD_SMC 0 /* SMC to use (0 indexed) */
65
66/*
67 * High Level Configuration Options
68 * (easy to change)
69 */
wdenk5b1d7132002-11-03 00:07:02 +000070#define CONFIG_MPC823 1
71#define CONFIG_MPC823FADS 1
72#define CONFIG_FADS 1
73
74#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
75#undef CONFIG_8xx_CONS_SMC2
76#undef CONFIG_8xx_CONS_NONE
77#define CONFIG_BAUDRATE 115200
78
79/* Set the CPU speed to 50Mhz on the FADS */
80
81#if 0
82#define MPC8XX_FACT 10 /* Multiply by 10 */
83#define MPC8XX_XIN 5000000 /* 5 MHz in */
84#else
85#define MPC8XX_FACT 10 /* Multiply by 10 */
86#define MPC8XX_XIN 5000000 /* 5 MHz in */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020087#define CONFIG_SYS_PLPRCR_MF (MPC8XX_FACT-1) << 20 /* From 0 to 4095 */
wdenk5b1d7132002-11-03 00:07:02 +000088#endif
89#define MPC8XX_HZ ((MPC8XX_XIN) * (MPC8XX_FACT))
90
91#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
92
93#if 1
94#define CONFIG_BOOTDELAY 2 /* autoboot after 2 seconds */
95#define CONFIG_LOADS_ECHO 0 /* Dont echoes received characters */
96#define CONFIG_BOOTARGS ""
97#define CONFIG_BOOTCOMMAND \
Wolfgang Denk53677ef2008-05-20 16:00:29 +020098"bootp ;" \
99"setenv bootargs console=tty0 console=ttyS0 " \
100"root=/dev/nfs nfsroot=${serverip}:${rootpath} " \
101"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}:eth0:off ;" \
wdenk5b1d7132002-11-03 00:07:02 +0000102"bootm"
103#else
104#define CONFIG_BOOTDELAY 0 /* autoboot disabled */
105#endif
106
107#undef CONFIG_WATCHDOG /* watchdog disabled */
108
Jon Loeliger5d2ebe12007-07-09 21:16:53 -0500109
110/*
111 * BOOTP options
112 */
113#define CONFIG_BOOTP_SUBNETMASK
114#define CONFIG_BOOTP_GATEWAY
115#define CONFIG_BOOTP_HOSTNAME
116#define CONFIG_BOOTP_BOOTPATH
117#define CONFIG_BOOTP_BOOTFILESIZE
118#define CONFIG_BOOTP_SUBNETMASK
119#define CONFIG_BOOTP_GATEWAY
120#define CONFIG_BOOTP_HOSTNAME
121#define CONFIG_BOOTP_NISDOMAIN
122#define CONFIG_BOOTP_BOOTPATH
123#define CONFIG_BOOTP_DNS
124#define CONFIG_BOOTP_DNS2
125#define CONFIG_BOOTP_SEND_HOSTNAME
126#define CONFIG_BOOTP_NTPSERVER
127#define CONFIG_BOOTP_TIMEOFFSET
128
wdenk5b1d7132002-11-03 00:07:02 +0000129
Jon Loeliger60a08762007-07-07 21:04:26 -0500130/*
131 * Command line configuration.
132 */
133#include <config_cmd_default.h>
134
wdenk5b1d7132002-11-03 00:07:02 +0000135
136/*
137 * Miscellaneous configurable options
138 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200139#define CONFIG_SYS_LONGHELP /* undef to save memory */
140#define CONFIG_SYS_PROMPT ":>" /* Monitor Command Prompt */
Jon Loeliger60a08762007-07-07 21:04:26 -0500141#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200142#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenk5b1d7132002-11-03 00:07:02 +0000143#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200144#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenk5b1d7132002-11-03 00:07:02 +0000145#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200146#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
147#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
148#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenk5b1d7132002-11-03 00:07:02 +0000149
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200150#define CONFIG_SYS_MEMTEST_START 0x00004000 /* memtest works on */
151#define CONFIG_SYS_MEMTEST_END 0x01000000 /* 0 ... 16 MB in DRAM */
wdenk5b1d7132002-11-03 00:07:02 +0000152
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200153#define CONFIG_SYS_LOAD_ADDR 0x00100000 /* default load address */
wdenk5b1d7132002-11-03 00:07:02 +0000154
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200155#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenk5b1d7132002-11-03 00:07:02 +0000156
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200157#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
wdenk5b1d7132002-11-03 00:07:02 +0000158
159/*
160 * Low Level Configuration Settings
161 * (address mappings, register initial values, etc.)
162 * You should know what you are doing if you make changes here.
163 */
164/*-----------------------------------------------------------------------
165 * Internal Memory Mapped Register
166 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200167#define CONFIG_SYS_IMMR_SIZE ((uint)(64 * 1024))
wdenk5b1d7132002-11-03 00:07:02 +0000168
169/*-----------------------------------------------------------------------
170 * Definitions for initial stack pointer and data area (in DPRAM)
171 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200172#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
Wolfgang Denk553f0982010-10-26 13:32:32 +0200173#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200174#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200175#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenk5b1d7132002-11-03 00:07:02 +0000176
177/*-----------------------------------------------------------------------
178 * Start addresses for the final memory configuration
179 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200180 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
wdenk5b1d7132002-11-03 00:07:02 +0000181 * Also NOTE that it doesn't mean SDRAM - it means MEMORY.
182 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200183#define CONFIG_SYS_FLASH_SIZE ((uint)(8 * 1024 * 1024)) /* max 8Mbyte */
wdenk5b1d7132002-11-03 00:07:02 +0000184#if 0
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200185#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
wdenk5b1d7132002-11-03 00:07:02 +0000186#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200187#define CONFIG_SYS_MONITOR_LEN (512 << 10) /* Reserve 512 kB for Monitor */
wdenk5b1d7132002-11-03 00:07:02 +0000188#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200189#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
190#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenk5b1d7132002-11-03 00:07:02 +0000191
192/*
193 * For booting Linux, the board info and command line data
194 * have to be in the first 8 MB of memory, since this is
195 * the maximum mapped by the Linux kernel during initialization.
196 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200197#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenk5b1d7132002-11-03 00:07:02 +0000198/*-----------------------------------------------------------------------
199 * FLASH organization
200 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200201#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
202#define CONFIG_SYS_MAX_FLASH_SECT 8 /* max number of sectors on one chip */
wdenk5b1d7132002-11-03 00:07:02 +0000203
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200204#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
205#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
wdenk5b1d7132002-11-03 00:07:02 +0000206
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200207#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200208#define CONFIG_ENV_OFFSET 0x00040000 /* Offset of Environment Sector */
209#define CONFIG_ENV_SIZE 0x40000 /* Total Size of Environment Sector */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200210#define CONFIG_SYS_USE_PPCENV /* Environment embedded in sect .ppcenv */
wdenk5b1d7132002-11-03 00:07:02 +0000211
212/*-----------------------------------------------------------------------
213 * Cache Configuration
214 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200215#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
Jon Loeliger60a08762007-07-07 21:04:26 -0500216#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200217#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
wdenk5b1d7132002-11-03 00:07:02 +0000218#endif
219
220/*-----------------------------------------------------------------------
221 * SYPCR - System Protection Control 11-9
222 * SYPCR can only be written once after reset!
223 *-----------------------------------------------------------------------
224 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
225 */
226#if defined(CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200227#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
wdenk5b1d7132002-11-03 00:07:02 +0000228 SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP)
229#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200230#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
wdenk5b1d7132002-11-03 00:07:02 +0000231#endif
232
233/*-----------------------------------------------------------------------
234 * SIUMCR - SIU Module Configuration 11-6
235 *-----------------------------------------------------------------------
236 * PCMCIA config., multi-function pin tri-state
237 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200238#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
wdenk5b1d7132002-11-03 00:07:02 +0000239
240/*-----------------------------------------------------------------------
241 * TBSCR - Time Base Status and Control 11-26
242 *-----------------------------------------------------------------------
243 * Clear Reference Interrupt Status, Timebase freezing enabled
244 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200245#define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)
wdenk5b1d7132002-11-03 00:07:02 +0000246
247/*-----------------------------------------------------------------------
248 * PISCR - Periodic Interrupt Status and Control 11-31
249 *-----------------------------------------------------------------------
250 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
251 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200252#define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF)
wdenk5b1d7132002-11-03 00:07:02 +0000253
254/*-----------------------------------------------------------------------
255 * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
256 *-----------------------------------------------------------------------
257 * Reset PLL lock status sticky bit, timer expired status bit and timer *
258 * interrupt status bit - leave PLL multiplication factor unchanged !
259 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200260#define CONFIG_SYS_PLPRCR (PLPRCR_SPLSS | PLPRCR_TEXPS | PLPRCR_TMIST | CONFIG_SYS_PLPRCR_MF)
wdenk5b1d7132002-11-03 00:07:02 +0000261
262/*-----------------------------------------------------------------------
263 * SCCR - System Clock and reset Control Register 15-27
264 *-----------------------------------------------------------------------
265 * Set clock output, timebase and RTC source and divider,
266 * power management and some other internal clocks
267 */
268#define SCCR_MASK SCCR_EBDF11
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200269#define CONFIG_SYS_SCCR (SCCR_TBS | \
wdenk5b1d7132002-11-03 00:07:02 +0000270 SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \
271 SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \
272 SCCR_DFALCD00)
273
274 /*-----------------------------------------------------------------------
275 *
276 *-----------------------------------------------------------------------
277 *
278 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200279#define CONFIG_SYS_DER 0
wdenk5b1d7132002-11-03 00:07:02 +0000280
281/* Because of the way the 860 starts up and assigns CS0 the
282* entire address space, we have to set the memory controller
283* differently. Normally, you write the option register
284* first, and then enable the chip select by writing the
285* base register. For CS0, you must write the base register
286* first, followed by the option register.
287*/
288
289/*
290 * Init Memory Controller:
291 *
292 * BR0/1 and OR0/1 (FLASH)
293 */
294/* the other CS:s are determined by looking at parameters in BCSRx */
295
296#define BCSR_SIZE ((uint)(64 * 1024))
297
298#define FLASH_BASE1_PRELIM 0x00000000 /* FLASH bank #1 */
299
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200300#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
301#define CONFIG_SYS_PRELIM_OR_AM 0xFFE00000 /* OR addr mask */
wdenk5b1d7132002-11-03 00:07:02 +0000302
303/* FLASH timing: ACS = 10, TRLX = 1, CSNT = 1, SCY = 3, EHTR = 0 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200304#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_DIV4 | OR_BI | OR_SCY_3_CLK | OR_TRLX)
wdenk5b1d7132002-11-03 00:07:02 +0000305
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200306#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
307#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) /* 1 Mbyte until detected and only 1 Mbyte is needed*/
308#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
wdenk5b1d7132002-11-03 00:07:02 +0000309
310/* BCSRx - Board Control and Status Registers */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200311#define CONFIG_SYS_OR1_REMAP CONFIG_SYS_OR0_REMAP
312#define CONFIG_SYS_OR1_PRELIM 0xffff8110 /* 64Kbyte address space */
313#define CONFIG_SYS_BR1_PRELIM ((BCSR_ADDR) | BR_V )
wdenk5b1d7132002-11-03 00:07:02 +0000314
315
316/*
317 * Memory Periodic Timer Prescaler
318 */
319
320/* periodic timer for refresh */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200321#define CONFIG_SYS_MAMR_PTA 97 /* start with divider for 100 MHz */
wdenk5b1d7132002-11-03 00:07:02 +0000322
323/* refresh rate 15.6 us (= 64 ms / 4K = 62.4 / quad bursts) for <= 128 MBit */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200324#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
325#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
wdenk5b1d7132002-11-03 00:07:02 +0000326
327/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200328#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
329#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
wdenk5b1d7132002-11-03 00:07:02 +0000330
331/*
332 * MAMR settings for SDRAM
333 */
334
335/* 8 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200336#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenk5b1d7132002-11-03 00:07:02 +0000337 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \
338 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
339/* 9 column SDRAM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200340#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \
wdenk5b1d7132002-11-03 00:07:02 +0000341 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \
342 MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X)
343
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200344#define CONFIG_SYS_MAMR 0x13a01114
wdenk5b1d7132002-11-03 00:07:02 +0000345
346/* values according to the manual */
347
348#define BCSR0 ((uint) (BCSR_ADDR + 00))
349#define BCSR1 ((uint) (BCSR_ADDR + 0x04))
350#define BCSR2 ((uint) (BCSR_ADDR + 0x08))
351#define BCSR3 ((uint) (BCSR_ADDR + 0x0c))
352#define BCSR4 ((uint) (BCSR_ADDR + 0x10))
353
354/* FADS bitvalues by Helmut Buchsbaum
355 * see MPC8xxADS User's Manual for a proper description
356 * of the following structures
357 */
358
359#define BCSR0_ERB ((uint)0x80000000)
360#define BCSR0_IP ((uint)0x40000000)
361#define BCSR0_BDIS ((uint)0x10000000)
362#define BCSR0_BPS_MASK ((uint)0x0C000000)
363#define BCSR0_ISB_MASK ((uint)0x01800000)
364#define BCSR0_DBGC_MASK ((uint)0x00600000)
365#define BCSR0_DBPC_MASK ((uint)0x00180000)
366#define BCSR0_EBDF_MASK ((uint)0x00060000)
367
368#define BCSR1_FLASH_EN ((uint)0x80000000)
369#define BCSR1_DRAM_EN ((uint)0x40000000)
370#define BCSR1_ETHEN ((uint)0x20000000)
371#define BCSR1_IRDEN ((uint)0x10000000)
372#define BCSR1_FLASH_CFG_EN ((uint)0x08000000)
373#define BCSR1_CNT_REG_EN_PROTECT ((uint)0x04000000)
374#define BCSR1_BCSR_EN ((uint)0x02000000)
375#define BCSR1_RS232EN_1 ((uint)0x01000000)
376#define BCSR1_PCCEN ((uint)0x00800000)
377#define BCSR1_PCCVCC0 ((uint)0x00400000)
378#define BCSR1_PCCVPP_MASK ((uint)0x00300000)
379#define BCSR1_DRAM_HALF_WORD ((uint)0x00080000)
380#define BCSR1_RS232EN_2 ((uint)0x00040000)
381#define BCSR1_SDRAM_EN ((uint)0x00020000)
382#define BCSR1_PCCVCC1 ((uint)0x00010000)
383
384#define BCSR2_FLASH_PD_MASK ((uint)0xF0000000)
wdenkb54d32b2004-06-10 21:34:36 +0000385#define BCSR2_FLASH_PD_SHIFT 28
wdenk5b1d7132002-11-03 00:07:02 +0000386#define BCSR2_DRAM_PD_MASK ((uint)0x07800000)
wdenkb54d32b2004-06-10 21:34:36 +0000387#define BCSR2_DRAM_PD_SHIFT 23
wdenk5b1d7132002-11-03 00:07:02 +0000388#define BCSR2_EXTTOLI_MASK ((uint)0x00780000)
389#define BCSR2_DBREVNR_MASK ((uint)0x00030000)
390
391#define BCSR3_DBID_MASK ((ushort)0x3800)
392#define BCSR3_CNT_REG_EN_PROTECT ((ushort)0x0400)
393#define BCSR3_BREVNR0 ((ushort)0x0080)
394#define BCSR3_FLASH_PD_MASK ((ushort)0x0070)
395#define BCSR3_BREVN1 ((ushort)0x0008)
396#define BCSR3_BREVN2_MASK ((ushort)0x0003)
397
398#define BCSR4_ETHLOOP ((uint)0x80000000)
399#define BCSR4_TFPLDL ((uint)0x40000000)
400#define BCSR4_TPSQEL ((uint)0x20000000)
401#define BCSR4_SIGNAL_LAMP ((uint)0x10000000)
402#ifdef CONFIG_MPC823
403#define BCSR4_USB_EN ((uint)0x08000000)
404#endif /* CONFIG_MPC823 */
405#ifdef CONFIG_MPC860SAR
406#define BCSR4_UTOPIA_EN ((uint)0x08000000)
407#endif /* CONFIG_MPC860SAR */
408#ifdef CONFIG_MPC860T
409#define BCSR4_FETH_EN ((uint)0x08000000)
410#endif /* CONFIG_MPC860T */
411#ifdef CONFIG_MPC823
412#define BCSR4_USB_SPEED ((uint)0x04000000)
413#endif /* CONFIG_MPC823 */
414#ifdef CONFIG_MPC860T
415#define BCSR4_FETHCFG0 ((uint)0x04000000)
416#endif /* CONFIG_MPC860T */
417#ifdef CONFIG_MPC823
418#define BCSR4_VCCO ((uint)0x02000000)
419#endif /* CONFIG_MPC823 */
420#ifdef CONFIG_MPC860T
421#define BCSR4_FETHFDE ((uint)0x02000000)
422#endif /* CONFIG_MPC860T */
423#ifdef CONFIG_MPC823
424#define BCSR4_VIDEO_ON ((uint)0x00800000)
425#endif /* CONFIG_MPC823 */
426#ifdef CONFIG_MPC823
427#define BCSR4_VDO_EKT_CLK_EN ((uint)0x00400000)
428#endif /* CONFIG_MPC823 */
429#ifdef CONFIG_MPC860T
430#define BCSR4_FETHCFG1 ((uint)0x00400000)
431#endif /* CONFIG_MPC860T */
432#ifdef CONFIG_MPC823
433#define BCSR4_VIDEO_RST ((uint)0x00200000)
434#endif /* CONFIG_MPC823 */
435#ifdef CONFIG_MPC860T
436#define BCSR4_FETHRST ((uint)0x00200000)
437#endif /* CONFIG_MPC860T */
438#ifdef CONFIG_MPC823
439#define BCSR4_MODEM_EN ((uint)0x00100000)
440#endif /* CONFIG_MPC823 */
441#ifdef CONFIG_MPC823
442#define BCSR4_DATA_VOICE ((uint)0x00080000)
443#endif /* CONFIG_MPC823 */
444#ifdef CONFIG_MPC850
445#define BCSR4_DATA_VOICE ((uint)0x00080000)
446#endif /* CONFIG_MPC850 */
447
448#define CONFIG_DRAM_50MHZ 1
449#define CONFIG_SDRAM_50MHZ
450
wdenk5b1d7132002-11-03 00:07:02 +0000451/* We don't use the 8259.
452*/
453#define NR_8259_INTS 0
454
wdenk5b1d7132002-11-03 00:07:02 +0000455/*
456 * MPC8xx CPM Options
457 */
458#define CONFIG_SCC_ENET 1
459#define CONFIG_SCC2_ENET 1
460#undef CONFIG_FEC_ENET
461#undef CONFIG_CPM_IIC
462#undef CONFIG_UCODE_PATCH
463
464#define CONFIG_DISK_SPINUP_TIME 1000000
465
466/* PCMCIA configuration */
467
468#define PCMCIA_MAX_SLOTS 1
469
470#ifdef CONFIG_MPC860
471#define PCMCIA_SLOT_A 1
472#endif
473
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200474#define CONFIG_SYS_DAUGHTERBOARD
wdenk180d3f72004-01-04 16:28:35 +0000475
wdenk5b1d7132002-11-03 00:07:02 +0000476#endif /* __CONFIG_H */