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wdenke2211742002-11-02 23:30:20 +00001/*
2 * (C) Copyright 2002 Wolfgang Grandegger <wg@denx.de>
3 *
4 * This file is based on similar values for other boards found in
5 * other U-Boot config files, mainly tqm8260.h and mpc8260ads.h.
6 *
7 * See file CREDITS for list of people who contributed to this
8 * project.
9 *
10 * This program is free software; you can redistribute it and/or
11 * modify it under the terms of the GNU General Public License as
12 * published by the Free Software Foundation; either version 2 of
13 * the License, or (at your option) any later version.
14 *
15 * This program is distributed in the hope that it will be useful,
16 * but WITHOUT ANY WARRANTY; without even the implied warranty of
17 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 * GNU General Public License for more details.
19 *
20 * You should have received a copy of the GNU General Public License
21 * along with this program; if not, write to the Free Software
22 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
23 * MA 02111-1307 USA
24 */
25
26/*
27 * Config header file for a Interphase 4539 PMC, 64 MB SDRAM, 4MB Flash.
28 */
29
30#ifndef __CONFIG_H
31#define __CONFIG_H
32
wdenke2211742002-11-02 23:30:20 +000033/*-----------------------------------------------------------------------
34 * High Level Configuration Options
35 * (easy to change)
36 */
37
38#define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */
39#define CONFIG_IPHASE4539 1 /* ...on a Interphase 4539 PMC */
40
Wolfgang Denk2ae18242010-10-06 09:05:45 +020041#define CONFIG_SYS_TEXT_BASE 0xffb00000
42
Jon Loeliger9c4c5ae2005-07-23 10:37:35 -050043#define CONFIG_CPM2 1 /* Has a CPM2 */
44
wdenke2211742002-11-02 23:30:20 +000045/*-----------------------------------------------------------------------
46 * select serial console configuration
47 *
48 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
49 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
50 * for SCC).
51 *
52 * if CONFIG_CONS_NONE is defined, then the serial console routines must
53 * defined elsewhere (for example, on the cogent platform, there are serial
54 * ports on the motherboard which are used for the serial console - see
55 * cogent/cma101/serial.[ch]).
56 */
57#define CONFIG_CONS_ON_SMC /* define if console on SMC */
58#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
59#undef CONFIG_CONS_NONE /* define if console on something else */
60#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
61
62/*-----------------------------------------------------------------------
63 * select ethernet configuration
64 *
65 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
66 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
67 * for FCC)
68 *
69 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
Jon Loeliger639221c2007-07-09 17:15:49 -050070 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
wdenke2211742002-11-02 23:30:20 +000071 */
72#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
73#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
74#undef CONFIG_ETHER_NONE /* define if ether on something else */
75#define CONFIG_ETHER_INDEX 3 /* which channel for ether */
76
77#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 3)
78
79/*-----------------------------------------------------------------------
80 * - Rx-CLK is CLK14
81 * - Tx-CLK is CLK16
82 * - Select bus for bd/buffers (see 28-13)
83 * - Half duplex
84 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020085# define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK)
86# define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF3CS_CLK14 | CMXFCR_TF3CS_CLK16)
87# define CONFIG_SYS_CPMFCR_RAMTYPE 0
88# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
wdenke2211742002-11-02 23:30:20 +000089
90#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
91
92/* other options */
93
94#define CONFIG_8260_CLKIN 66666666 /* in Hz */
95#define CONFIG_BAUDRATE 19200
96
Jon Loeliger7be044e2007-07-09 21:24:19 -050097/*
98 * BOOTP options
99 */
100#define CONFIG_BOOTP_SUBNETMASK
101#define CONFIG_BOOTP_GATEWAY
102#define CONFIG_BOOTP_HOSTNAME
103#define CONFIG_BOOTP_BOOTPATH
104#define CONFIG_BOOTP_BOOTFILESIZE
wdenke2211742002-11-02 23:30:20 +0000105
106/*
107 * select i2c support configuration
108 *
109 * Supported configurations are {none, software, hardware} drivers.
110 * If the software driver is chosen, there are some additional
111 * configuration items that the driver uses to drive the port pins.
112 */
113#undef CONFIG_HARD_I2C /* I2C with hardware support */
114#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200115#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
116#define CONFIG_SYS_I2C_SLAVE 0x7F
wdenke2211742002-11-02 23:30:20 +0000117
118/*
119 * Software (bit-bang) I2C driver configuration
120 */
121#ifdef CONFIG_SOFT_I2C
122#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
123#define I2C_ACTIVE (iop->pdir |= 0x00010000)
124#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
125#define I2C_READ ((iop->pdat & 0x00010000) != 0)
126#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
127 else iop->pdat &= ~0x00010000
128#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
129 else iop->pdat &= ~0x00020000
130#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
131#endif /* CONFIG_SOFT_I2C */
132
wdenke2211742002-11-02 23:30:20 +0000133
Jon Loeliger348f2582007-07-08 13:46:18 -0500134/*
135 * Command line configuration.
136 */
137#include <config_cmd_default.h>
wdenke2211742002-11-02 23:30:20 +0000138
139
140#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
141#define CONFIG_BOOTCOMMAND "bootm 100000" /* autoboot command */
142#define CONFIG_BOOTARGS "root=/dev/ram rw"
143
Jon Loeliger348f2582007-07-08 13:46:18 -0500144#if defined(CONFIG_CMD_KGDB)
wdenke2211742002-11-02 23:30:20 +0000145#undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */
146#define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */
147#undef CONFIG_KGDB_NONE /* define if kgdb on something else */
148#define CONFIG_KGDB_INDEX 2 /* which serial channel for kgdb */
149#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port at */
150#endif
151
152#undef CONFIG_WATCHDOG /* disable platform specific watchdog */
153
154/*-----------------------------------------------------------------------
155 * Miscellaneous configurable options
156 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200157#define CONFIG_SYS_LONGHELP /* undef to save memory */
158#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Jon Loeliger348f2582007-07-08 13:46:18 -0500159#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200160#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
wdenke2211742002-11-02 23:30:20 +0000161#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200162#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
wdenke2211742002-11-02 23:30:20 +0000163#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200164#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
165#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
166#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
wdenke2211742002-11-02 23:30:20 +0000167
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200168#define CONFIG_SYS_MEMTEST_START 0x00100000 /* memtest works on */
169#define CONFIG_SYS_MEMTEST_END 0x00F00000 /* 1 ... 15 MB in DRAM */
wdenke2211742002-11-02 23:30:20 +0000170
171#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passed to Linux in MHz */
172 /* for versions < 2.4.5-pre5 */
173
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200174#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
wdenke2211742002-11-02 23:30:20 +0000175
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200176#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
wdenke2211742002-11-02 23:30:20 +0000177
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200178#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
wdenke2211742002-11-02 23:30:20 +0000179
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200180#define CONFIG_SYS_RESET_ADDRESS 0x04400000
wdenke2211742002-11-02 23:30:20 +0000181
182#define CONFIG_MISC_INIT_R 1 /* We need misc_init_r() */
183
184/*-----------------------------------------------------------------------
185 * For booting Linux, the board info and command line data
186 * have to be in the first 8 MB of memory, since this is
187 * the maximum mapped by the Linux kernel during initialization.
188 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200189#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
wdenke2211742002-11-02 23:30:20 +0000190
191/*-----------------------------------------------------------------------
192 * Start addresses for the final memory configuration (Setup by the
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200193 * startup code). Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0.
wdenke2211742002-11-02 23:30:20 +0000194 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200195#define CONFIG_SYS_SDRAM_BASE 0x00000000
196#define CONFIG_SYS_FLASH_BASE 0xFF800000
wdenke2211742002-11-02 23:30:20 +0000197
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200198#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200199#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
200#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
wdenke2211742002-11-02 23:30:20 +0000201
202/*-----------------------------------------------------------------------
203 * FLASH organization
204 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200205#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
206#define CONFIG_SYS_MAX_FLASH_SECT 64 /* max num of sects on one chip */
207#define CONFIG_SYS_MAX_FLASH_SIZE (CONFIG_SYS_MAX_FLASH_SECT * 0x10000) /* 4 MB */
wdenke2211742002-11-02 23:30:20 +0000208
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200209#define CONFIG_SYS_FLASH_ERASE_TOUT 2400000 /* Flash Erase Timeout (in ms) */
210#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
wdenke2211742002-11-02 23:30:20 +0000211
212/* Environment in FLASH, there is little space left in Serial EEPROM */
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200213#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200214#define CONFIG_ENV_SECT_SIZE 0x10000 /* We use one complete sector */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200215#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x10000) /* 2. sector */
wdenke2211742002-11-02 23:30:20 +0000216
217
218/*-----------------------------------------------------------------------
219 * Hard Reset Configuration Words
220 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200221 * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
wdenke2211742002-11-02 23:30:20 +0000222 * defines for the various registers affected by the HRCW e.g. changing
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200223 * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
wdenke2211742002-11-02 23:30:20 +0000224 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200225#define CONFIG_SYS_HRCW_MASTER ( ( HRCW_BPS01 | HRCW_EBM ) |\
wdenke2211742002-11-02 23:30:20 +0000226 ( HRCW_L2CPC10 | HRCW_ISB110 ) |\
227 ( HRCW_MMR11 | HRCW_APPC10 ) |\
228 ( HRCW_CS10PC01 | HRCW_MODCK_H0101 ) \
229 ) /* 0x14863245 */
230
231/* no slaves */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200232#define CONFIG_SYS_HRCW_SLAVE1 0
233#define CONFIG_SYS_HRCW_SLAVE2 0
234#define CONFIG_SYS_HRCW_SLAVE3 0
235#define CONFIG_SYS_HRCW_SLAVE4 0
236#define CONFIG_SYS_HRCW_SLAVE5 0
237#define CONFIG_SYS_HRCW_SLAVE6 0
238#define CONFIG_SYS_HRCW_SLAVE7 0
wdenke2211742002-11-02 23:30:20 +0000239
240/*-----------------------------------------------------------------------
241 * Internal Memory Mapped Register
242 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200243#define CONFIG_SYS_IMMR 0xFF000000 /* We keep original value */
wdenke2211742002-11-02 23:30:20 +0000244
245/*-----------------------------------------------------------------------
246 * Definitions for initial stack pointer and data area (in DPRAM)
247 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200248#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
Wolfgang Denk553f0982010-10-26 13:32:32 +0200249#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in DPRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200250#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200251#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
wdenke2211742002-11-02 23:30:20 +0000252
253/*-----------------------------------------------------------------------
wdenke2211742002-11-02 23:30:20 +0000254 * Cache Configuration
255 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200256#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
Jon Loeliger348f2582007-07-08 13:46:18 -0500257#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200258# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
wdenke2211742002-11-02 23:30:20 +0000259#endif
260
261/*-----------------------------------------------------------------------
262 * HIDx - Hardware Implementation-dependent Registers 2-11
263 *-----------------------------------------------------------------------
264 * HID0 also contains cache control.
265 *
266 * HID1 has only read-only information - nothing to set.
267 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200268#define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
Wolfgang Denk53677ef2008-05-20 16:00:29 +0200269 HID0_IFEM|HID0_ABE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200270#define CONFIG_SYS_HID0_FINAL (HID0_IFEM|HID0_ABE)
271#define CONFIG_SYS_HID2 0
wdenke2211742002-11-02 23:30:20 +0000272
273/*-----------------------------------------------------------------------
274 * RMR - Reset Mode Register 5-5
275 *-----------------------------------------------------------------------
276 * turn on Checkstop Reset Enable
277 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200278#define CONFIG_SYS_RMR RMR_CSRE
wdenke2211742002-11-02 23:30:20 +0000279
280/*-----------------------------------------------------------------------
281 * BCR - Bus Configuration 4-25
282 *-----------------------------------------------------------------------
283 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200284#define CONFIG_SYS_BCR 0xA01C0000
wdenke2211742002-11-02 23:30:20 +0000285
286/*-----------------------------------------------------------------------
287 * SIUMCR - SIU Module Configuration 4-31
288 *-----------------------------------------------------------------------
289 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200290#define CONFIG_SYS_SIUMCR 0X4205C000
wdenke2211742002-11-02 23:30:20 +0000291
292/*-----------------------------------------------------------------------
293 * SYPCR - System Protection Control 4-35
294 * SYPCR can only be written once after reset!
295 *-----------------------------------------------------------------------
296 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
297 */
298#if defined (CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200299#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
wdenke2211742002-11-02 23:30:20 +0000300 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
301#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200302#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
wdenke2211742002-11-02 23:30:20 +0000303 SYPCR_SWRI|SYPCR_SWP)
304#endif /* CONFIG_WATCHDOG */
305
306/*-----------------------------------------------------------------------
307 * TMCNTSC - Time Counter Status and Control 4-40
308 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
309 * and enable Time Counter
310 *-----------------------------------------------------------------------
311 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200312#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
wdenke2211742002-11-02 23:30:20 +0000313
314/*-----------------------------------------------------------------------
315 * PISCR - Periodic Interrupt Status and Control 4-42
316 *-----------------------------------------------------------------------
317 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
318 * Periodic timer
319 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200320#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
wdenke2211742002-11-02 23:30:20 +0000321
322/*-----------------------------------------------------------------------
323 * SCCR - System Clock Control 9-8
324 *-----------------------------------------------------------------------
325 * Ensure DFBRG is Divide by 16
326 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200327#define CONFIG_SYS_SCCR 0
wdenke2211742002-11-02 23:30:20 +0000328
329/*-----------------------------------------------------------------------
330 * RCCR - RISC Controller Configuration 13-7
331 *-----------------------------------------------------------------------
332 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200333#define CONFIG_SYS_RCCR 0
wdenke2211742002-11-02 23:30:20 +0000334
335/*-----------------------------------------------------------------------
336 * Init Memory Controller:
337 *
338 * Bank Bus Machine PortSz Device
339 * ---- --- ------- ------ ------
340 * 0 60x GPCM 64 bit FLASH
341 * 1 60x SDRAM 64 bit SDRAM
342 */
343
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200344#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) | 0x0801)
345#define CONFIG_SYS_OR0_PRELIM 0xFF800882
346#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) | 0x0041)
347#define CONFIG_SYS_OR1_PRELIM 0xF8002CD0
wdenke2211742002-11-02 23:30:20 +0000348
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200349#define CONFIG_SYS_PSDMR 0x404A241A
350#define CONFIG_SYS_MPTPR 0x00007400
351#define CONFIG_SYS_PSRT 0x00000007
wdenke2211742002-11-02 23:30:20 +0000352
353#endif /* __CONFIG_H */