blob: d0e4b2c00bd086fb93a0bf101e5356284e372ec7 [file] [log] [blame]
Kim Phillips5e918a92008-01-16 00:38:05 -06001/*
2 * Copyright (C) 2007 Freescale Semiconductor, Inc.
3 * Kevin Lam <kevin.lam@freescale.com>
4 * Joe D'Abbraccio <joe.d'abbraccio@freescale.com>
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation; either version 2 of
9 * the License, or (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program; if not, write to the Free Software
18 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
19 * MA 02111-1307 USA
20 */
21
22#ifndef __CONFIG_H
23#define __CONFIG_H
24
25/*
26 * High Level Configuration Options
27 */
28#define CONFIG_E300 1 /* E300 family */
Peter Tyser2c7920a2009-05-22 17:23:25 -050029#define CONFIG_MPC83xx 1 /* MPC83xx family */
30#define CONFIG_MPC837x 1 /* MPC837x CPU specific */
Kim Phillips5e918a92008-01-16 00:38:05 -060031#define CONFIG_MPC837XERDB 1
32
Wolfgang Denk2ae18242010-10-06 09:05:45 +020033#define CONFIG_SYS_TEXT_BASE 0xFE000000
34
Kim Phillips5e918a92008-01-16 00:38:05 -060035#define CONFIG_PCI 1
36
Anton Vorontsov2bd74602008-03-24 17:40:43 +030037#define CONFIG_BOARD_EARLY_INIT_F
Timur Tabi89c77842008-02-08 13:15:55 -060038#define CONFIG_MISC_INIT_R
Anton Vorontsovc9646ed2009-06-10 00:25:30 +040039#define CONFIG_HWCONFIG
Timur Tabi89c77842008-02-08 13:15:55 -060040
41/*
42 * On-board devices
43 */
44#define CONFIG_TSEC_ENET /* TSEC Ethernet support */
45#define CONFIG_VSC7385_ENET
46
Kim Phillips5e918a92008-01-16 00:38:05 -060047/*
48 * System Clock Setup
49 */
50#ifdef CONFIG_PCISLAVE
51#define CONFIG_83XX_PCICLK 66666667 /* in HZ */
52#else
53#define CONFIG_83XX_CLKIN 66666667 /* in Hz */
Kim Phillipsbe9b56d2009-07-23 14:09:38 -050054#define CONFIG_PCIE
Kim Phillips5e918a92008-01-16 00:38:05 -060055#endif
56
57#ifndef CONFIG_SYS_CLK_FREQ
58#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN
59#endif
60
61/*
62 * Hardware Reset Configuration Word
63 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020064#define CONFIG_SYS_HRCW_LOW (\
Kim Phillips5e918a92008-01-16 00:38:05 -060065 HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\
66 HRCWL_DDR_TO_SCB_CLK_1X1 |\
67 HRCWL_SVCOD_DIV_2 |\
68 HRCWL_CSB_TO_CLKIN_5X1 |\
69 HRCWL_CORE_TO_CSB_2X1)
70
71#ifdef CONFIG_PCISLAVE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020072#define CONFIG_SYS_HRCW_HIGH (\
Kim Phillips5e918a92008-01-16 00:38:05 -060073 HRCWH_PCI_AGENT |\
74 HRCWH_PCI1_ARBITER_DISABLE |\
75 HRCWH_CORE_ENABLE |\
76 HRCWH_FROM_0XFFF00100 |\
77 HRCWH_BOOTSEQ_DISABLE |\
78 HRCWH_SW_WATCHDOG_DISABLE |\
79 HRCWH_ROM_LOC_LOCAL_16BIT |\
80 HRCWH_RL_EXT_LEGACY |\
81 HRCWH_TSEC1M_IN_RGMII |\
82 HRCWH_TSEC2M_IN_RGMII |\
83 HRCWH_BIG_ENDIAN |\
84 HRCWH_LDP_CLEAR)
85#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +020086#define CONFIG_SYS_HRCW_HIGH (\
Kim Phillips5e918a92008-01-16 00:38:05 -060087 HRCWH_PCI_HOST |\
88 HRCWH_PCI1_ARBITER_ENABLE |\
89 HRCWH_CORE_ENABLE |\
90 HRCWH_FROM_0X00000100 |\
91 HRCWH_BOOTSEQ_DISABLE |\
92 HRCWH_SW_WATCHDOG_DISABLE |\
93 HRCWH_ROM_LOC_LOCAL_16BIT |\
94 HRCWH_RL_EXT_LEGACY |\
95 HRCWH_TSEC1M_IN_RGMII |\
96 HRCWH_TSEC2M_IN_RGMII |\
97 HRCWH_BIG_ENDIAN |\
98 HRCWH_LDP_CLEAR)
99#endif
100
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200101/* System performance - define the value i.e. CONFIG_SYS_XXX
Kim Phillips5e918a92008-01-16 00:38:05 -0600102*/
103
104/* Arbiter Configuration Register */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200105#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */
106#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */
Kim Phillips5e918a92008-01-16 00:38:05 -0600107
108/* System Priority Control Regsiter */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200109#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC1&2 emergency priority (0-3) */
Kim Phillips5e918a92008-01-16 00:38:05 -0600110
111/* System Clock Configuration Register */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200112#define CONFIG_SYS_SCCR_TSEC1CM 1 /* eTSEC1 clock mode (0-3) */
113#define CONFIG_SYS_SCCR_TSEC2CM 1 /* eTSEC2 clock mode (0-3) */
114#define CONFIG_SYS_SCCR_SATACM SCCR_SATACM_2 /* SATA1-4 clock mode (0-3) */
Kim Phillips5e918a92008-01-16 00:38:05 -0600115
116/*
117 * System IO Config
118 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200119#define CONFIG_SYS_SICRH 0x08200000
120#define CONFIG_SYS_SICRL 0x00000000
Kim Phillips5e918a92008-01-16 00:38:05 -0600121
122/*
123 * Output Buffer Impedance
124 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200125#define CONFIG_SYS_OBIR 0x30100000
Kim Phillips5e918a92008-01-16 00:38:05 -0600126
127/*
128 * IMMR new address
129 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200130#define CONFIG_SYS_IMMR 0xE0000000
Kim Phillips5e918a92008-01-16 00:38:05 -0600131
132/*
Timur Tabi89c77842008-02-08 13:15:55 -0600133 * Device configurations
134 */
135
136/* Vitesse 7385 */
137
138#ifdef CONFIG_VSC7385_ENET
139
140#define CONFIG_TSEC2
141
142/* The flash address and size of the VSC7385 firmware image */
143#define CONFIG_VSC7385_IMAGE 0xFE7FE000
144#define CONFIG_VSC7385_IMAGE_SIZE 8192
145
146#endif
147
148/*
Kim Phillips5e918a92008-01-16 00:38:05 -0600149 * DDR Setup
150 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200151#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */
152#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE
153#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE
154#define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x03000000
155#define CONFIG_SYS_83XX_DDR_USES_CS0
Kim Phillips5e918a92008-01-16 00:38:05 -0600156
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200157#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN)
Kim Phillips5e918a92008-01-16 00:38:05 -0600158
159#undef CONFIG_DDR_ECC /* support DDR ECC function */
160#undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */
161
162#undef CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */
163
164/*
165 * Manually set up DDR parameters
166 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200167#define CONFIG_SYS_DDR_SIZE 256 /* MB */
168#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f
169#define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN | CSCONFIG_ODT_WR_ACS \
Kim Phillips5e918a92008-01-16 00:38:05 -0600170 | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10)
171
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200172#define CONFIG_SYS_DDR_TIMING_3 0x00000000
173#define CONFIG_SYS_DDR_TIMING_0 ((0 << TIMING_CFG0_RWT_SHIFT) \
Kim Phillips5e918a92008-01-16 00:38:05 -0600174 | (0 << TIMING_CFG0_WRT_SHIFT) \
175 | (0 << TIMING_CFG0_RRT_SHIFT) \
176 | (0 << TIMING_CFG0_WWT_SHIFT) \
177 | (2 << TIMING_CFG0_ACT_PD_EXIT_SHIFT) \
178 | (6 << TIMING_CFG0_PRE_PD_EXIT_SHIFT) \
179 | (8 << TIMING_CFG0_ODT_PD_EXIT_SHIFT) \
180 | (2 << TIMING_CFG0_MRS_CYC_SHIFT))
181 /* 0x00220802 */
182 /* 0x00260802 */ /* DDR400 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200183#define CONFIG_SYS_DDR_TIMING_1 ((3 << TIMING_CFG1_PRETOACT_SHIFT) \
Kim Phillips5e918a92008-01-16 00:38:05 -0600184 | (9 << TIMING_CFG1_ACTTOPRE_SHIFT) \
185 | (3 << TIMING_CFG1_ACTTORW_SHIFT) \
186 | (7 << TIMING_CFG1_CASLAT_SHIFT) \
187 | (13 << TIMING_CFG1_REFREC_SHIFT) \
188 | (3 << TIMING_CFG1_WRREC_SHIFT) \
189 | (2 << TIMING_CFG1_ACTTOACT_SHIFT) \
190 | (2 << TIMING_CFG1_WRTORD_SHIFT))
191 /* 0x3935d322 */
192 /* 0x3937d322 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200193#define CONFIG_SYS_DDR_TIMING_2 0x02984cc8
Kim Phillips5e918a92008-01-16 00:38:05 -0600194
Kim Phillips8eceeb72009-08-21 16:33:15 -0500195#define CONFIG_SYS_DDR_INTERVAL ((1024 << SDRAM_INTERVAL_REFINT_SHIFT) \
196 | (0 << SDRAM_INTERVAL_BSTOPRE_SHIFT))
Kim Phillips5e918a92008-01-16 00:38:05 -0600197 /* 0x06090100 */
198
199#if defined(CONFIG_DDR_2T_TIMING)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200200#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
Kim Phillips5e918a92008-01-16 00:38:05 -0600201 | 3 << SDRAM_CFG_SDRAM_TYPE_SHIFT \
202 | SDRAM_CFG_2T_EN \
203 | SDRAM_CFG_DBW_32)
204#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200205#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \
Kim Phillips5e918a92008-01-16 00:38:05 -0600206 | 3 << SDRAM_CFG_SDRAM_TYPE_SHIFT)
207 /* 0x43000000 */
208#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200209#define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */
Kim Phillips8eceeb72009-08-21 16:33:15 -0500210#define CONFIG_SYS_DDR_MODE ((0x0406 << SDRAM_MODE_ESD_SHIFT) \
Kim Phillips5e918a92008-01-16 00:38:05 -0600211 | (0x0442 << SDRAM_MODE_SD_SHIFT))
212 /* 0x04400442 */ /* DDR400 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200213#define CONFIG_SYS_DDR_MODE2 0x00000000
Kim Phillips5e918a92008-01-16 00:38:05 -0600214
215/*
216 * Memory test
217 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200218#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
219#define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest region */
220#define CONFIG_SYS_MEMTEST_END 0x0ef70010
Kim Phillips5e918a92008-01-16 00:38:05 -0600221
222/*
223 * The reserved memory
224 */
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200225#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
Kim Phillips5e918a92008-01-16 00:38:05 -0600226
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200227#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
228#define CONFIG_SYS_RAMBOOT
Kim Phillips5e918a92008-01-16 00:38:05 -0600229#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200230#undef CONFIG_SYS_RAMBOOT
Kim Phillips5e918a92008-01-16 00:38:05 -0600231#endif
232
Kim Phillips4a9932a2009-07-07 18:04:21 -0500233#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200234#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
Kim Phillips5e918a92008-01-16 00:38:05 -0600235
236/*
237 * Initial RAM Base Address Setup
238 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200239#define CONFIG_SYS_INIT_RAM_LOCK 1
240#define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */
Wolfgang Denk553f0982010-10-26 13:32:32 +0200241#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200242#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Kim Phillips5e918a92008-01-16 00:38:05 -0600243
244/*
245 * Local Bus Configuration & Clock Setup
246 */
Kim Phillipsc7190f02009-09-25 18:19:44 -0500247#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP
248#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200249#define CONFIG_SYS_LBC_LBCR 0x00000000
Becky Bruce0914f482010-06-17 11:37:18 -0500250#define CONFIG_FSL_ELBC 1
Kim Phillips5e918a92008-01-16 00:38:05 -0600251
252/*
253 * FLASH on the Local Bus
254 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200255#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200256#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200257#define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */
258#define CONFIG_SYS_FLASH_SIZE 8 /* max FLASH size is 32M */
Kim Phillips5e918a92008-01-16 00:38:05 -0600259
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200260#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */
261#define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */
262#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */
Kim Phillips5e918a92008-01-16 00:38:05 -0600263
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200264#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE /* Window base at flash base */
265#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016 /* 8 MB window size */
Kim Phillips5e918a92008-01-16 00:38:05 -0600266
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200267#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | /* Flash Base address */ \
Kim Phillips5e918a92008-01-16 00:38:05 -0600268 (2 << BR_PS_SHIFT) | /* 16 bit port size */ \
269 BR_V) /* valid */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200270#define CONFIG_SYS_OR0_PRELIM (0xFF800000 /* 8 MByte */ \
Kim Phillips5e918a92008-01-16 00:38:05 -0600271 | OR_GPCM_XACS \
272 | OR_GPCM_SCY_9 \
273 | OR_GPCM_EHTR \
274 | OR_GPCM_EAD)
275 /* 0xFF806FF7 TODO SLOW 8 MB flash size */
276
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200277#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
278#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */
Kim Phillips5e918a92008-01-16 00:38:05 -0600279
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200280#undef CONFIG_SYS_FLASH_CHECKSUM
281#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
282#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
Kim Phillips5e918a92008-01-16 00:38:05 -0600283
Anton Vorontsov46a3aee2008-03-24 17:40:23 +0300284/*
285 * NAND Flash on the Local Bus
286 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200287#define CONFIG_SYS_NAND_BASE 0xE0600000 /* 0xE0600000 */
288#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE | \
Anton Vorontsov46a3aee2008-03-24 17:40:23 +0300289 (2 << BR_DECC_SHIFT) | /* Use HW ECC */ \
290 BR_PS_8 | /* Port Size = 8 bit */ \
291 BR_MS_FCM | /* MSEL = FCM */ \
292 BR_V) /* valid */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200293#define CONFIG_SYS_OR1_PRELIM (0xFFFF8000 | /* length 32K */ \
Anton Vorontsov46a3aee2008-03-24 17:40:23 +0300294 OR_FCM_CSCT | \
295 OR_FCM_CST | \
296 OR_FCM_CHT | \
297 OR_FCM_SCY_1 | \
298 OR_FCM_TRLX | \
299 OR_FCM_EHTR)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200300#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE
301#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000000E /* 32KB */
Anton Vorontsov46a3aee2008-03-24 17:40:23 +0300302
Timur Tabi89c77842008-02-08 13:15:55 -0600303/* Vitesse 7385 */
304
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200305#define CONFIG_SYS_VSC7385_BASE 0xF0000000
Kim Phillips5e918a92008-01-16 00:38:05 -0600306
Timur Tabi89c77842008-02-08 13:15:55 -0600307#ifdef CONFIG_VSC7385_ENET
308
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200309#define CONFIG_SYS_BR2_PRELIM 0xf0000801 /* Base address */
310#define CONFIG_SYS_OR2_PRELIM 0xfffe09ff /* 128K bytes*/
311#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE /* Access Base */
312#define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000010 /* Access Size 128K */
Kim Phillips5e918a92008-01-16 00:38:05 -0600313
Timur Tabi89c77842008-02-08 13:15:55 -0600314#endif
315
Kim Phillips5e918a92008-01-16 00:38:05 -0600316/*
317 * Serial Port
318 */
319#define CONFIG_CONS_INDEX 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200320#define CONFIG_SYS_NS16550
321#define CONFIG_SYS_NS16550_SERIAL
322#define CONFIG_SYS_NS16550_REG_SIZE 1
323#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
Kim Phillips5e918a92008-01-16 00:38:05 -0600324
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200325#define CONFIG_SYS_BAUDRATE_TABLE \
Kim Phillips5e918a92008-01-16 00:38:05 -0600326 {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
327
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200328#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR+0x4500)
329#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600)
Kim Phillips5e918a92008-01-16 00:38:05 -0600330
Anton Vorontsov2bd74602008-03-24 17:40:43 +0300331/* SERDES */
332#define CONFIG_FSL_SERDES
333#define CONFIG_FSL_SERDES1 0xe3000
334#define CONFIG_FSL_SERDES2 0xe3100
335
Kim Phillips5e918a92008-01-16 00:38:05 -0600336/* Use the HUSH parser */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200337#define CONFIG_SYS_HUSH_PARSER
338#ifdef CONFIG_SYS_HUSH_PARSER
339#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
Kim Phillips5e918a92008-01-16 00:38:05 -0600340#endif
341
342/* Pass open firmware flat tree */
343#define CONFIG_OF_LIBFDT 1
344#define CONFIG_OF_BOARD_SETUP 1
Anton Vorontsovaabce7f2008-03-24 17:40:47 +0300345#define CONFIG_OF_STDOUT_VIA_ALIAS 1
Kim Phillips5e918a92008-01-16 00:38:05 -0600346
347/* I2C */
348#define CONFIG_HARD_I2C /* I2C with hardware support */
349#undef CONFIG_SOFT_I2C /* I2C bit-banged */
350#define CONFIG_FSL_I2C
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200351#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
352#define CONFIG_SYS_I2C_SLAVE 0x7F
353#define CONFIG_SYS_I2C_NOPROBES {0x51} /* Don't probe these addrs */
354#define CONFIG_SYS_I2C_OFFSET 0x3000
355#define CONFIG_SYS_I2C2_OFFSET 0x3100
Kim Phillips5e918a92008-01-16 00:38:05 -0600356
357/*
358 * Config on-board RTC
359 */
360#define CONFIG_RTC_DS1374 /* use ds1374 rtc via i2c */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200361#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
Kim Phillips5e918a92008-01-16 00:38:05 -0600362
363/*
364 * General PCI
365 * Addresses are mapped 1-1.
366 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200367#define CONFIG_SYS_PCI_MEM_BASE 0x80000000
368#define CONFIG_SYS_PCI_MEM_PHYS CONFIG_SYS_PCI_MEM_BASE
369#define CONFIG_SYS_PCI_MEM_SIZE 0x10000000 /* 256M */
370#define CONFIG_SYS_PCI_MMIO_BASE 0x90000000
371#define CONFIG_SYS_PCI_MMIO_PHYS CONFIG_SYS_PCI_MMIO_BASE
372#define CONFIG_SYS_PCI_MMIO_SIZE 0x10000000 /* 256M */
373#define CONFIG_SYS_PCI_IO_BASE 0x00000000
374#define CONFIG_SYS_PCI_IO_PHYS 0xE0300000
375#define CONFIG_SYS_PCI_IO_SIZE 0x100000 /* 1M */
Kim Phillips5e918a92008-01-16 00:38:05 -0600376
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200377#define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE
378#define CONFIG_SYS_PCI_SLV_MEM_BUS 0x00000000
379#define CONFIG_SYS_PCI_SLV_MEM_SIZE 0x80000000
Kim Phillips5e918a92008-01-16 00:38:05 -0600380
Anton Vorontsov7e915582009-02-19 18:20:52 +0300381#define CONFIG_SYS_PCIE1_BASE 0xA0000000
382#define CONFIG_SYS_PCIE1_CFG_BASE 0xA0000000
383#define CONFIG_SYS_PCIE1_CFG_SIZE 0x08000000
384#define CONFIG_SYS_PCIE1_MEM_BASE 0xA8000000
385#define CONFIG_SYS_PCIE1_MEM_PHYS 0xA8000000
386#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000
387#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000
388#define CONFIG_SYS_PCIE1_IO_PHYS 0xB8000000
389#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000
390
391#define CONFIG_SYS_PCIE2_BASE 0xC0000000
392#define CONFIG_SYS_PCIE2_CFG_BASE 0xC0000000
393#define CONFIG_SYS_PCIE2_CFG_SIZE 0x08000000
394#define CONFIG_SYS_PCIE2_MEM_BASE 0xC8000000
395#define CONFIG_SYS_PCIE2_MEM_PHYS 0xC8000000
396#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000
397#define CONFIG_SYS_PCIE2_IO_BASE 0x00000000
398#define CONFIG_SYS_PCIE2_IO_PHYS 0xD8000000
399#define CONFIG_SYS_PCIE2_IO_SIZE 0x00800000
400
Kim Phillips5e918a92008-01-16 00:38:05 -0600401#ifdef CONFIG_PCI
Kim Phillips5e918a92008-01-16 00:38:05 -0600402#define CONFIG_PCI_PNP /* do pci plug-and-play */
403
Kim Phillips5e918a92008-01-16 00:38:05 -0600404#undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200405#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */
Kim Phillips5e918a92008-01-16 00:38:05 -0600406#endif /* CONFIG_PCI */
407
Kim Phillips5e918a92008-01-16 00:38:05 -0600408/*
409 * TSEC
410 */
Timur Tabi89c77842008-02-08 13:15:55 -0600411#ifdef CONFIG_TSEC_ENET
Kim Phillips5e918a92008-01-16 00:38:05 -0600412
Timur Tabi89c77842008-02-08 13:15:55 -0600413#define CONFIG_GMII /* MII PHY management */
414
415#define CONFIG_TSEC1
416
417#ifdef CONFIG_TSEC1
418#define CONFIG_HAS_ETH0
Kim Phillips5e918a92008-01-16 00:38:05 -0600419#define CONFIG_TSEC1_NAME "TSEC0"
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200420#define CONFIG_SYS_TSEC1_OFFSET 0x24000
Kim Phillips5e918a92008-01-16 00:38:05 -0600421#define TSEC1_PHY_ADDR 2
Kim Phillips5e918a92008-01-16 00:38:05 -0600422#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
Kim Phillips5e918a92008-01-16 00:38:05 -0600423#define TSEC1_PHYIDX 0
Timur Tabi89c77842008-02-08 13:15:55 -0600424#endif
Kim Phillips5e918a92008-01-16 00:38:05 -0600425
Timur Tabi89c77842008-02-08 13:15:55 -0600426#ifdef CONFIG_TSEC2
427#define CONFIG_HAS_ETH1
428#define CONFIG_TSEC2_NAME "TSEC1"
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200429#define CONFIG_SYS_TSEC2_OFFSET 0x25000
Timur Tabi89c77842008-02-08 13:15:55 -0600430#define TSEC2_PHY_ADDR 0x1c
431#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED)
432#define TSEC2_PHYIDX 0
433#endif
Kim Phillips5e918a92008-01-16 00:38:05 -0600434
435/* Options are: TSEC[0-1] */
436#define CONFIG_ETHPRIME "TSEC0"
437
Timur Tabi89c77842008-02-08 13:15:55 -0600438#endif
439
Kim Phillips5e918a92008-01-16 00:38:05 -0600440/*
Kim Phillips730e7922008-03-28 14:31:23 -0500441 * SATA
442 */
443#define CONFIG_LIBATA
444#define CONFIG_FSL_SATA
445
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200446#define CONFIG_SYS_SATA_MAX_DEVICE 2
Kim Phillips730e7922008-03-28 14:31:23 -0500447#define CONFIG_SATA1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200448#define CONFIG_SYS_SATA1_OFFSET 0x18000
449#define CONFIG_SYS_SATA1 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA1_OFFSET)
450#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA
Kim Phillips730e7922008-03-28 14:31:23 -0500451#define CONFIG_SATA2
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200452#define CONFIG_SYS_SATA2_OFFSET 0x19000
453#define CONFIG_SYS_SATA2 (CONFIG_SYS_IMMR + CONFIG_SYS_SATA2_OFFSET)
454#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA
Kim Phillips730e7922008-03-28 14:31:23 -0500455
456#ifdef CONFIG_FSL_SATA
457#define CONFIG_LBA48
458#define CONFIG_CMD_SATA
459#define CONFIG_DOS_PARTITION
460#define CONFIG_CMD_EXT2
461#endif
462
463/*
Kim Phillips5e918a92008-01-16 00:38:05 -0600464 * Environment
465 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200466#ifndef CONFIG_SYS_RAMBOOT
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200467 #define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200468 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200469 #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for env */
470 #define CONFIG_ENV_SIZE 0x4000
Kim Phillips5e918a92008-01-16 00:38:05 -0600471#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200472 #define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
Jean-Christophe PLAGNIOL-VILLARD93f6d722008-09-10 22:48:00 +0200473 #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200474 #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-0x1000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200475 #define CONFIG_ENV_SIZE 0x2000
Kim Phillips5e918a92008-01-16 00:38:05 -0600476#endif
477
478#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200479#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
Kim Phillips5e918a92008-01-16 00:38:05 -0600480
481/*
482 * BOOTP options
483 */
484#define CONFIG_BOOTP_BOOTFILESIZE
485#define CONFIG_BOOTP_BOOTPATH
486#define CONFIG_BOOTP_GATEWAY
487#define CONFIG_BOOTP_HOSTNAME
488
489
490/*
491 * Command line configuration.
492 */
493#include <config_cmd_default.h>
494
495#define CONFIG_CMD_PING
496#define CONFIG_CMD_I2C
497#define CONFIG_CMD_MII
498#define CONFIG_CMD_DATE
499
500#if defined(CONFIG_PCI)
501#define CONFIG_CMD_PCI
502#endif
503
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200504#if defined(CONFIG_SYS_RAMBOOT)
Mike Frysingerbdab39d2009-01-28 19:08:14 -0500505#undef CONFIG_CMD_SAVEENV
Kim Phillips5e918a92008-01-16 00:38:05 -0600506#undef CONFIG_CMD_LOADS
507#endif
508
509#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Kim Phillipsa059e902010-04-15 17:36:05 -0500510#define CONFIG_AUTO_COMPLETE /* add autocompletion support */
Kim Phillips5e918a92008-01-16 00:38:05 -0600511
512#undef CONFIG_WATCHDOG /* watchdog disabled */
513
Anton Vorontsovc9646ed2009-06-10 00:25:30 +0400514#define CONFIG_MMC 1
515
516#ifdef CONFIG_MMC
517#define CONFIG_FSL_ESDHC
Chenhui Zhaoa6da8b82011-01-04 17:23:05 +0800518#define CONFIG_FSL_ESDHC_PIN_MUX
Anton Vorontsovc9646ed2009-06-10 00:25:30 +0400519#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR
520#define CONFIG_CMD_MMC
521#define CONFIG_GENERIC_MMC
522#define CONFIG_CMD_EXT2
523#define CONFIG_CMD_FAT
524#define CONFIG_DOS_PARTITION
525#endif
526
Kim Phillips5e918a92008-01-16 00:38:05 -0600527/*
528 * Miscellaneous configurable options
529 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200530#define CONFIG_SYS_LONGHELP /* undef to save memory */
531#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */
532#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Kim Phillips5e918a92008-01-16 00:38:05 -0600533
534#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200535 #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Kim Phillips5e918a92008-01-16 00:38:05 -0600536#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200537 #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Kim Phillips5e918a92008-01-16 00:38:05 -0600538#endif
539
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200540#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
541#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
542#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
543#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */
Kim Phillips5e918a92008-01-16 00:38:05 -0600544
545/*
546 * For booting Linux, the board info and command line data
Ira W. Snyder9f530d52010-09-10 15:42:32 -0700547 * have to be in the first 256 MB of memory, since this is
Kim Phillips5e918a92008-01-16 00:38:05 -0600548 * the maximum mapped by the Linux kernel during initialization.
549 */
Ira W. Snyder9f530d52010-09-10 15:42:32 -0700550#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */
Kim Phillips5e918a92008-01-16 00:38:05 -0600551
552/*
553 * Core HID Setup
554 */
Kim Phillips1a2e2032010-04-20 19:37:54 -0500555#define CONFIG_SYS_HID0_INIT 0x000000000
556#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \
557 HID0_ENABLE_INSTRUCTION_CACHE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200558#define CONFIG_SYS_HID2 HID2_HBE
Kim Phillips5e918a92008-01-16 00:38:05 -0600559
560/*
561 * MMU Setup
562 */
563
Becky Bruce31d82672008-05-08 19:02:12 -0500564#define CONFIG_HIGH_BATS 1 /* High BATs supported */
565
Kim Phillips5e918a92008-01-16 00:38:05 -0600566/* DDR: cache cacheable */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200567#define CONFIG_SYS_SDRAM_LOWER CONFIG_SYS_SDRAM_BASE
568#define CONFIG_SYS_SDRAM_UPPER (CONFIG_SYS_SDRAM_BASE + 0x10000000)
Kim Phillips5e918a92008-01-16 00:38:05 -0600569
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200570#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_LOWER | BATL_PP_10 | BATL_MEMCOHERENCE)
571#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_LOWER | BATU_BL_256M | BATU_VS | BATU_VP)
572#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L
573#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U
Kim Phillips5e918a92008-01-16 00:38:05 -0600574
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200575#define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_UPPER | BATL_PP_10 | BATL_MEMCOHERENCE)
576#define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_UPPER | BATU_BL_256M | BATU_VS | BATU_VP)
577#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L
578#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U
Kim Phillips5e918a92008-01-16 00:38:05 -0600579
580/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200581#define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR | BATL_PP_10 | \
Kim Phillips5e918a92008-01-16 00:38:05 -0600582 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200583#define CONFIG_SYS_IBAT2U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS | BATU_VP)
584#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L
585#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U
Kim Phillips5e918a92008-01-16 00:38:05 -0600586
587/* L2 Switch: cache-inhibit and guarded */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200588#define CONFIG_SYS_IBAT3L (CONFIG_SYS_VSC7385_BASE | BATL_PP_10 | \
Kim Phillips5e918a92008-01-16 00:38:05 -0600589 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200590#define CONFIG_SYS_IBAT3U (CONFIG_SYS_VSC7385_BASE | BATU_BL_128K | BATU_VS | BATU_VP)
591#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L
592#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U
Kim Phillips5e918a92008-01-16 00:38:05 -0600593
594/* FLASH: icache cacheable, but dcache-inhibit and guarded */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200595#define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | BATL_MEMCOHERENCE)
596#define CONFIG_SYS_IBAT4U (CONFIG_SYS_FLASH_BASE | BATU_BL_32M | BATU_VS | BATU_VP)
597#define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \
Kim Phillips5e918a92008-01-16 00:38:05 -0600598 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200599#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U
Kim Phillips5e918a92008-01-16 00:38:05 -0600600
601/* Stack in dcache: cacheable, no memory coherence */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200602#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10)
603#define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K | BATU_VS | BATU_VP)
604#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L
605#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U
Kim Phillips5e918a92008-01-16 00:38:05 -0600606
607#ifdef CONFIG_PCI
608/* PCI MEM space: cacheable */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200609#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS | BATL_PP_10 | BATL_MEMCOHERENCE)
610#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
611#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
612#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
Kim Phillips5e918a92008-01-16 00:38:05 -0600613/* PCI MMIO space: cache-inhibit and guarded */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200614#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS | BATL_PP_10 | \
Kim Phillips5e918a92008-01-16 00:38:05 -0600615 BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200616#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS | BATU_BL_256M | BATU_VS | BATU_VP)
617#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
618#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
Kim Phillips5e918a92008-01-16 00:38:05 -0600619#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200620#define CONFIG_SYS_IBAT6L (0)
621#define CONFIG_SYS_IBAT6U (0)
622#define CONFIG_SYS_IBAT7L (0)
623#define CONFIG_SYS_IBAT7U (0)
624#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L
625#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U
626#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L
627#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U
Kim Phillips5e918a92008-01-16 00:38:05 -0600628#endif
629
Kim Phillips5e918a92008-01-16 00:38:05 -0600630#if defined(CONFIG_CMD_KGDB)
631#define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */
632#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
633#endif
634
635/*
636 * Environment Configuration
637 */
638#define CONFIG_ENV_OVERWRITE
639
Anton Vorontsov18e69a32008-03-14 23:20:18 +0300640#define CONFIG_HAS_FSL_DR_USB
641
Kim Phillips5e918a92008-01-16 00:38:05 -0600642#define CONFIG_NETDEV eth1
643
644#define CONFIG_HOSTNAME mpc837x_rdb
645#define CONFIG_ROOTPATH /nfsroot
646#define CONFIG_RAMDISKFILE rootfs.ext2.gz.uboot
647#define CONFIG_BOOTFILE uImage
648#define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */
Kim Phillips270fe262008-03-07 12:27:31 -0600649#define CONFIG_FDTFILE mpc8379_rdb.dtb
Kim Phillips5e918a92008-01-16 00:38:05 -0600650
Kim Phillips79f516b2009-08-21 16:34:38 -0500651#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */
Kim Phillips7fd0bea2008-09-24 08:46:25 -0500652#define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */
Kim Phillips5e918a92008-01-16 00:38:05 -0600653#define CONFIG_BAUDRATE 115200
654
655#define XMK_STR(x) #x
656#define MK_STR(x) XMK_STR(x)
657
658#define CONFIG_EXTRA_ENV_SETTINGS \
659 "netdev=" MK_STR(CONFIG_NETDEV) "\0" \
660 "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \
661 "tftpflash=tftp $loadaddr $uboot;" \
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200662 "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
663 "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
664 "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \
665 "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \
666 "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \
Kim Phillips79f516b2009-08-21 16:34:38 -0500667 "fdtaddr=780000\0" \
Kim Phillips5e918a92008-01-16 00:38:05 -0600668 "fdtfile=" MK_STR(CONFIG_FDTFILE) "\0" \
669 "ramdiskaddr=1000000\0" \
670 "ramdiskfile=" MK_STR(CONFIG_RAMDISKFILE) "\0" \
671 "console=ttyS0\0" \
672 "setbootargs=setenv bootargs " \
673 "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \
674 "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \
675 "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \
676 "root=$rootdev rw console=$console,$baudrate $othbootargs\0"
677
678#define CONFIG_NFSBOOTCOMMAND \
679 "setenv rootdev /dev/nfs;" \
680 "run setbootargs;" \
681 "run setipargs;" \
682 "tftp $loadaddr $bootfile;" \
683 "tftp $fdtaddr $fdtfile;" \
684 "bootm $loadaddr - $fdtaddr"
685
686#define CONFIG_RAMBOOTCOMMAND \
687 "setenv rootdev /dev/ram;" \
688 "run setbootargs;" \
689 "tftp $ramdiskaddr $ramdiskfile;" \
690 "tftp $loadaddr $bootfile;" \
691 "tftp $fdtaddr $fdtfile;" \
692 "bootm $loadaddr $ramdiskaddr $fdtaddr"
693
694#undef MK_STR
695#undef XMK_STR
696
697#endif /* __CONFIG_H */