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Heiko Schocherfa230442006-12-21 17:17:02 +01001/*
2 * (C) Copyright 2006
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
4 *
5 * See file CREDITS for list of people who contributed to this
6 * project.
7 *
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
12 *
13 * This program is distributed in the hope that it will be useful,
14 * but WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 * GNU General Public License for more details.
17 *
18 * You should have received a copy of the GNU General Public License
19 * along with this program; if not, write to the Free Software
20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
21 * MA 02111-1307 USA
22 */
23
24/*
25 * board/config.h - configuration options, board specific
26 */
27
28#ifndef __CONFIG_H
29#define __CONFIG_H
30
31/*
32 * High Level Configuration Options
33 * (easy to change)
34 */
35
36#define CONFIG_MPC8260 1 /* This is a MPC8260 CPU */
37#define CONFIG_MPC8272_FAMILY 1
38#define CONFIG_TQM8272 1
39
Wolfgang Denk2ae18242010-10-06 09:05:45 +020040#define CONFIG_SYS_TEXT_BASE 0x40000000
41
Heiko Schocherfa230442006-12-21 17:17:02 +010042#define CONFIG_GET_CPU_STR_F 1 /* Get the CPU ID STR */
Wolfgang Denk9c0f42e2006-12-24 01:42:57 +010043#define CONFIG_BOARD_GET_CPU_CLK_F 1 /* Get the CLKIN from board fct */
44
Heiko Schocherfa230442006-12-21 17:17:02 +010045#define STK82xx_150 1 /* on a STK82xx.150 */
46
47#define CONFIG_CPM2 1 /* Has a CPM2 */
48
49#define CONFIG_82xx_CONS_SMC1 1 /* console on SMC1 */
50
51#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
52
53#define CONFIG_BOARD_EARLY_INIT_R 1
54
55#if defined(CONFIG_CONS_NONE) || defined(CONFIG_CONS_USE_EXTC)
56#define CONFIG_BAUDRATE 230400
57#else
58#define CONFIG_BAUDRATE 115200
59#endif
60
Wolfgang Denk32bf3d12008-03-03 12:16:44 +010061#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
Heiko Schocherfa230442006-12-21 17:17:02 +010062
63#undef CONFIG_BOOTARGS
64
65#define CONFIG_EXTRA_ENV_SETTINGS \
66 "netdev=eth0\0" \
67 "consdev=ttyCPM0\0" \
68 "nfsargs=setenv bootargs root=/dev/nfs rw " \
69 "nfsroot=${serverip}:${rootpath}\0" \
70 "ramargs=setenv bootargs root=/dev/ram rw\0" \
71 "hostname=tqm8272\0" \
72 "addip=setenv bootargs ${bootargs} " \
73 "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
74 ":${hostname}:${netdev}:off panic=1\0" \
75 "addcons=setenv bootargs ${bootargs} " \
Wolfgang Denk9c0f42e2006-12-24 01:42:57 +010076 "console=$(consdev),$(baudrate)\0" \
77 "flash_nfs=run nfsargs addip addcons;" \
Heiko Schocherfa230442006-12-21 17:17:02 +010078 "bootm ${kernel_addr}\0" \
Wolfgang Denk9c0f42e2006-12-24 01:42:57 +010079 "flash_self=run ramargs addip addcons;" \
Heiko Schocherfa230442006-12-21 17:17:02 +010080 "bootm ${kernel_addr} ${ramdisk_addr}\0" \
81 "net_nfs=tftp 300000 ${bootfile};" \
Wolfgang Denk9c0f42e2006-12-24 01:42:57 +010082 "run nfsargs addip addcons;bootm\0" \
Heiko Schocherfa230442006-12-21 17:17:02 +010083 "rootpath=/opt/eldk/ppc_82xx\0" \
84 "bootfile=/tftpboot/tqm8272/uImage\0" \
85 "kernel_addr=40080000\0" \
86 "ramdisk_addr=40100000\0" \
87 "load=tftp 300000 /tftpboot/tqm8272/u-boot.bin\0" \
88 "update=protect off 40000000 4003ffff;era 40000000 4003ffff;" \
89 "cp.b 300000 40000000 40000;" \
90 "setenv filesize;saveenv\0" \
Wolfgang Denk9c0f42e2006-12-24 01:42:57 +010091 "cphwib=cp.b 4003fc00 33fc00 400\0" \
Detlev Zundeld8ab58b2008-03-06 16:45:53 +010092 "upd=run load cphwib update\0" \
Heiko Schocherfa230442006-12-21 17:17:02 +010093 ""
94#define CONFIG_BOOTCOMMAND "run flash_self"
95
96#define CONFIG_I2C 1
97
98#if CONFIG_I2C
99/* enable I2C and select the hardware/software driver */
100#undef CONFIG_HARD_I2C /* I2C with hardware support */
101#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200102#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
103#define CONFIG_SYS_I2C_SLAVE 0x7F
Heiko Schocherfa230442006-12-21 17:17:02 +0100104
105/*
106 * Software (bit-bang) I2C driver configuration
107 */
108#define I2C_PORT 3 /* Port A=0, B=1, C=2, D=3 */
109#define I2C_ACTIVE (iop->pdir |= 0x00010000)
110#define I2C_TRISTATE (iop->pdir &= ~0x00010000)
111#define I2C_READ ((iop->pdat & 0x00010000) != 0)
112#define I2C_SDA(bit) if(bit) iop->pdat |= 0x00010000; \
113 else iop->pdat &= ~0x00010000
114#define I2C_SCL(bit) if(bit) iop->pdat |= 0x00020000; \
115 else iop->pdat &= ~0x00020000
116#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
117
118#define CONFIG_I2C_X
119
120/* EEPROM */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200121#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
122#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 4
123#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */
124#define CONFIG_SYS_I2C_MULTI_EEPROMS 1 /* more than one eeprom */
Heiko Schocherfa230442006-12-21 17:17:02 +0100125
126/* I2C RTC */
127#define CONFIG_RTC_DS1337 /* Use ds1337 rtc via i2c */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200128#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
Heiko Schocherfa230442006-12-21 17:17:02 +0100129
130/* I2C SYSMON (LM75) */
131#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
132#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200133#define CONFIG_SYS_DTT_MAX_TEMP 70
134#define CONFIG_SYS_DTT_LOW_TEMP -30
135#define CONFIG_SYS_DTT_HYSTERESIS 3
Heiko Schocherfa230442006-12-21 17:17:02 +0100136
137#else
138#undef CONFIG_HARD_I2C
139#undef CONFIG_SOFT_I2C
Heiko Schocherfa230442006-12-21 17:17:02 +0100140#endif
141
142/*
143 * select serial console configuration
144 *
145 * if either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then
146 * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4
147 * for SCC).
148 *
149 * if CONFIG_CONS_NONE is defined, then the serial console routines must
150 * defined elsewhere (for example, on the cogent platform, there are serial
151 * ports on the motherboard which are used for the serial console - see
152 * cogent/cma101/serial.[ch]).
153 */
154#define CONFIG_CONS_ON_SMC /* define if console on SMC */
155#undef CONFIG_CONS_ON_SCC /* define if console on SCC */
156#undef CONFIG_CONS_NONE /* define if console on something else*/
157#ifdef CONFIG_82xx_CONS_SMC1
158#define CONFIG_CONS_INDEX 1 /* which serial channel for console */
159#endif
160#ifdef CONFIG_82xx_CONS_SMC2
161#define CONFIG_CONS_INDEX 2 /* which serial channel for console */
162#endif
163
164#undef CONFIG_CONS_USE_EXTC /* SMC/SCC use ext clock not brg_clk */
165#define CONFIG_CONS_EXTC_RATE 3686400 /* SMC/SCC ext clk rate in Hz */
166#define CONFIG_CONS_EXTC_PINSEL 0 /* pin select 0=CLK3/CLK9 */
167
168/*
169 * select ethernet configuration
170 *
171 * if either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, then
172 * CONFIG_ETHER_INDEX must be set to the channel number (1-4 for SCC, 1-3
173 * for FCC)
174 *
175 * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
Jon Loeliger639221c2007-07-09 17:15:49 -0500176 * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
Heiko Schocherfa230442006-12-21 17:17:02 +0100177 *
178 * (On TQM8272 either SCC1 or FCC2 may be chosen: SCC1 is hardwired to the
179 * X.29 connector, and FCC2 is hardwired to the X.1 connector)
180 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200181#define CONFIG_SYS_FCC_ETHERNET
Heiko Schocherfa230442006-12-21 17:17:02 +0100182
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200183#if defined(CONFIG_SYS_FCC_ETHERNET)
Heiko Schocherfa230442006-12-21 17:17:02 +0100184#undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */
185#define CONFIG_ETHER_ON_FCC /* define if ether on FCC */
186#undef CONFIG_ETHER_NONE /* define if ether on something else */
187#define CONFIG_ETHER_INDEX 2 /* which SCC/FCC channel for ethernet */
188#else
189#define CONFIG_ETHER_ON_SCC /* define if ether on SCC */
190#undef CONFIG_ETHER_ON_FCC /* define if ether on FCC */
191#undef CONFIG_ETHER_NONE /* define if ether on something else */
192#define CONFIG_ETHER_INDEX 1 /* which SCC/FCC channel for ethernet */
193#endif
194
195#if defined(CONFIG_ETHER_ON_SCC) && (CONFIG_ETHER_INDEX == 1)
196
197/*
198 * - RX clk is CLK11
199 * - TX clk is CLK12
200 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200201# define CONFIG_SYS_CMXSCR_VALUE (CMXSCR_RS1CS_CLK11 | CMXSCR_TS1CS_CLK12)
Heiko Schocherfa230442006-12-21 17:17:02 +0100202
203#elif defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2)
204
205/*
206 * - Rx-CLK is CLK13
207 * - Tx-CLK is CLK14
208 * - RAM for BD/Buffers is on the 60x Bus (see 28-13)
209 * - Enable Full Duplex in FSMR
210 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200211# define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC2|CMXFCR_RF2CS_MSK|CMXFCR_TF2CS_MSK)
212# define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13|CMXFCR_TF2CS_CLK14)
213# define CONFIG_SYS_CPMFCR_RAMTYPE 0
214# define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB)
Heiko Schocherfa230442006-12-21 17:17:02 +0100215
216#endif /* CONFIG_ETHER_ON_FCC, CONFIG_ETHER_INDEX */
217
218#define CONFIG_MII /* MII PHY management */
219#define CONFIG_BITBANGMII /* bit-bang MII PHY management */
220/*
221 * GPIO pins used for bit-banged MII communications
222 */
223#define MDIO_PORT 2 /* Port C */
Luigi 'Comio' Mantellinibe225442009-10-10 12:42:22 +0200224#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \
225 (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT )
226#define MDC_DECLARE MDIO_DECLARE
Heiko Schocherfa230442006-12-21 17:17:02 +0100227
228#if STK82xx_150
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200229#define CONFIG_SYS_MDIO_PIN 0x00008000 /* PC16 */
230#define CONFIG_SYS_MDC_PIN 0x00004000 /* PC17 */
Heiko Schocherfa230442006-12-21 17:17:02 +0100231#endif
232
233#if STK82xx_100
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200234#define CONFIG_SYS_MDIO_PIN 0x00000002 /* PC30 */
235#define CONFIG_SYS_MDC_PIN 0x00000001 /* PC31 */
Heiko Schocherfa230442006-12-21 17:17:02 +0100236#endif
237
238#if 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200239#define MDIO_ACTIVE (iop->pdir |= CONFIG_SYS_MDIO_PIN)
240#define MDIO_TRISTATE (iop->pdir &= ~CONFIG_SYS_MDIO_PIN)
241#define MDIO_READ ((iop->pdat & CONFIG_SYS_MDIO_PIN) != 0)
Heiko Schocherfa230442006-12-21 17:17:02 +0100242
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200243#define MDIO(bit) if(bit) iop->pdat |= CONFIG_SYS_MDIO_PIN; \
244 else iop->pdat &= ~CONFIG_SYS_MDIO_PIN
Heiko Schocherfa230442006-12-21 17:17:02 +0100245
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200246#define MDC(bit) if(bit) iop->pdat |= CONFIG_SYS_MDC_PIN; \
247 else iop->pdat &= ~CONFIG_SYS_MDC_PIN
Heiko Schocherfa230442006-12-21 17:17:02 +0100248#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200249#define MDIO_ACTIVE ({unsigned long tmp; tmp = iop->pdir; tmp |= CONFIG_SYS_MDIO_PIN; iop->pdir = tmp;})
250#define MDIO_TRISTATE ({unsigned long tmp; tmp = iop->pdir; tmp &= ~CONFIG_SYS_MDIO_PIN; iop->pdir = tmp;})
251#define MDIO_READ ((iop->pdat & CONFIG_SYS_MDIO_PIN) != 0)
Heiko Schocherfa230442006-12-21 17:17:02 +0100252
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200253#define MDIO(bit) if(bit) {unsigned long tmp; tmp = iop->pdat; tmp |= CONFIG_SYS_MDIO_PIN; iop->pdat = tmp;}\
254 else {unsigned long tmp; tmp = iop->pdat; tmp &= ~CONFIG_SYS_MDIO_PIN; iop->pdat = tmp;}
Heiko Schocherfa230442006-12-21 17:17:02 +0100255
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200256#define MDC(bit) if(bit) {unsigned long tmp; tmp = iop->pdat; tmp |= CONFIG_SYS_MDC_PIN; iop->pdat = tmp;}\
257 else {unsigned long tmp; tmp = iop->pdat; tmp &= ~CONFIG_SYS_MDC_PIN; iop->pdat = tmp;}
Heiko Schocherfa230442006-12-21 17:17:02 +0100258#endif
259
260#define MIIDELAY udelay(1)
261
262
Heiko Schocherfa230442006-12-21 17:17:02 +0100263/* system clock rate (CLKIN) - equal to the 60x and local bus speed */
264#define CONFIG_8260_CLKIN 66666666 /* in Hz */
265
266#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200267#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
Heiko Schocherfa230442006-12-21 17:17:02 +0100268
269#undef CONFIG_WATCHDOG /* watchdog disabled */
270
271#define CONFIG_TIMESTAMP /* Print image info with timestamp */
272
Jon Loeliger37d4bb72007-07-09 21:38:02 -0500273/*
274 * BOOTP options
275 */
276#define CONFIG_BOOTP_SUBNETMASK
277#define CONFIG_BOOTP_GATEWAY
278#define CONFIG_BOOTP_HOSTNAME
279#define CONFIG_BOOTP_BOOTPATH
280#define CONFIG_BOOTP_BOOTFILESIZE
Heiko Schocherfa230442006-12-21 17:17:02 +0100281
Heiko Schocherfa230442006-12-21 17:17:02 +0100282
Jon Loeliger26946902007-07-04 22:30:50 -0500283/*
284 * Command line configuration.
285 */
286#include <config_cmd_default.h>
287
288#define CONFIG_CMD_I2C
289#define CONFIG_CMD_DHCP
290#define CONFIG_CMD_MII
291#define CONFIG_CMD_NAND
292#define CONFIG_CMD_NFS
293#define CONFIG_CMD_PCI
294#define CONFIG_CMD_PING
295#define CONFIG_CMD_SNTP
296
Jon Loeligera1aa0bb2007-07-10 09:22:23 -0500297#if CONFIG_I2C
298 #define CONFIG_CMD_I2C
299 #define CONFIG_CMD_DATE
300 #define CONFIG_CMD_DTT
301 #define CONFIG_CMD_EEPROM
302#endif
303
Heiko Schocherfa230442006-12-21 17:17:02 +0100304
305/*
306 * Miscellaneous configurable options
307 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200308#define CONFIG_SYS_LONGHELP /* undef to save memory */
309#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
Heiko Schocherfa230442006-12-21 17:17:02 +0100310
311#if 0
312#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200313#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
314#ifdef CONFIG_SYS_HUSH_PARSER
315#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
Heiko Schocherfa230442006-12-21 17:17:02 +0100316#endif
317#endif
318
Jon Loeliger26946902007-07-04 22:30:50 -0500319#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200320#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
Heiko Schocherfa230442006-12-21 17:17:02 +0100321#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200322#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
Heiko Schocherfa230442006-12-21 17:17:02 +0100323#endif
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200324#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
325#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
326#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
Heiko Schocherfa230442006-12-21 17:17:02 +0100327
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200328#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
329#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
Heiko Schocherfa230442006-12-21 17:17:02 +0100330
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200331#define CONFIG_SYS_LOAD_ADDR 0x300000 /* default load address */
Heiko Schocherfa230442006-12-21 17:17:02 +0100332
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200333#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
Heiko Schocherfa230442006-12-21 17:17:02 +0100334
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200335#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
Heiko Schocherfa230442006-12-21 17:17:02 +0100336
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200337#define CONFIG_SYS_RESET_ADDRESS 0x40000104 /* "bad" address */
Heiko Schocherfa230442006-12-21 17:17:02 +0100338
339/*
340 * For booting Linux, the board info and command line data
341 * have to be in the first 8 MB of memory, since this is
342 * the maximum mapped by the Linux kernel during initialization.
343 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200344#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
Heiko Schocherfa230442006-12-21 17:17:02 +0100345
346/*-----------------------------------------------------------------------
347 * CAN stuff
348 *-----------------------------------------------------------------------
349 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200350#define CONFIG_SYS_CAN_BASE 0x51000000
351#define CONFIG_SYS_CAN_SIZE 1
352#define CONFIG_SYS_CAN_BR ((CONFIG_SYS_CAN_BASE & BRx_BA_MSK) |\
Heiko Schocherfa230442006-12-21 17:17:02 +0100353 BRx_PS_8 |\
354 BRx_MS_UPMC |\
355 BRx_V)
356
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200357#define CONFIG_SYS_CAN_OR (MEG_TO_AM(CONFIG_SYS_CAN_SIZE) |\
Heiko Schocherfa230442006-12-21 17:17:02 +0100358 ORxU_BI)
359
360
361/* What should the base address of the main FLASH be and how big is
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200362 * it (in MBytes)? This must contain CONFIG_SYS_TEXT_BASE from board/tqm8272/config.mk
Heiko Schocherfa230442006-12-21 17:17:02 +0100363 * The main FLASH is whichever is connected to *CS0.
364 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200365#define CONFIG_SYS_FLASH0_BASE 0x40000000
366#define CONFIG_SYS_FLASH0_SIZE 32 /* 32 MB */
Heiko Schocherfa230442006-12-21 17:17:02 +0100367
368/* Flash bank size (for preliminary settings)
369 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200370#define CONFIG_SYS_FLASH_SIZE CONFIG_SYS_FLASH0_SIZE
Heiko Schocherfa230442006-12-21 17:17:02 +0100371
372/*-----------------------------------------------------------------------
373 * FLASH organization
374 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200375#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max num of memory banks */
376#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max num of sects on one chip */
Heiko Schocherfa230442006-12-21 17:17:02 +0100377
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200378#define CONFIG_SYS_FLASH_CFI /* flash is CFI compat. */
Jean-Christophe PLAGNIOL-VILLARD00b18832008-08-13 01:40:42 +0200379#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver*/
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200380#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector */
381#define CONFIG_SYS_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash*/
Heiko Schocherfa230442006-12-21 17:17:02 +0100382
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200383#define CONFIG_SYS_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */
384#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */
Heiko Schocherfa230442006-12-21 17:17:02 +0100385
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200386#define CONFIG_SYS_UPDATE_FLASH_SIZE
Heiko Schocherfa230442006-12-21 17:17:02 +0100387
Jean-Christophe PLAGNIOL-VILLARD5a1aceb2008-09-10 22:48:04 +0200388#define CONFIG_ENV_IS_IN_FLASH 1
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200389#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x40000)
Jean-Christophe PLAGNIOL-VILLARD0e8d1582008-09-10 22:48:06 +0200390#define CONFIG_ENV_SIZE 0x20000
391#define CONFIG_ENV_SECT_SIZE 0x20000
392#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR + CONFIG_ENV_SIZE)
393#define CONFIG_ENV_SIZE_REDUND 0x20000
Heiko Schocherfa230442006-12-21 17:17:02 +0100394
395/* Where is the Hardwareinformation Block (from Monitor Sources) */
396#define MON_RES_LENGTH (0x0003FC00)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200397#define HWIB_INFO_START_ADDR (CONFIG_SYS_FLASH_BASE + MON_RES_LENGTH)
Heiko Schocherfa230442006-12-21 17:17:02 +0100398#define HWIB_INFO_LEN 512
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200399#define CIB_INFO_START_ADDR (CONFIG_SYS_FLASH_BASE + MON_RES_LENGTH + HWIB_INFO_LEN)
Heiko Schocherfa230442006-12-21 17:17:02 +0100400#define CIB_INFO_LEN 512
401
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200402#define CONFIG_SYS_HWINFO_OFFSET 0x3fc00 /* offset of HW Info block */
403#define CONFIG_SYS_HWINFO_SIZE 0x00000060 /* size of HW Info block */
404#define CONFIG_SYS_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */
Heiko Schocherfa230442006-12-21 17:17:02 +0100405
406/*-----------------------------------------------------------------------
407 * NAND-FLASH stuff
408 *-----------------------------------------------------------------------
409 */
Jon Loeliger26946902007-07-04 22:30:50 -0500410#if defined(CONFIG_CMD_NAND)
Heiko Schocherfa230442006-12-21 17:17:02 +0100411
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200412#define CONFIG_SYS_NAND_CS_DIST 0x80
413#define CONFIG_SYS_NAND_UPM_WRITE_CMD_OFS 0x20
414#define CONFIG_SYS_NAND_UPM_WRITE_ADDR_OFS 0x40
Heiko Schocherfa230442006-12-21 17:17:02 +0100415
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200416#define CONFIG_SYS_NAND_BR ((CONFIG_SYS_NAND0_BASE & BRx_BA_MSK) |\
Heiko Schocherfa230442006-12-21 17:17:02 +0100417 BRx_PS_8 |\
418 BRx_MS_UPMB |\
419 BRx_V)
420
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200421#define CONFIG_SYS_NAND_OR (MEG_TO_AM(CONFIG_SYS_NAND_SIZE) |\
Heiko Schocherfa230442006-12-21 17:17:02 +0100422 ORxU_BI |\
423 ORxU_EHTR_8IDLE)
424
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200425#define CONFIG_SYS_NAND_SIZE 1
426#define CONFIG_SYS_NAND0_BASE 0x50000000
427#define CONFIG_SYS_NAND1_BASE (CONFIG_SYS_NAND0_BASE + CONFIG_SYS_NAND_CS_DIST)
428#define CONFIG_SYS_NAND2_BASE (CONFIG_SYS_NAND1_BASE + CONFIG_SYS_NAND_CS_DIST)
429#define CONFIG_SYS_NAND3_BASE (CONFIG_SYS_NAND2_BASE + CONFIG_SYS_NAND_CS_DIST)
Heiko Schocherfa230442006-12-21 17:17:02 +0100430
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200431#define CONFIG_SYS_MAX_NAND_DEVICE 4 /* Max number of NAND devices */
Heiko Schocherfa230442006-12-21 17:17:02 +0100432
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200433#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND0_BASE, \
434 CONFIG_SYS_NAND1_BASE, \
435 CONFIG_SYS_NAND2_BASE, \
436 CONFIG_SYS_NAND3_BASE, \
Heiko Schocherfa230442006-12-21 17:17:02 +0100437 }
438
439#define WRITE_NAND(d, adr) do{ *(volatile __u8 *)((unsigned long)(adr)) = (__u8)d; } while(0)
440#define READ_NAND(adr) ((volatile unsigned char)(*(volatile __u8 *)(unsigned long)(adr)))
441#define WRITE_NAND_UPM(d, adr, off) do \
442{ \
443 volatile unsigned char *addr = (unsigned char *) (adr + off); \
444 WRITE_NAND(d, addr); \
445} while(0)
446
Jon Loeligera1aa0bb2007-07-10 09:22:23 -0500447#endif /* CONFIG_CMD_NAND */
Heiko Schocherfa230442006-12-21 17:17:02 +0100448
449#define CONFIG_PCI
450#ifdef CONFIG_PCI
451#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */
452#define CONFIG_PCI_PNP
453#define CONFIG_EEPRO100
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200454#define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */
Heiko Schocherfa230442006-12-21 17:17:02 +0100455#define CONFIG_PCI_SCAN_SHOW
456#endif
457
458/*-----------------------------------------------------------------------
459 * Hard Reset Configuration Words
460 *
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200461 * if you change bits in the HRCW, you must also change the CONFIG_SYS_*
Heiko Schocherfa230442006-12-21 17:17:02 +0100462 * defines for the various registers affected by the HRCW e.g. changing
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200463 * HRCW_DPPCxx requires you to also change CONFIG_SYS_SIUMCR.
Heiko Schocherfa230442006-12-21 17:17:02 +0100464 */
465#if 0
466#define __HRCW__ALL__ (HRCW_CIP | HRCW_ISB111 | HRCW_BMS)
467
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200468# define CONFIG_SYS_HRCW_MASTER (__HRCW__ALL__ | HRCW_MODCK_H0111)
Heiko Schocherfa230442006-12-21 17:17:02 +0100469#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200470#define CONFIG_SYS_HRCW_MASTER (HRCW_BPS11 | HRCW_ISB111 | HRCW_BMS | HRCW_MODCK_H0111)
Heiko Schocherfa230442006-12-21 17:17:02 +0100471#endif
472
473/* no slaves so just fill with zeros */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200474#define CONFIG_SYS_HRCW_SLAVE1 0
475#define CONFIG_SYS_HRCW_SLAVE2 0
476#define CONFIG_SYS_HRCW_SLAVE3 0
477#define CONFIG_SYS_HRCW_SLAVE4 0
478#define CONFIG_SYS_HRCW_SLAVE5 0
479#define CONFIG_SYS_HRCW_SLAVE6 0
480#define CONFIG_SYS_HRCW_SLAVE7 0
Heiko Schocherfa230442006-12-21 17:17:02 +0100481
482/*-----------------------------------------------------------------------
483 * Internal Memory Mapped Register
484 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200485#define CONFIG_SYS_IMMR 0xFFF00000
Heiko Schocherfa230442006-12-21 17:17:02 +0100486
487/*-----------------------------------------------------------------------
488 * Definitions for initial stack pointer and data area (in DPRAM)
489 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200490#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
Wolfgang Denk553f0982010-10-26 13:32:32 +0200491#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in DPRAM */
Wolfgang Denk25ddd1f2010-10-26 14:34:52 +0200492#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200493#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
Heiko Schocherfa230442006-12-21 17:17:02 +0100494
495/*-----------------------------------------------------------------------
496 * Start addresses for the final memory configuration
497 * (Set up by the startup code)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200498 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
Heiko Schocherfa230442006-12-21 17:17:02 +0100499 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200500#define CONFIG_SYS_SDRAM_BASE 0x00000000
501#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_FLASH0_BASE
Wolfgang Denk14d0a022010-10-07 21:51:12 +0200502#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200503#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
504#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc()*/
Heiko Schocherfa230442006-12-21 17:17:02 +0100505
Heiko Schocherfa230442006-12-21 17:17:02 +0100506/*-----------------------------------------------------------------------
507 * Cache Configuration
508 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200509#define CONFIG_SYS_CACHELINE_SIZE 32 /* For MPC8260 CPU */
Jon Loeliger26946902007-07-04 22:30:50 -0500510#if defined(CONFIG_CMD_KGDB)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200511# define CONFIG_SYS_CACHELINE_SHIFT 5 /* log base 2 of the above value */
Heiko Schocherfa230442006-12-21 17:17:02 +0100512#endif
513
514/*-----------------------------------------------------------------------
515 * HIDx - Hardware Implementation-dependent Registers 2-11
516 *-----------------------------------------------------------------------
517 * HID0 also contains cache control - initially enable both caches and
518 * invalidate contents, then the final state leaves only the instruction
519 * cache enabled. Note that Power-On and Hard reset invalidate the caches,
520 * but Soft reset does not.
521 *
522 * HID1 has only read-only information - nothing to set.
523 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200524#define CONFIG_SYS_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|HID0_DCI|\
Heiko Schocherfa230442006-12-21 17:17:02 +0100525 HID0_IFEM|HID0_ABE)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200526#define CONFIG_SYS_HID0_FINAL (HID0_IFEM|HID0_ABE)
527#define CONFIG_SYS_HID2 0
Heiko Schocherfa230442006-12-21 17:17:02 +0100528
529/*-----------------------------------------------------------------------
530 * RMR - Reset Mode Register 5-5
531 *-----------------------------------------------------------------------
532 * turn on Checkstop Reset Enable
533 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200534#define CONFIG_SYS_RMR RMR_CSRE
Heiko Schocherfa230442006-12-21 17:17:02 +0100535
536/*-----------------------------------------------------------------------
537 * BCR - Bus Configuration 4-25
538 *-----------------------------------------------------------------------
539 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200540#define CONFIG_SYS_BCR_60x (BCR_EBM|BCR_NPQM0|BCR_NPQM2) /* 60x mode */
Heiko Schocherfa230442006-12-21 17:17:02 +0100541#define BCR_APD01 0x10000000
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200542#define CONFIG_SYS_BCR_SINGLE (BCR_APD01|BCR_ETM) /* 8260 mode */
Heiko Schocherfa230442006-12-21 17:17:02 +0100543
544/*-----------------------------------------------------------------------
545 * SIUMCR - SIU Module Configuration 4-31
546 *-----------------------------------------------------------------------
547 */
548#if defined(CONFIG_BOARD_GET_CPU_CLK_F)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200549#define CONFIG_SYS_SIUMCR_LOW (SIUMCR_DPPC00)
550#define CONFIG_SYS_SIUMCR_HIGH (SIUMCR_DPPC00 | SIUMCR_ABE)
Heiko Schocherfa230442006-12-21 17:17:02 +0100551#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200552#define CONFIG_SYS_SIUMCR (SIUMCR_DPPC00)
Heiko Schocherfa230442006-12-21 17:17:02 +0100553#endif
554
555/*-----------------------------------------------------------------------
556 * SYPCR - System Protection Control 4-35
557 * SYPCR can only be written once after reset!
558 *-----------------------------------------------------------------------
559 * Watchdog & Bus Monitor Timer max, 60x Bus Monitor enable
560 */
561#if defined(CONFIG_WATCHDOG)
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200562#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
Heiko Schocherfa230442006-12-21 17:17:02 +0100563 SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE)
564#else
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200565#define CONFIG_SYS_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\
Heiko Schocherfa230442006-12-21 17:17:02 +0100566 SYPCR_SWRI|SYPCR_SWP)
567#endif /* CONFIG_WATCHDOG */
568
569/*-----------------------------------------------------------------------
570 * TMCNTSC - Time Counter Status and Control 4-40
571 *-----------------------------------------------------------------------
572 * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk,
573 * and enable Time Counter
574 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200575#define CONFIG_SYS_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE)
Heiko Schocherfa230442006-12-21 17:17:02 +0100576
577/*-----------------------------------------------------------------------
578 * PISCR - Periodic Interrupt Status and Control 4-42
579 *-----------------------------------------------------------------------
580 * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable
581 * Periodic timer
582 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200583#define CONFIG_SYS_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE)
Heiko Schocherfa230442006-12-21 17:17:02 +0100584
585/*-----------------------------------------------------------------------
586 * SCCR - System Clock Control 9-8
587 *-----------------------------------------------------------------------
588 * Ensure DFBRG is Divide by 16
589 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200590#define CONFIG_SYS_SCCR SCCR_DFBRG01
Heiko Schocherfa230442006-12-21 17:17:02 +0100591
592/*-----------------------------------------------------------------------
593 * RCCR - RISC Controller Configuration 13-7
594 *-----------------------------------------------------------------------
595 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200596#define CONFIG_SYS_RCCR 0
Heiko Schocherfa230442006-12-21 17:17:02 +0100597
598/*
599 * Init Memory Controller:
600 *
601 * Bank Bus Machine PortSz Device
602 * ---- --- ------- ------ ------
603 * 0 60x GPCM 32 bit FLASH
604 * 1 60x SDRAM 64 bit SDRAM
605 * 2 60x UPMB 8 bit NAND
Wolfgang Denk9c0f42e2006-12-24 01:42:57 +0100606 * 3 60x UPMC 8 bit CAN
Heiko Schocherfa230442006-12-21 17:17:02 +0100607 *
608 */
609
610/* Initialize SDRAM
611 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200612#undef CONFIG_SYS_INIT_LOCAL_SDRAM /* No SDRAM on Local Bus */
Heiko Schocherfa230442006-12-21 17:17:02 +0100613
614#define SDRAM_MAX_SIZE 0x20000000 /* max. 512 MB */
615
616/* Minimum mask to separate preliminary
617 * address ranges for CS[0:2]
618 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200619#define CONFIG_SYS_GLOBAL_SDRAM_LIMIT (512<<20) /* less than 512 MB */
Heiko Schocherfa230442006-12-21 17:17:02 +0100620
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200621#define CONFIG_SYS_MPTPR 0x4000
Heiko Schocherfa230442006-12-21 17:17:02 +0100622
623/*-----------------------------------------------------------------------------
624 * Address for Mode Register Set (MRS) command
625 *-----------------------------------------------------------------------------
626 * In fact, the address is rather configuration data presented to the SDRAM on
627 * its address lines. Because the address lines may be mux'ed externally either
628 * for 8 column or 9 column devices, some bits appear twice in the 8260's
629 * address:
630 *
631 * | (RFU) | (RFU) | WBL | TM | CL | BT | Burst Length |
632 * | BA1 BA0 | A12 : A10 | A9 | A8 A7 | A6 : A4 | A3 | A2 : A0 |
633 * 8 columns mux'ing: | A9 | A10 A21 | A22 : A24 | A25 | A26 : A28 |
634 * 9 columns mux'ing: | A8 | A20 A21 | A22 : A24 | A25 | A26 : A28 |
635 * Settings: | 0 | 0 0 | 0 1 0 | 0 | 0 1 0 |
636 *-----------------------------------------------------------------------------
637 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200638#define CONFIG_SYS_MRS_OFFS 0x00000110
Heiko Schocherfa230442006-12-21 17:17:02 +0100639
Heiko Schocherfa230442006-12-21 17:17:02 +0100640/* Bank 0 - FLASH
641 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200642#define CONFIG_SYS_BR0_PRELIM ((CONFIG_SYS_FLASH_BASE & BRx_BA_MSK) |\
Heiko Schocherfa230442006-12-21 17:17:02 +0100643 BRx_PS_32 |\
644 BRx_MS_GPCM_P |\
645 BRx_V)
646
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200647#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) |\
Heiko Schocherfa230442006-12-21 17:17:02 +0100648 ORxG_CSNT |\
649 ORxG_ACS_DIV4 |\
650 ORxG_SCY_8_CLK |\
651 ORxG_TRLX)
652
653/* SDRAM on TQM8272 can have either 8 or 9 columns.
654 * The number affects configuration values.
655 */
656
657/* Bank 1 - 60x bus SDRAM
658 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200659#define CONFIG_SYS_PSRT 0x20 /* Low Value */
660/* #define CONFIG_SYS_PSRT 0x10 Fast Value */
661#define CONFIG_SYS_LSRT 0x20 /* Local Bus */
662#ifndef CONFIG_SYS_RAMBOOT
663#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM_BASE & BRx_BA_MSK) |\
Heiko Schocherfa230442006-12-21 17:17:02 +0100664 BRx_PS_64 |\
665 BRx_MS_SDRAM_P |\
666 BRx_V)
667
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200668#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_OR1_8COL
Heiko Schocherfa230442006-12-21 17:17:02 +0100669
670/* SDRAM initialization values for 8-column chips
671 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200672#define CONFIG_SYS_OR1_8COL ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
Heiko Schocherfa230442006-12-21 17:17:02 +0100673 ORxS_BPD_4 |\
674 ORxS_ROWST_PBI1_A7 |\
675 ORxS_NUMR_12)
676
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200677#define CONFIG_SYS_PSDMR_8COL (PSDMR_PBI |\
Heiko Schocherfa230442006-12-21 17:17:02 +0100678 PSDMR_SDAM_A15_IS_A5 |\
679 PSDMR_BSMA_A12_A14 |\
680 PSDMR_SDA10_PBI1_A8 |\
681 PSDMR_RFRC_7_CLK |\
682 PSDMR_PRETOACT_2W |\
683 PSDMR_ACTTORW_2W |\
684 PSDMR_LDOTOPRE_1C |\
685 PSDMR_WRC_2C |\
686 PSDMR_EAMUX |\
687 PSDMR_BUFCMD |\
688 PSDMR_CL_2)
689
690
691/* SDRAM initialization values for 9-column chips
692 */
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200693#define CONFIG_SYS_OR1_9COL ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
Heiko Schocherfa230442006-12-21 17:17:02 +0100694 ORxS_BPD_4 |\
695 ORxS_ROWST_PBI1_A5 |\
696 ORxS_NUMR_13)
697
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200698#define CONFIG_SYS_PSDMR_9COL (PSDMR_PBI |\
Heiko Schocherfa230442006-12-21 17:17:02 +0100699 PSDMR_SDAM_A16_IS_A5 |\
700 PSDMR_BSMA_A12_A14 |\
701 PSDMR_SDA10_PBI1_A7 |\
702 PSDMR_RFRC_7_CLK |\
703 PSDMR_PRETOACT_2W |\
704 PSDMR_ACTTORW_2W |\
705 PSDMR_LDOTOPRE_1C |\
706 PSDMR_WRC_2C |\
707 PSDMR_EAMUX |\
708 PSDMR_BUFCMD |\
709 PSDMR_CL_2)
710
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200711#define CONFIG_SYS_OR1_10COL ((~(CONFIG_SYS_GLOBAL_SDRAM_LIMIT-1) & ORxS_SDAM_MSK) |\
Heiko Schocherfa230442006-12-21 17:17:02 +0100712 ORxS_BPD_4 |\
713 ORxS_ROWST_PBI1_A4 |\
714 ORxS_NUMR_13)
715
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200716#define CONFIG_SYS_PSDMR_10COL (PSDMR_PBI |\
Heiko Schocherfa230442006-12-21 17:17:02 +0100717 PSDMR_SDAM_A17_IS_A5 |\
718 PSDMR_BSMA_A12_A14 |\
719 PSDMR_SDA10_PBI1_A4 |\
720 PSDMR_RFRC_6_CLK |\
721 PSDMR_PRETOACT_2W |\
722 PSDMR_ACTTORW_2W |\
723 PSDMR_LDOTOPRE_1C |\
724 PSDMR_WRC_2C |\
725 PSDMR_EAMUX |\
726 PSDMR_BUFCMD |\
727 PSDMR_CL_2)
728
Heiko Schocherfa230442006-12-21 17:17:02 +0100729#define PSDMR_RFRC_66MHZ_SINGLE 0x00028000 /* PSDMR[RFRC] at 66 MHz single mode */
730#define PSDMR_RFRC_100MHZ_SINGLE 0x00030000 /* PSDMR[RFRC] at 100 MHz single mode */
731#define PSDMR_RFRC_133MHZ_SINGLE 0x00030000 /* PSDMR[RFRC] at 133 MHz single mode */
732#define PSDMR_RFRC_66MHZ_60X 0x00030000 /* PSDMR[RFRC] at 66 MHz 60x mode */
733#define PSDMR_RFRC_100MHZ_60X 0x00028000 /* PSDMR[RFRC] at 100 MHz 60x mode */
734#define PSDMR_RFRC_DEFAULT PSDMR_RFRC_133MHZ_SINGLE /* PSDMR[RFRC] default value */
735
736#define PSDMR_PRETOACT_66MHZ_SINGLE 0x00002000 /* PSDMR[PRETOACT] at 66 MHz single mode */
737#define PSDMR_PRETOACT_100MHZ_SINGLE 0x00002000 /* PSDMR[PRETOACT] at 100 MHz single mode */
738#define PSDMR_PRETOACT_133MHZ_SINGLE 0x00002000 /* PSDMR[PRETOACT] at 133 MHz single mode */
739#define PSDMR_PRETOACT_66MHZ_60X 0x00001000 /* PSDMR[PRETOACT] at 66 MHz 60x mode */
740#define PSDMR_PRETOACT_100MHZ_60X 0x00001000 /* PSDMR[PRETOACT] at 100 MHz 60x mode */
741#define PSDMR_PRETOACT_DEFAULT PSDMR_PRETOACT_133MHZ_SINGLE /* PSDMR[PRETOACT] default value */
742
743#define PSDMR_WRC_66MHZ_SINGLE 0x00000020 /* PSDMR[WRC] at 66 MHz single mode */
744#define PSDMR_WRC_100MHZ_SINGLE 0x00000020 /* PSDMR[WRC] at 100 MHz single mode */
745#define PSDMR_WRC_133MHZ_SINGLE 0x00000010 /* PSDMR[WRC] at 133 MHz single mode */
746#define PSDMR_WRC_66MHZ_60X 0x00000010 /* PSDMR[WRC] at 66 MHz 60x mode */
747#define PSDMR_WRC_100MHZ_60X 0x00000010 /* PSDMR[WRC] at 100 MHz 60x mode */
748#define PSDMR_WRC_DEFAULT PSDMR_WRC_133MHZ_SINGLE /* PSDMR[WRC] default value */
749
750#define PSDMR_BUFCMD_66MHZ_SINGLE 0x00000000 /* PSDMR[BUFCMD] at 66 MHz single mode */
751#define PSDMR_BUFCMD_100MHZ_SINGLE 0x00000000 /* PSDMR[BUFCMD] at 100 MHz single mode */
752#define PSDMR_BUFCMD_133MHZ_SINGLE 0x00000004 /* PSDMR[BUFCMD] at 133 MHz single mode */
753#define PSDMR_BUFCMD_66MHZ_60X 0x00000000 /* PSDMR[BUFCMD] at 66 MHz 60x mode */
754#define PSDMR_BUFCMD_100MHZ_60X 0x00000000 /* PSDMR[BUFCMD] at 100 MHz 60x mode */
755#define PSDMR_BUFCMD_DEFAULT PSDMR_BUFCMD_133MHZ_SINGLE /* PSDMR[BUFCMD] default value */
756
Jean-Christophe PLAGNIOL-VILLARD6d0f6bc2008-10-16 15:01:15 +0200757#endif /* CONFIG_SYS_RAMBOOT */
Heiko Schocherfa230442006-12-21 17:17:02 +0100758
759#endif /* __CONFIG_H */